coreboot-gerrit January 2021

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Change in coreboot[master]: mb/google/dedede/var/boten: Update LTE GPIO configuration
by Henry Sun (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Evan Green, Tim Wawrzynczak, Karthik Ramasubramanian. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48623 ) Change subject: mb/google/dedede/var/boten: Update LTE GPIO configuration ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: CL verified by ODM in related issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/48623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8676da6186559288aabe078b6158fc01075c7b41 Gerrit-Change-Number: 48623 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 14:38:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell: acpi_wake_source()
by build bot (Jenkins) (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49356 ) Change subject: soc/intel/broadwell: acpi_wake_source() ...................................................................... Patch Set 1: (4 comments) File src/soc/intel/baytrail/ramstage.c: https://review.coreboot.org/c/coreboot/+/49356/comment/a5eaef5f_2cc22dad PS1, Line 126: if (!ps || !gnvs) spaces required around that '||' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/49356/comment/7fd40946_bb6545b1 PS1, Line 126: if (!ps || !gnvs) space required before that '!' (ctx:VxV) File src/soc/intel/broadwell/ramstage.c: https://review.coreboot.org/c/coreboot/+/49356/comment/2391e946_83357cd5 PS1, Line 22: if (!ps || !gnvs) spaces required around that '||' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/49356/comment/32b3a15e_05e858ea PS1, Line 22: if (!ps || !gnvs) space required before that '!' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/49356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c277a4b8536fd79bda040d4ada9b0c454399b09 Gerrit-Change-Number: 49356 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 14:09:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] ACPI: Unify acpi_wake_source and CBMEM_ID_POWER_STATE
by Kyösti Mälkki (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49357 ) Change subject: [WIP] ACPI: Unify acpi_wake_source and CBMEM_ID_POWER_STATE ...................................................................... [WIP] ACPI: Unify acpi_wake_source and CBMEM_ID_POWER_STATE Change-Id: Ia6688ec7abf16ed15f3db5da41b6e5ed73ffbc7d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/ramstage.c M src/soc/intel/broadwell/ramstage.c 2 files changed, 0 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/49357/1 diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index f2c9cdc..ffb9675 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -2,7 +2,6 @@ #include <arch/cpu.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> @@ -16,7 +15,6 @@ #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/msr.h> -#include <soc/nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -116,33 +114,6 @@ attrs->bclk_khz = bus_freq_khz(); } -/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ -static void s3_save_acpi_wake_source(void) -{ - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - struct global_nvs *gnvs = acpi_get_gnvs(); - uint16_t pm1; - - if (!ps || !gnvs) - return; - - pm1 = ps->pm1_sts & ps->pm1_en; - - /* Scan for first set bit in PM1 */ - for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) { - if (pm1 & 1) - break; - pm1 >>= 1; - } - - /* If unable to determine then return -1 */ - if (gnvs->pm1i >= 16) - gnvs->pm1i = -1; - - printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n", - gnvs->pm1i); -} - static void baytrail_enable_2x_refresh_rate(void) { u32 reg; @@ -164,10 +135,6 @@ /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); - /* Indicate S3 resume to rest of ramstage. */ - if (acpi_is_wakeup_s3()) - s3_save_acpi_wake_source(); - /* Run reference code. */ baytrail_run_reference_code(); diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 2e50555..915bfd5 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -1,72 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> -#include <cbmem.h> -#include <console/console.h> -#include <device/device.h> -#include <string.h> -#include <soc/nvs.h> -#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/intel/broadwell/chip.h> -/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ -static void save_acpi_wake_source(void) -{ - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - struct global_nvs *gnvs = acpi_get_gnvs(); - uint16_t pm1; - int gpe_reg; - - if (!ps || !gnvs) - return; - - pm1 = ps->pm1_sts & ps->pm1_en; - - /* Scan for first set bit in PM1 */ - for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) { - if (pm1 & 1) - break; - pm1 >>= 1; - } - - /* If unable to determine then return -1 */ - if (gnvs->pm1i >= 16) - gnvs->pm1i = -1; - - /* Scan for first set bit in GPE registers */ - gnvs->gpei = -1; - for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) { - u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg]; - int start = gpe_reg * GPE0_REG_SIZE; - int end = start + GPE0_REG_SIZE; - - if (gpe == 0) { - if (!gnvs->gpei) - gnvs->gpei = end; - continue; - } - - for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { - if (gpe & 1) - break; - gpe >>= 1; - } - } - - /* If unable to determine then return -1 */ - if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE)) - gnvs->gpei = -1; - - printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", - gnvs->pm1i, gnvs->gpei); -} - void broadwell_init_pre_device(void *chip_info) { - if (acpi_is_wakeup_s3()) - save_acpi_wake_source(); - broadwell_run_reference_code(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6688ec7abf16ed15f3db5da41b6e5ed73ffbc7d Gerrit-Change-Number: 49357 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: acpi_wake_source()
by Kyösti Mälkki (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49356 ) Change subject: soc/intel/broadwell: acpi_wake_source() ...................................................................... soc/intel/broadwell: acpi_wake_source() Change-Id: I5c277a4b8536fd79bda040d4ada9b0c454399b09 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/ramstage.c M src/soc/intel/broadwell/ramstage.c 2 files changed, 11 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/49356/1 diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index e199e9f..f2c9cdc 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -117,12 +117,13 @@ } /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ -static void s3_save_acpi_wake_source(struct global_nvs *gnvs) +static void s3_save_acpi_wake_source(void) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + struct global_nvs *gnvs = acpi_get_gnvs(); uint16_t pm1; - if (!ps) + if (!ps || !gnvs) return; pm1 = ps->pm1_sts & ps->pm1_en; @@ -142,14 +143,6 @@ gnvs->pm1i); } -static void s3_resume_prepare(void) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - - if (gnvs && acpi_is_wakeup_s3()) - s3_save_acpi_wake_source(gnvs); -} - static void baytrail_enable_2x_refresh_rate(void) { u32 reg; @@ -172,7 +165,8 @@ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); /* Indicate S3 resume to rest of ramstage. */ - s3_resume_prepare(); + if (acpi_is_wakeup_s3()) + s3_save_acpi_wake_source(); /* Run reference code. */ baytrail_run_reference_code(); diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index b4f38a5..2e50555 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -12,13 +12,14 @@ #include <soc/intel/broadwell/chip.h> /* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ -static void save_acpi_wake_source(struct global_nvs *gnvs) +static void save_acpi_wake_source(void) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + struct global_nvs *gnvs = acpi_get_gnvs(); uint16_t pm1; int gpe_reg; - if (!ps) + if (!ps || !gnvs) return; pm1 = ps->pm1_sts & ps->pm1_en; @@ -62,16 +63,10 @@ gnvs->pm1i, gnvs->gpei); } -static void s3_resume_prepare(void) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - - if (gnvs && acpi_is_wakeup_s3()) - save_acpi_wake_source(gnvs); -} - void broadwell_init_pre_device(void *chip_info) { - s3_resume_prepare(); + if (acpi_is_wakeup_s3()) + save_acpi_wake_source(); + broadwell_run_reference_code(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/49356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c277a4b8536fd79bda040d4ada9b0c454399b09 Gerrit-Change-Number: 49356 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add option to stub out Global NVS
by Lance Zhao (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Martin Roth, Angel Pons. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49278 ) Change subject: acpi: Add option to stub out Global NVS ...................................................................... Patch Set 1: (1 comment) File src/acpi/gnvs.c: https://review.coreboot.org/c/coreboot/+/49278/comment/7192589c_6f0c6607 PS1, Line 14: if (CONFIG(ACPI_NO_GLOBAL_NVS_SUPPORT)) : return NULL; Why not totally exclude the gnvs.c file instead of return NULL? -- To view, visit https://review.coreboot.org/c/coreboot/+/49278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie31f02c9e279e47ff10562bb077367d4e33f4dd9 Gerrit-Change-Number: 49278 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 14:02:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboards: Drop GNVS OSYS
by Kyösti Mälkki (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Damien Zammit, Angel Pons. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49353 ) Change subject: mainboards: Drop GNVS OSYS ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49353/comment/bbefdd1f_08314e67 PS1, Line 7: mainboards: Drop GNVS OSYS > Some ASL depends on the OSYS value, though. Yes, CB:49350 is related, faking the OSYS to show HPET is wrong. -- To view, visit https://review.coreboot.org/c/coreboot/+/49353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c Gerrit-Change-Number: 49353 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 13:40:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE`
by Patrick Georgi (Code Review) 12 Jan '21

12 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49282 ) Change subject: soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE` ...................................................................... soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE` It is only used in one place, and there's two other equivalent macros. Change-Id: I7c8241e28f688abd2df8180559dd02ee441c7023 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49282 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/pmc.c 2 files changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index fb5aafd..c252ca1 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -12,7 +12,6 @@ /* Southbridge internal device IO BARs (Set to match FSP settings) */ #define DEFAULT_PMBASE 0x1800 -#define DEFAULT_ACPI_BASE DEFAULT_PMBASE #define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400 diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 8755825..258e6a4 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -16,7 +16,7 @@ /* While we read BAR dynamically in case it changed, let's * initialize it with a same value */ -static u16 acpi_base = DEFAULT_ACPI_BASE; +static u16 acpi_base = ACPI_BASE_ADDRESS; static u32 pwrm_base = DEFAULT_PWRM_BASE; static void pch_power_options(struct device *dev) { /* TODO */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/49282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8241e28f688abd2df8180559dd02ee441c7023 Gerrit-Change-Number: 49282 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: pmic: allow to support Vreq for scp
by hsin-hsiung wang (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Hung-Te Lin. hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49355 ) Change subject: WIP: soc/mediatek/mt8192: pmic: allow to support Vreq for scp ...................................................................... WIP: soc/mediatek/mt8192: pmic: allow to support Vreq for scp Add the settings of Vreq to provide the voltage of scp BUG=none BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I68302715ae804fed11bb54f4dfc4e90cde5224df --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/49355/1 diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index 2249915..ae44177 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -182,6 +182,13 @@ {0x202C, 0x8, 0xC, 0}, {0x208C, 0x100, 0xF00, 0}, {0x209C, 0x80, 0x1E0, 0}, + /* + * BUCK_VGPU11_OP_MODE/CFG/EN + * add the setting of Vreq for scp usage + */ + {0x15a0, 0x0, 0x1, 11}, + {0x159a, 0x0, 0x1, 11}, + {0x1594, 0x1, 0x1, 11}, }; static const struct pmic_setting lp_setting[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/49355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68302715ae804fed11bb54f4dfc4e90cde5224df Gerrit-Change-Number: 49355 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: pmic: enable pwrkey long-press shutdown setting
by hsin-hsiung wang (Code Review) 12 Jan '21

12 Jan '21

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49354 ) Change subject: soc/mediatek/mt8192: pmic: enable pwrkey long-press shutdown setting ...................................................................... soc/mediatek/mt8192: pmic: enable pwrkey long-press shutdown setting Update the settings of long press shutdown to avoid rtc alarm boot. BUG=b:174546890 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I0841e55674f6b26f355ab678a73d4060fe93f27c --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/49354/1 diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index 7ba39b4..2249915 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -39,7 +39,11 @@ {0xA08, 0x1, 0x1, 0}, {0xA0C, 0x300, 0x300, 0}, {0xA10, 0x0, 0x4000, 0}, - {0xA12, 0x1E0, 0x1E0, 0}, + /* + * RG_STRUP_LONG_PRESS_EXT_SEL + * only allow pwrkey boot after long-press shutdown. + */ + {0xA12, 0x1F2, 0x1F3, 0}, {0xA24, 0xFFFF, 0xFFFF, 0}, {0xA26, 0xFFE0, 0xFFE0, 0}, {0xA2C, 0xC0DF, 0xC0DF, 0}, -- To view, visit https://review.coreboot.org/c/coreboot/+/49354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0841e55674f6b26f355ab678a73d4060fe93f27c Gerrit-Change-Number: 49354 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Fix toctree and remove dead links
by Patrick Georgi (Code Review) 12 Jan '21

12 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49292 ) Change subject: Documentation: Fix toctree and remove dead links ...................................................................... Documentation: Fix toctree and remove dead links Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49292 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/drivers/index.md M Documentation/mainboard/index.md M Documentation/soc/intel/icelake/iceLake_coreboot_development.md M Documentation/soc/intel/index.md 4 files changed, 4 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 508beaf..40d747d 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -4,7 +4,9 @@ and plugin devices, significantly reducing integration complexity and they allow to easily reuse existing code accross platforms. +* [Intel DPTF](dptf.md) * [IPMI KCS](ipmi_kcs.md) * [SMMSTORE](smmstore.md) * [SoundWire](soundwire.md) * [SMMSTOREv2](smmstorev2.md) +* [USB4 Retimer](retimer.md) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 1f8f6bc2..b558760 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -16,6 +16,7 @@ ## ASUS +- [A88XM-E](asus/a88xm-e.md) - [F2A85-M](asus/f2a85-m.md) - [P5Q](asus/p5q.md) - [P8H61-M LX](asus/p8h61-m_lx.md) diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md index 5f8e279..2147331 100644 --- a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md +++ b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md @@ -20,11 +20,6 @@ :doc:`../../../mainboard/intel/icelake_rvp` ``` -3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google - ```eval_rst - :doc:`../../../mainboard/google/dragonegg` - ``` - ### Summary: * SoC is Ice Lake. * Reference platform is icelake_rvp. diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index 5c7239a..71e427e 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -11,4 +11,4 @@ - [Microcode Updates](microcode.md) - [Firmware Interface Table](fit.md) - [Apollolake](apollolake/index.md) -- [CSE FW Update](cse_fw_update/cse_fw_update_model.md) +- [CSE FW Update](cse_fw_update/cse_fw_update.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/49292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068 Gerrit-Change-Number: 49292 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit January 2021