coreboot-gerrit September 2020

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Change in coreboot[master]: mb/google/dedede/var/boten: Add audio configuration
by Angel Pons (Code Review) 10 Sep '20

10 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44920 ) Change subject: mb/google/dedede/var/boten: Add audio configuration ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5 Gerrit-Change-Number: 44920 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ben Zhang <benzh(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 09 Sep 2020 23:35:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/imc: Drop unused code
by Angel Pons (Code Review) 10 Sep '20

10 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45046 ) Change subject: soc/intel/common/block/imc: Drop unused code ...................................................................... soc/intel/common/block/imc: Drop unused code Nothing uses this code anymore. Change-Id: I5da1020597c126a40b015beb6e43fb0168aa330f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/soc/intel/common/block/imc/Kconfig D src/soc/intel/common/block/imc/Makefile.inc D src/soc/intel/common/block/imc/imc.c 3 files changed, 0 insertions(+), 173 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/45046/1 diff --git a/src/soc/intel/common/block/imc/Kconfig b/src/soc/intel/common/block/imc/Kconfig deleted file mode 100644 index 490b80e..0000000 --- a/src/soc/intel/common/block/imc/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -config SOC_INTEL_COMMON_BLOCK_IMC - bool - depends on MMCONF_SUPPORT - default n - help - Driver for communication with Integrated Memory Controller that is found on - some Xeon server processors. diff --git a/src/soc/intel/common/block/imc/Makefile.inc b/src/soc/intel/common/block/imc/Makefile.inc deleted file mode 100644 index a6bc985..0000000 --- a/src/soc/intel/common/block/imc/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_IMC),y) - -bootblock-y += imc.c -romstage-y += imc.c -verstage-y += imc.c -postcar-y += imc.c -ramstage-y += imc.c - -endif diff --git a/src/soc/intel/common/block/imc/imc.c b/src/soc/intel/common/block/imc/imc.c deleted file mode 100644 index 57c7fa8..0000000 --- a/src/soc/intel/common/block/imc/imc.c +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Please note: the driver uses MMIO PCIe register access. IO based access will - * not work. - */ - -#include <console/console.h> -#include <device/pci_ops.h> -#include <intelblocks/imc.h> -#include <soc/pci_devs.h> -#include <timer.h> - -#define IMC_SMBUS_TIMEOUT_MS 100 -#define IMC_SMBCNTL_DTI_TSOD 0x3 -#define IMC_SMBCNTL_DTI_EEPROM 0xa -#define IMC_SMBCNTL_DTI_WP_EEPROM 0x6 - -#define SMBSTAT(i) (0x180 + 0x10 * i) -#define SMBCMD(i) (0x184 + 0x10 * i) -#define SMBCNTL(i) (0x188 + 0x10 * i) - -#define SMBSTAT_RDO (1u << 31) /* Read Data Valid */ -#define SMBSTAT_WOD (1u << 30) /* Write Operation Done */ -#define SMBSTAT_SBE (1u << 29) /* SMBus Error */ -#define SMBSTAT_SMB_BUSY (1u << 28) /* SMBus Busy State */ - -#define SMBCMD_TRIGGER (1u << 31) /* CMD Trigger */ -#define SMBCMD_PNTR_SEL (1u << 30) /* HW polls TSOD with pointer */ -#define SMBCMD_WORD_ACCESS (1u << 29) /* word (vs byte) access */ -#define SMBCMD_TYPE_MASK (3u << 27) /* Mask for access type */ -#define SMBCMD_TYPE_READ (0u << 27) /* Read */ -#define SMBCMD_TYPE_WRITE (1u << 27) /* Write */ -#define SMBCMD_TYPE_PNTR_WRITE (3u << 27) /* Write to pointer */ -#define SMBCMD_SA_MASK (7u << 24) /* Slave Address high bits */ -#define SMBCMD_SA_SHIFT 24 -#define SMBCMD_BA_MASK 0xff0000 /* Bus Txn address */ -#define SMBCMD_BA_SHIFT 16 -#define SMBCMD_WDATA_MASK 0xffff /* data to write */ - -#define SMBCNTL_DTI_MASK 0xf0000000 /* Slave Address low bits */ -#define SMBCNTL_DTI_SHIFT 28 /* Slave Address low bits */ -#define SMBCNTL_CKOVRD (1u << 27) /* # Clock Override */ -#define SMBCNTL_DIS_WRT (1u << 26) /* Disable Write (sadly) */ -#define SMBCNTL_SOFT_RST (1u << 10) /* Soft Reset */ -#define SMBCNTL_TSOD_POLL_EN (1u << 8) /* TSOD Polling Enable */ - -static bool poll_ready(pci_devfn_t dev, enum memory_controller_id mcid, uint32_t *status) -{ - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, IMC_SMBUS_TIMEOUT_MS); - - do { - *status = pci_mmio_read_config32(dev, SMBSTAT(mcid)); - if (!(*status & SMBSTAT_SMB_BUSY)) - break; - } while (!stopwatch_expired(&sw)); - - return (!(*status & SMBSTAT_SMB_BUSY)); -} - -static bool claim_controller(pci_devfn_t dev, enum memory_controller_id mcid) -{ - uint32_t cntl, status; - - cntl = pci_mmio_read_config32(dev, SMBCNTL(mcid)); - cntl &= ~SMBCNTL_TSOD_POLL_EN; - cntl &= ~SMBCNTL_DIS_WRT; - pci_mmio_write_config32(dev, SMBCNTL(mcid), cntl); - - return poll_ready(dev, mcid, &status); -} - - -static void release_controller(pci_devfn_t dev, enum memory_controller_id mcid) -{ - uint32_t cntl, status; - - cntl = pci_mmio_read_config32(dev, SMBCNTL(mcid)); - cntl |= SMBCNTL_TSOD_POLL_EN; - pci_mmio_write_config32(dev, SMBCNTL(mcid), cntl); - - poll_ready(dev, mcid, &status); -} - -int imc_smbus_spd_xfer(pci_devfn_t dev, uint8_t slave_addr, uint8_t bus_addr, - enum device_type_id dti, enum access_width width, - enum memory_controller_id mcid, enum smbus_command cmd, void *data) -{ - int ret = -1; - uint32_t cmdbits = 0, stat = 0, cntlbits = 0, data_mask = 0; - uint16_t wdata = 0, rdata = 0; - - /* slaves addresses are 7 bits length */ - if (slave_addr > (1 << 7) - 1) { - printk(BIOS_ERR, "invalid SMBus address, aborting xfer\n"); - return -1; - } - - if (!claim_controller(dev, mcid)) { - printk(BIOS_ERR, "ayee! couldn't claim controller, giving up xfer\n"); - return -1; - } - - cmdbits = (slave_addr << SMBCMD_SA_SHIFT); - cmdbits |= (bus_addr << SMBCMD_BA_SHIFT); - - if (cmd == IMC_WRITE) { - wdata = (width == IMC_DATA_BYTE ? read8(data) : cpu_to_be16(read16(data))); - cmdbits |= (SMBCMD_TYPE_WRITE | wdata); - } else { - cmdbits |= SMBCMD_TYPE_READ; - } - - if (width == IMC_DATA_WORD) { - cmdbits |= SMBCMD_WORD_ACCESS; - data_mask = 0xffff; - } else { - data_mask = 0xff; - } - - cntlbits = pci_mmio_read_config32(dev, SMBCNTL(mcid)); - cntlbits &= ~SMBCNTL_DTI_MASK; - cntlbits |= (dti << SMBCNTL_DTI_SHIFT); - - pci_mmio_write_config32(dev, SMBCNTL(mcid), cntlbits); - - /* Pull the trigger */ - cmdbits |= SMBCMD_TRIGGER; - pci_mmio_write_config32(dev, SMBCMD(mcid), cmdbits); - - if (!poll_ready(dev, mcid, &stat)) { - printk(BIOS_ERR, "IMC xfer failed for slave %x", slave_addr); - ret = -1; - goto cleanup; - } - - if (stat & SMBSTAT_SBE) { - ret = -1; - goto cleanup; - } - - if (cmd == IMC_READ) { - rdata = stat & data_mask; - if (width == IMC_DATA_WORD) - write16(data, cpu_to_be16(rdata)); - else - write8(data, rdata); - } - - ret = 0; -cleanup: - release_controller(dev, SMBSTAT(mcid)); - - return ret; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5da1020597c126a40b015beb6e43fb0168aa330f Gerrit-Change-Number: 45046 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: GPIO: Add I2S configuration for google/trogdor
by Ravi kumar (Code Review) 10 Sep '20

10 Sep '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41428 ) Change subject: sc7180: GPIO: Add I2S configuration for google/trogdor ...................................................................... sc7180: GPIO: Add I2S configuration for google/trogdor Configure GPIO pins as I2S mode for audio speaker. The audio speaker does not work on Trogdor revision 1, as the layout was changed. Developer/Reviewer reference, be aware of this issue: https://partnerissuetracker.corp.google.com/issues/146533652 Change-Id: Ia4bbfea591a3231640b53e64f0e4e9d43c4437a3 --- M src/mainboard/google/trogdor/mainboard.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/41428/1 diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index c82eaa0..5081db9 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -19,13 +19,13 @@ { gpio_configure(GPIO(49), GPIO49_FUNC_MI2S_1_SCK, - GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); gpio_configure(GPIO(50), GPIO50_FUNC_MI2S_1_WS, - GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); gpio_configure(GPIO(51), GPIO51_FUNC_MI2S_1_DATA0, - GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); } static void load_qup_fw(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/41428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4bbfea591a3231640b53e64f0e4e9d43c4437a3 Gerrit-Change-Number: 41428 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: lib/spd_bin: Only build when CONFIG option is set
by Marc Jones (Code Review) 10 Sep '20

10 Sep '20

Marc Jones has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/22575 ) Change subject: lib/spd_bin: Only build when CONFIG option is set ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/22575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a4d810199c96912d13737046e6041b74315164 Gerrit-Change-Number: 22575 Gerrit-PatchSet: 4 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: sc7180: clock: Add display external clock in coreboot
by Ravi kumar (Code Review) 10 Sep '20

10 Sep '20

Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39612 to review the following change. Change subject: sc7180: clock: Add display external clock in coreboot ...................................................................... sc7180: clock: Add display external clock in coreboot Add support for display external clock in coreboot for SC7180. Tested: Display clocks are configured. Change-Id: Ida222890252b80db738fa1f685b212b3f7c6e689 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h M src/soc/qualcomm/sc7180/include/soc/clock.h 3 files changed, 145 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/39612/1 diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 2eb5830..f9ddeee 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -18,10 +18,12 @@ #include <delay.h> #include <device/mmio.h> #include <soc/clock.h> +#include <string.h> #include <timer.h> #include <types.h> #define DIV(div) (2 * div - 1) +#define HALF_DIVIDER(div2x) (div2x ? (div2x - 1) : 0) struct clock_config qup_cfg[] = { { @@ -117,6 +119,30 @@ }, }; +struct mdss_clock_config mdss_extclk_config[] = { + { + "disp_cc_mdss_esc0_clk", + mdss_reg_ptr(struct sc7180_disp_cc, esc0_rcgr, DISP_CC_BASE), + mdss_reg_ptr(struct sc7180_disp_cc, esc0_cbcr, DISP_CC_BASE), + }, + { + "disp_cc_mdss_pclk0_clk", + mdss_reg_ptr(struct sc7180_disp_cc, pclk0_rcgr, DISP_CC_BASE), + mdss_reg_ptr(struct sc7180_disp_cc, pclk0_cbcr, DISP_CC_BASE), + }, + { + "disp_cc_mdss_byte0_clk", + mdss_reg_ptr(struct sc7180_disp_cc, byte0_rcgr, DISP_CC_BASE), + mdss_reg_ptr(struct sc7180_disp_cc, byte0_cbcr, DISP_CC_BASE), + }, + { + "disp_cc_mdss_byte0_intf_clk", + mdss_reg_ptr(struct sc7180_disp_cc, byte0_rcgr, DISP_CC_BASE), + mdss_reg_ptr(struct sc7180_disp_cc, byte0_intf_cbcr, + DISP_CC_BASE), + }, +}; + static int clock_configure_gpll0(void) { setbits32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); @@ -336,6 +362,90 @@ printk(BIOS_INFO, "L3 Frequency bumped to 1.2096(GHz)\n"); } +static void * mdss_clock_get_reg_addr(const char *clk_name, + uint32_t mdss_clk_type) +{ + void *reg_addr = NULL; + int i; + int num_clks; + + num_clks = sizeof(mdss_extclk_config) / + sizeof(struct mdss_clock_config); + + for (i = 0; i < num_clks; i++) { + if (strcmp(mdss_extclk_config[i].clk_name, clk_name) != 0) + continue; + + if (mdss_clk_type == 0) + reg_addr = (void *)mdss_extclk_config[i].rcgr; + else if(mdss_clk_type == 1) + reg_addr = (void *)mdss_extclk_config[i].cbcr; + } + return reg_addr; +} + +int mdss_clock_configure(const char *clk_name, uint32_t source, + uint32_t divider, uint32_t m, uint32_t n, uint32_t d_2) +{ + struct clock_config mdss_clk_cfg; + struct sc7180_mdss_rcg *mdss_clk; + uint32_t reg_val; + + /* Find out the RCGR address corresponding to the given clock */ + mdss_clk = mdss_clock_get_reg_addr(clk_name, 0); + + /* clk_name not found in the available clock list */ + if (mdss_clk == NULL) + return -1; + + /* Initialize it with received arguments */ + mdss_clk_cfg.hz = 0; + mdss_clk_cfg.src = source; + mdss_clk_cfg.div = HALF_DIVIDER(divider); + mdss_clk_cfg.m = m; + mdss_clk_cfg.n = n; + mdss_clk_cfg.d_2 = d_2; + + /* configure and set the clock */ + reg_val = (mdss_clk_cfg.src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (mdss_clk_cfg.div << CLK_CTL_CFG_SRC_DIV_SHFT); + + write32(&mdss_clk->cfg, reg_val); + + /* Set m/n/d values for a specific clock */ + if (mdss_clk_cfg.m != 0) { + setbits32(&mdss_clk->cfg, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + write32(&mdss->pclk0_m, mdss_clk_cfg.m & CLK_CTL_RCG_MND_BMSK); + write32(&mdss->pclk0_n, ~(mdss_clk_cfg.n-mdss_clk_cfg.m) & + CLK_CTL_RCG_MND_BMSK); + write32(&mdss->pclk0_d, ~(mdss_clk_cfg.d_2) & + CLK_CTL_RCG_MND_BMSK); + } + + /* Commit config to RCG */ + setbits32(&mdss_clk->cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +int mdss_clock_enable(const char *clk_name, uint32_t clk_on) +{ + void *cbcr; + + /* Find out the RCGR address corresponding to the given clock */ + cbcr = mdss_clock_get_reg_addr(clk_name, 1); + + /* clk_name not found in the available clock list */ + if ((cbcr == NULL) || (clk_on == 0)) + return -1; + + /* Enable clock*/ + clock_enable(cbcr); + + return 0; +} + void clock_init(void) { clock_configure_gpll0(); diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index ee640a2..ff05616 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -26,6 +26,7 @@ #define TLMM_WEST_TILE_BASE 0x03500000 #define SILVER_PLL_BASE 0x18280000 #define L3_PLL_BASE 0x18284000 +#define DISP_CC_BASE 0x0AF00000 /* * QUP SERIAL ENGINE BASE ADDRESSES diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 26e3d09..e42f9b3 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -43,6 +43,9 @@ #define SCALE_FREQ_SHFT 11 +#define mdss_reg_ptr(type, mem, base) \ + ((offsetof(type, mem)) + base) + struct sc7180_clock { u32 cbcr; u32 rcg_cmd; @@ -140,6 +143,33 @@ u32 aoss_cc_apcs_misc; }; +struct sc7180_mdss_rcg { + u32 cmd; + u32 cfg; +}; + +struct sc7180_disp_cc { + u8 _res0[0x2004]; + u32 pclk0_cbcr; + u8 _res1[0x2028 - 0x2008]; + u32 byte0_cbcr; + u32 byte0_intf_cbcr; + u8 _res2[0x2038 - 0x2030]; + u32 esc0_cbcr; + u8 _res3[0x2098 - 0x203C]; + struct sc7180_mdss_rcg pclk0_rcgr; + u32 pclk0_m; + u32 pclk0_n; + u32 pclk0_d; + u8 _res4[0x2110 - 0x20AC]; + struct sc7180_mdss_rcg byte0_rcgr; + u8 _res5[0x2148 - 0x2118]; + struct sc7180_mdss_rcg esc0_rcgr; + u8 _res6[0x10000 - 0x2050]; +}; +check_member(sc7180_disp_cc, byte0_cbcr, 0x2028); +check_member(sc7180_disp_cc, esc0_cbcr, 0x2038); + enum clk_ctl_gpll_user_ctl { CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, @@ -280,6 +310,7 @@ static struct sc7180_aoss *const aoss = (void *)AOSS_CC_BASE; static struct sc7180_apss_clock *const apss_silver = (void *)SILVER_PLL_BASE; static struct sc7180_apss_clock *const apss_l3 = (void *)L3_PLL_BASE; +static struct sc7180_disp_cc *const mdss = (void *)DISP_CC_BASE; void clock_init(void); void clock_reset_aop(void); @@ -288,5 +319,8 @@ void clock_configure_qup(int qup, uint32_t hz); void clock_enable_qup(int qup); void clock_configure_dfsr(int qup); +int mdss_clock_configure(const char *clk_name, uint32_t source, + uint32_t divider, uint32_t m, uint32_t n, uint32_t d); +int mdss_clock_enable(const char *sName, uint32_t clk_on); #endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/39612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida222890252b80db738fa1f685b212b3f7c6e689 Gerrit-Change-Number: 39612 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

6 20

Change in coreboot[master]: trogdor: SoC makefile blob support
by Julius Werner (Code Review) 10 Sep '20

10 Sep '20

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: trogdor: SoC makefile blob support ...................................................................... trogdor: SoC makefile blob support Following blobs will includes with SoC makefile: * AOP * BOOT * QTISECLIB * QCSEC * QUPV3FW Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Signed-off-by: Ashwin Kumar <ashk(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35508 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/qualcomm/sc7180/Makefile.inc 1 file changed, 78 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 4961d24..4f2a311 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -65,6 +65,84 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include CPPFLAGS_common += -Isrc/soc/qualcomm/common/include +BL31_MAKEARGS += PLAT=sc7180 + +SC7180_BLOB := $(top)/3rdparty/qc_blobs/sc7180 + ################################################################################ +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +QCSDI_FILE := $(SC7180_BLOB)/boot/QcSdi.elf +QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi +$(QCSDI_CBFS)-file := $(QCSDI_FILE) +$(QCSDI_CBFS)-type := stage +$(QCSDI_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(QCSDI_CBFS) +endif + +################################################################################ +QCLIB_FILE := $(SC7180_BLOB)/boot/QcLib.elf +QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib +$(QCLIB_CBFS)-file := $(QCLIB_FILE) +$(QCLIB_CBFS)-type := stage +$(QCLIB_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(QCLIB_CBFS) + +################################################################################ +PMIC_FILE := $(SC7180_BLOB)/boot/Pmic.bin +PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg +$(PMIC_CBFS)-file := $(PMIC_FILE) +$(PMIC_CBFS)-type := raw +$(PMIC_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(PMIC_CBFS) + +################################################################################ +DCB_FILE := $(SC7180_BLOB)/boot/dcb.bin +DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb +$(DCB_CBFS)-file := $(DCB_FILE) +$(DCB_CBFS)-type := raw +$(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DCB_CBFS) + +################################################################################ +AOP_FILE := $(SC7180_BLOB)/aop/aop.mbn +AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop +$(AOP_CBFS)-file := $(AOP_FILE) +$(AOP_CBFS)-type := payload +$(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(AOP_CBFS) + +################################################################################ +UART_FW_FILE := $(SC7180_BLOB)/qup_fw/uart_fw.bin +UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw +$(UART_FW_CBFS)-file := $(UART_FW_FILE) +$(UART_FW_CBFS)-type := raw +$(UART_FW_CBFS)-compression := none +cbfs-files-y += $(UART_FW_CBFS) + +################################################################################ +SPI_FW_FILE := $(SC7180_BLOB)/qup_fw/spi_fw.bin +SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw +$(SPI_FW_CBFS)-file := $(SPI_FW_FILE) +$(SPI_FW_CBFS)-type := raw +$(SPI_FW_CBFS)-compression := none +cbfs-files-y += $(SPI_FW_CBFS) + +################################################################################ +I2C_FW_FILE := $(SC7180_BLOB)/qup_fw/i2c_fw.bin +I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw +$(I2C_FW_CBFS)-file := $(I2C_FW_FILE) +$(I2C_FW_CBFS)-type := raw +$(I2C_FW_CBFS)-compression := none +cbfs-files-y += $(I2C_FW_CBFS) + +################################################################################ +QC_SEC_FILE := $(SC7180_BLOB)/qc_sec/qc_sec.mbn +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf + @util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.raw.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 64 -c 64 + @printf "\nqgpt.py 4K sector size\n" + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 94 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Saurabh Gorecha <sgorecha(a)codeaurora.org> Gerrit-MessageType: merged

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Change in coreboot[master]: trogdor: SoC makefile blob support
by Julius Werner (Code Review) 10 Sep '20

10 Sep '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: trogdor: SoC makefile blob support ...................................................................... Patch Set 93: (3 comments) https://review.coreboot.org/c/coreboot/+/35508/76//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35508/76//COMMIT_MSG@7 PS76, Line 7: HACK trogdor: SoC makefile BLOB support HACK > Please make it a statement by adding a verb (in imperative mood). That's not a strict requirement, I think this subject is fine for a patch like this. https://review.coreboot.org/c/coreboot/+/35508/15/src/soc/qualcomm/sc7180/M… File src/soc/qualcomm/sc7180/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35508/15/src/soc/qualcomm/sc7180/M… PS15, Line 102: DCB_FILE := $(SC7180_BLOB)/600E_0100_1_1_dcb.bin > Sorry, I don't understand what you mean here? QcLib doesn't ever get to see this filename, all it ge […] Done https://review.coreboot.org/c/coreboot/+/35508/78/src/soc/qualcomm/sc7180/M… File src/soc/qualcomm/sc7180/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35508/78/src/soc/qualcomm/sc7180/M… PS78, Line 79: SC7180_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/sc7180 > Now that CB:42548 has landed, please rewrite this to access $(top)/3rdparty/qc_blobs instead and tak […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 93 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Saurabh Gorecha <sgorecha(a)codeaurora.org> Gerrit-Comment-Date: Wed, 09 Sep 2020 22:07:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Fix GPP_E12 definition
by Nick Vaccaro (Code Review) 09 Sep '20

09 Sep '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45197 ) Change subject: mb/google/volteer: Fix GPP_E12 definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837 Gerrit-Change-Number: 45197 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Sep 2020 21:23:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LP
by Paul Menzel (Code Review) 09 Sep '20

09 Sep '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45200 ) Change subject: util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LP ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c7159d9f48560c41efdfe49f162aef00499d13 Gerrit-Change-Number: 45200 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Sep 2020 20:51:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: add missing special function pads
by Paul Menzel (Code Review) 09 Sep '20

09 Sep '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45211 ) Change subject: soc/intel/cannonlake: add missing special function pads ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3bc1df1a14dbca7c7213577cb2d5b98bb0acf64 Gerrit-Change-Number: 45211 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Sep 2020 20:50:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit September 2020