coreboot-gerrit September 2020

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Change in coreboot[master]: soc/amd/picasso/acpi: Fix hang caused by IVRS
by Jason Glenesk (Code Review) 10 Sep '20

10 Sep '20

Hello Jason Glenesk, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45056 to review the following change. Change subject: soc/amd/picasso/acpi: Fix hang caused by IVRS ...................................................................... soc/amd/picasso/acpi: Fix hang caused by IVRS MADT does not contain an entry for the second ioapic described in the IVRS. Add second ioapic to MADT. Cq-Depend: chrome-internal:3247427, chrome-internal:3247427 BUG=b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Dump MADT and IVRS tables. Cross check ioapic entries in MADT against IVRS. Confirm IVRS contains no alignment gaps/corruption. Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e --- M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/include/soc/smu.h 2 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45056/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 1b9c0ca..dc4a167 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -26,6 +26,7 @@ #include <soc/gpio.h> #include <version.h> #include "chip.h" +#include <soc/smu.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -45,13 +46,29 @@ unsigned int i; uint8_t irq; uint8_t flags; + uint32_t nb_ioapic_base; + uint8_t ioapic_id; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - /* Write Kern IOAPIC, only one */ + /* Lapics use IDs 0 - max logical cpus - 1. FCH ioapic ID uses the next ID*/ + ioapic_id = CONFIG_MAX_CPUS; + + /* Write FCH IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + ioapic_id, IO_APIC_ADDR, 0); + + /* Read base address assigned to gnb ioapic */ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, REG_NB_IOAPIC_BASE); + nb_ioapic_base = pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR); + + /* GNB uses the next ID*/ + ioapic_id++; + + /* Write GNB IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + ioapic_id, nb_ioapic_base, IO_APIC_INTERRUPTS); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index 128f4c4..bc9f4f3 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -12,6 +12,7 @@ #define REG_ADDR_MESG_ID 0x3b10528 #define REG_ADDR_MESG_RESP 0x3b10564 #define REG_ADDR_MESG_ARGS_BASE 0x0b10998 +#define REG_NB_IOAPIC_BASE 0x13b102f0 /* Argument 0-5 indexed locations are contiguous */ #define SMU_NUM_ARGS 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e Gerrit-Change-Number: 45056 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/*/*/irq_tables.c: Drop unneeded empty lines
by HAOUAS Elyes (Code Review) 10 Sep '20

10 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44585 ) Change subject: mb/*/*/irq_tables.c: Drop unneeded empty lines ...................................................................... mb/*/*/irq_tables.c: Drop unneeded empty lines Change-Id: I13bc1c4a1d527276fe3f7f801318cc748e2daf0a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/inagua/irq_tables.c M src/mainboard/amd/persimmon/irq_tables.c M src/mainboard/amd/south_station/irq_tables.c M src/mainboard/amd/union_station/irq_tables.c M src/mainboard/asrock/e350m1/irq_tables.c M src/mainboard/biostar/am1ml/irq_tables.c M src/mainboard/elmex/pcm205400/irq_tables.c M src/mainboard/gizmosphere/gizmo/irq_tables.c M src/mainboard/jetway/nf81-t56n-lf/irq_tables.c M src/mainboard/lippert/frontrunner-af/irq_tables.c M src/mainboard/pcengines/apu1/irq_tables.c 11 files changed, 0 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/44585/1 diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 5d2d253..398594f 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -27,7 +27,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index 5d2d253..398594f 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -27,7 +27,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index 5d2d253..398594f 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -27,7 +27,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index 5d2d253..398594f 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -27,7 +27,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index 5d2d253..398594f 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -27,7 +27,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/biostar/am1ml/irq_tables.c b/src/mainboard/biostar/am1ml/irq_tables.c index a85f715..cc5f34f 100644 --- a/src/mainboard/biostar/am1ml/irq_tables.c +++ b/src/mainboard/biostar/am1ml/irq_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ - #include <arch/pirq_routing.h> const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index 5947b7a..398594f 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -1,13 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include <console/console.h> #include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> - static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, @@ -29,7 +27,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -66,19 +63,14 @@ pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - /* pci bridge */ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) @@ -93,5 +85,4 @@ printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index 5d2d253..398594f 100644 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -27,7 +27,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index 1ef9477..e83c087 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -27,7 +27,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index 5d2d253..398594f 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -27,7 +27,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/pcengines/apu1/irq_tables.c b/src/mainboard/pcengines/apu1/irq_tables.c index 5d2d253..398594f 100644 --- a/src/mainboard/pcengines/apu1/irq_tables.c +++ b/src/mainboard/pcengines/apu1/irq_tables.c @@ -27,7 +27,6 @@ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } -- To view, visit https://review.coreboot.org/c/coreboot/+/44585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13bc1c4a1d527276fe3f7f801318cc748e2daf0a Gerrit-Change-Number: 44585 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/*/*/mainboard.c: Drop unneeded empty lines
by HAOUAS Elyes (Code Review) 10 Sep '20

10 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44589 ) Change subject: mb/*/*/mainboard.c: Drop unneeded empty lines ...................................................................... mb/*/*/mainboard.c: Drop unneeded empty lines Change-Id: Ia61101d4767ed928fcea51ea36be1a97a72063d7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/stout/mainboard.c M src/mainboard/hp/z220_sff_workstation/mainboard.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/lenovo/g505s/mainboard.c M src/mainboard/samsung/lumpy/mainboard.c 6 files changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/44589/1 diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 2a819d3..90f28e7 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -16,8 +16,6 @@ apm_control(APM_CNT_FINALIZE); } - - static void mainboard_init(struct device *dev) { mainboard_ec_init(); diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 29a6923..7f4e29d2 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -17,8 +17,6 @@ ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); } - - static void mainboard_init(struct device *dev) { struct device *ethernet_dev = NULL; diff --git a/src/mainboard/hp/z220_sff_workstation/mainboard.c b/src/mainboard/hp/z220_sff_workstation/mainboard.c index 0d62fae..75dc330 100644 --- a/src/mainboard/hp/z220_sff_workstation/mainboard.c +++ b/src/mainboard/hp/z220_sff_workstation/mainboard.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index a5062e4..e1c02f0 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -19,7 +19,6 @@ #define FAN_SPEED_5625 0 - struct fan_speed { u8 fan_in; u16 fan_speed; diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index 8339626..d900c94 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -26,7 +26,6 @@ if (!acpi_is_wakeup_s3()) pavilion_cold_boot_init(); - } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index fbb7480..cdeaf72 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -19,8 +19,6 @@ send_ec_command(EC_ACPI_ENABLE); } - - static void mainboard_init(struct device *dev) { /* Initialize the Embedded Controller */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia61101d4767ed928fcea51ea36be1a97a72063d7 Gerrit-Change-Number: 44589 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: drivers/spi/tpm: Improve error checking
by Caveh Jalali (Code Review) 10 Sep '20

10 Sep '20

Hello Jes Klinke, Vadim Bendebury, Christian Walter, Tim Wawrzynczak, Duncan Laurie, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45232 to look at the new patch set (#2). Change subject: drivers/spi/tpm: Improve error checking ...................................................................... drivers/spi/tpm: Improve error checking This adds error checking in paths that previously ignored TPM communication errors. We hit this case occasionally during "Checking cr50 for pending updates"; previously we would go down this path and eventually time out using MAX_STATUS_TIMEOUT, which is 2 minutes. Now, we detect the failure and return with an error indication instead of timing out after a long time. The root cause of the communication error is an open issue. BUG=b:168090038 TEST=booted on volteer, observed error handling when "Checking cr50 for pending updates" fails. Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069 --- M src/drivers/spi/tpm/tpm.c 1 file changed, 38 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45232/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069 Gerrit-Change-Number: 45232 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tpm: Improve error checking
by Caveh Jalali (Code Review) 10 Sep '20

10 Sep '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45232 ) Change subject: tpm: Improve error checking ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069 Gerrit-Change-Number: 45232 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Sep 2020 08:50:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths
by Angel Pons (Code Review) 10 Sep '20

10 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44557 ) Change subject: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths ...................................................................... Patch Set 2: Code-Review+1 (3 comments) https://review.coreboot.org/c/coreboot/+/44557/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44557/2//COMMIT_MSG@7 PS2, Line 7: Add I'd use `Hook up` instead https://review.coreboot.org/c/coreboot/+/44557/2//COMMIT_MSG@9 PS2, Line 9: Add Same here https://review.coreboot.org/c/coreboot/+/44557/2//COMMIT_MSG@10 PS2, Line 10: P lowercase `p` -- To view, visit https://review.coreboot.org/c/coreboot/+/44557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f Gerrit-Change-Number: 44557 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Sep 2020 08:15:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Refactor baseboard devicetree
by Angel Pons (Code Review) 10 Sep '20

10 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45179 ) Change subject: mb/google/volteer: Refactor baseboard devicetree ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93 Gerrit-Change-Number: 45179 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 10 Sep 2020 08:10:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/asurada: Add config for hayato
by Yu-Ping Wu (Code Review) 10 Sep '20

10 Sep '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45163 ) Change subject: mb/google/asurada: Add config for hayato ...................................................................... mb/google/asurada: Add config for hayato BUG=b:163789704 TEST=emerge-asurada coreboot BRANCH=none Change-Id: I1a5928fb81356aaf040534e1675933a504aa9f95 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/mainboard/google/asurada/Kconfig M src/mainboard/google/asurada/Kconfig.name 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/45163/1 diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index 51e42a8..894d566 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -35,6 +35,7 @@ config MAINBOARD_PART_NUMBER string default "Asurada" if BOARD_GOOGLE_ASURADA + default "Hayato" if BOARD_GOOGLE_HAYATO config DRIVER_TPM_SPI_BUS hex diff --git a/src/mainboard/google/asurada/Kconfig.name b/src/mainboard/google/asurada/Kconfig.name index df3dc24..6f287e5 100644 --- a/src/mainboard/google/asurada/Kconfig.name +++ b/src/mainboard/google/asurada/Kconfig.name @@ -3,3 +3,7 @@ config BOARD_GOOGLE_ASURADA bool "-> Asurada" select BOARD_GOOGLE_ASURADA_COMMON + +config BOARD_GOOGLE_HAYATO + bool "-> Hayato" + select BOARD_GOOGLE_ASURADA_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/45163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a5928fb81356aaf040534e1675933a504aa9f95 Gerrit-Change-Number: 45163 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/mediatek: Drop unneeded empty lines
by HAOUAS Elyes (Code Review) 10 Sep '20

10 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44596 ) Change subject: soc/mediatek: Drop unneeded empty lines ...................................................................... soc/mediatek: Drop unneeded empty lines Change-Id: Ia419de14614a7a1b583e0870e9ca2fcdc8cf815a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/mediatek/common/include/soc/ddp_common.h M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/mt8173/da9212.c M src/soc/mediatek/mt8173/mt6311.c M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8173/rtc.c M src/soc/mediatek/mt8183/include/soc/ddp.h M src/soc/mediatek/mt8183/pmic_wrap.c M src/soc/mediatek/mt8192/include/soc/gpio.h 9 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/44596/1 diff --git a/src/soc/mediatek/common/include/soc/ddp_common.h b/src/soc/mediatek/common/include/soc/ddp_common.h index e86675b..43893f7 100644 --- a/src/soc/mediatek/common/include/soc/ddp_common.h +++ b/src/soc/mediatek/common/include/soc/ddp_common.h @@ -6,7 +6,6 @@ #include <soc/addressmap.h> #include <types.h> - struct disp_ovl_regs { u32 sta; u32 inten; @@ -113,7 +112,6 @@ check_member(disp_color_regs, height, 0xC54); static struct disp_color_regs *const disp_color0 = (void *)DISP_COLOR0_BASE; - enum { COLOR_BYPASS_ALL = BIT(7), COLOR_SEQ_SEL = BIT(13), diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index 71deb71..cbec250 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include <device/mmio.h> #include <soc/mtcmos.h> #include <soc/spm.h> diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c index 8c98b35..e44a76f 100644 --- a/src/soc/mediatek/mt8173/da9212.c +++ b/src/soc/mediatek/mt8173/da9212.c @@ -56,7 +56,6 @@ unsigned char device_id = 0; unsigned char variant_id = 0; - /* select to page 4, clear REVERT at first time */ ret |= i2c_write_field(i2c_num, DA9212_SLAVE_ADDR, DA9212_REG_PAGE_CON, DA9212_REG_PAGE4, diff --git a/src/soc/mediatek/mt8173/mt6311.c b/src/soc/mediatek/mt8173/mt6311.c index e8fe6dc..3e61f8c 100644 --- a/src/soc/mediatek/mt8173/mt6311.c +++ b/src/soc/mediatek/mt8173/mt6311.c @@ -25,7 +25,6 @@ int ret = 0; unsigned char var[3] = {0}; - /* * Phase Shedding Trim Software Setting * The phase 2 of MT6311 will enter PWM mode if the threshold is diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 8a86f0b..0fe94cf 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -373,7 +373,6 @@ setbits32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); } - /* after pmic_init */ void mt_pll_post_init(void) { diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index ef57fa6..d08de45 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -9,7 +9,6 @@ #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - /* initialize rtc related gpio */ static int rtc_gpio_init(void) { diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h index bc4e6ab..a059abf 100644 --- a/src/soc/mediatek/mt8183/include/soc/ddp.h +++ b/src/soc/mediatek/mt8183/include/soc/ddp.h @@ -42,7 +42,6 @@ static struct mmsys_cfg_regs *const mmsys_cfg = (void *)MMSYS_BASE; - /* DISP_REG_CONFIG_MMSYS_CG_CON0 Configures free-run clock gating 0 0: Enable clock diff --git a/src/soc/mediatek/mt8183/pmic_wrap.c b/src/soc/mediatek/mt8183/pmic_wrap.c index bae3fce..4d195b7 100644 --- a/src/soc/mediatek/mt8183/pmic_wrap.c +++ b/src/soc/mediatek/mt8183/pmic_wrap.c @@ -47,7 +47,6 @@ COUNTER16_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x340), }; - static void pwrap_soft_reset(void) { write32(&mt8183_infracfg->infra_globalcon_rst2_set, 0x1); diff --git a/src/soc/mediatek/mt8192/include/soc/gpio.h b/src/soc/mediatek/mt8192/include/soc/gpio.h index 0c90bdf..716a63d 100644 --- a/src/soc/mediatek/mt8192/include/soc/gpio.h +++ b/src/soc/mediatek/mt8192/include/soc/gpio.h @@ -699,7 +699,6 @@ I2S6_DI, I2S8_DI, RES6, RES7), }; - struct val_regs { uint32_t val; uint32_t set; -- To view, visit https://review.coreboot.org/c/coreboot/+/44596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia419de14614a7a1b583e0870e9ca2fcdc8cf815a Gerrit-Change-Number: 44596 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/siemens/mc_apl2/gpio: Fix code style
by Maxim Polyakov (Code Review) 10 Sep '20

10 Sep '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44470 ) Change subject: mb/siemens/mc_apl2/gpio: Fix code style ...................................................................... mb/siemens/mc_apl2/gpio: Fix code style Use the 96 character limit for pad macros. Change-Id: I03fd2f9309c04628c46e3473bed280edc57e215c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c 1 file changed, 57 insertions(+), 114 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44470/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index 9c1d79a..d3fe627 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -53,11 +53,9 @@ PAD_CFG_NF_IOSSTATE(GPIO_171, UP_20K, DEEP, NF1, HIZCRx1), /* SDCARD_CLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* SDCARD_D0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* SDCARD_D1 */ PAD_CFG_NF_IOSSTATE(GPIO_174, UP_20K, DEEP, NF1, HIZCRx1), /* SDCARD_D2 */ @@ -67,8 +65,7 @@ /* SDCARD_CD_1V8# */ PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CMD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_178, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_178, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* Not connected */ PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_WP_1V8 */ @@ -79,42 +76,31 @@ /* West Community */ /* I2C_PM_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_PM_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM0_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM0_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM1_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM1_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_GP_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_GP_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_LCD_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_LCD_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* Not connected */ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_134, UP_20K, DEEP, Tx0RxDCRx0, MASK), /* Not connected */ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_135, UP_20K, DEEP, Tx0RxDCRx0, MASK), /* GPIO_PWRBTN# */ - PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, - TxDRxE, SAME), + PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), /* HDA_BCLK_1V8 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, DN_20K, DEEP, NF3, MASK, SAME), @@ -147,19 +133,15 @@ PAD_CFG_GPI_INT(OSC_CLK_OUT_4, DN_20K, DEEP, OFF), /* PM_CHARGER_PRSNT */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_AC_PRESENT, DN_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_AC_PRESENT, DN_20K, DEEP, NF1, MASK, SAME), /* PM_BATLOW# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_BATLOW_B, UP_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_BATLOW_B, UP_20K, DEEP, NF1, MASK, SAME), /* PMU_PLTRST# */ PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PLTRST_B, NONE, DEEP, NF1, MASK, SAME), /* PMU_PWRBTN# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PWRBTN_B, UP_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PWRBTN_B, UP_20K, DEEP, NF1, MASK, SAME), /* SYS_RESET# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_RESETBUTTON_B, NONE, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_RESETBUTTON_B, NONE, DEEP, NF1, MASK, SAME), /* PMU_SLP_S0# */ PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_SLP_S0_B, NONE, DEEP, NF1, MASK, SAME), /* PMU_SLP_S3# */ @@ -198,12 +180,9 @@ /* Not connected */ PAD_CFG_NF(GPIO_191, DN_20K, DEEP, NF1), PAD_CFG_NF(GPIO_192, DN_20K, DEEP, NF1), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_193, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_194, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_195, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_193, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_194, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_195, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), /* EDP_VDD_EN_1V8 (DNI) - Alternative stuffing option for * PTN3460 LVDS_VDD_EN. @@ -228,10 +207,8 @@ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), /* USB2_OC0_1V8# - Connected to (USB0_OC#:MUX_SEL[USB2_OTG_0/USB2_6]), * (USB1_OC#:USB1), (USB2_OC#:USB2) @@ -243,34 +220,26 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, MASK, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS0, UP_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS0, UP_20K, DEEP, NF1, TxLASTRxE, SAME), /* EDP_HPD# - from HPDRX pin of PTN3460 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS1, UP_20K, DEEP, NF2, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS1, UP_20K, DEEP, NF2, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS2, UP_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS2, UP_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_RXD, DN_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_RXD, DN_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_TXD, DN_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_TXD, DN_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_CLK, DN_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_CLK, DN_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), PAD_CFG_TERM_GPO(GPIO_214, 1, DN_20K, DEEP), PAD_CFG_TERM_GPO(GPIO_215, 1, DN_20K, DEEP), /* THERMTRIP_1V8# - Connected to CPLD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1, - TxLASTRxE, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1, TxLASTRxE, SAME), /* PROCHOT_CPU# - Connected to CPLD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PROCHOT_B, UP_20K, DEEP, NF1, HIZCRx1, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PROCHOT_B, UP_20K, DEEP, NF1, HIZCRx1, SAME), /* Not connected */ PAD_CFG_GPI_INT(PMIC_I2C_SCL, DN_20K, DEEP, OFF), @@ -342,8 +311,7 @@ /* FST_SPI_CLK_1V8. Goes to both module SPI chip and carrier board. */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_103, NATIVE, DEEP, NF1, MASK, SAME), /* FST_SPI_CLK_FB */ - PAD_CFG_NF_IOSSTATE_IOSTERM(FST_SPI_CLK_FB, NONE, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(FST_SPI_CLK_FB, NONE, DEEP, NF1, MASK, SAME), /* SIO_SPI_CLK_1V8 - Connected to ESPI_CK of SMARC connector. */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD), @@ -436,8 +404,7 @@ * Module. Pulled up on Module. Driven by Open Drain (OD) part on * Carrier. */ - PAD_CFG_GPI_SCI_IOS(GPIO_22, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, - SAME), + PAD_CFG_GPI_SCI_IOS(GPIO_22, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), /* LID_CPU_1V8# - Connect to the SMARC Connector LID# pin. * Lid open/close indication to Module. Low indicates lid closure * (which system may use to initiate a sleep state). Carrier to float @@ -445,8 +412,7 @@ * de-bounced on the Module Pulled up on Module. Driven by OD part on * Carrier. */ - PAD_CFG_GPI_SCI_IOS(GPIO_23, UP_20K, DEEP, EDGE_BOTH, INVERT, TxDRxE, - SAME), + PAD_CFG_GPI_SCI_IOS(GPIO_23, UP_20K, DEEP, EDGE_BOTH, INVERT, TxDRxE, SAME), /* WDT_IRQ1_1V8# (NMI) - Trigger by CPLD Watchdog module when enabled * and timeout. */ @@ -504,11 +470,9 @@ /* MCSI1_RST_1V8# - Reset the MIPI CSI camera interfaces 1 */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_68, 0, DEEP, DN_20K, HIZCRx0, SAME), /* MCSI0_PWR_1V8# - Power for the MIPI CSI camera interfaces 0 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_69, 0, DEEP, DN_20K, Tx1RxDCRx1, - SAME), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_69, 0, DEEP, DN_20K, Tx1RxDCRx1, SAME), /* MCSI1_PWR_1V8# - Power for the MIPI CSI camera interfaces 1 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_70, 0, DEEP, DN_20K, Tx1RxDCRx1, - SAME), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_70, 0, DEEP, DN_20K, Tx1RxDCRx1, SAME), /* Not connected */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_71, 0, DEEP, DN_20K, HIZCRx0, SAME), /* Not connected */ @@ -577,41 +541,29 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, DN_20K, PWROK, NF1, HIZCRx0, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* STRAP_GPIO_39 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* STRAP_GPIO_40 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* CPU_UART1_RX to SMARC Connector SER0_RX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* CPU_UART1_TX to SMARC Connector SER0_TX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART1_RTS_1V8# to SMARC Connector SER0_RTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART1_CTS_1V8# to SMARC Connector SER0_CTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, HIZCRx0, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* CPU_UART2_RX_1V8 to SMARC Connector SER2_RX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* CPU_UART2_TX_1V8 to SMARC Connector SER2_TX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART2_RTS_1V8# to SMARC Connector SER2_RTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_48, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_48, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART2_CTS_1V8# to SMARC Connector SER2_CTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_49, UP_20K, DEEP, NF1, HIZCRx0, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_49, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* Board ID - GPIO_223 */ PAD_CFG_GPI_INT(PMIC_RESET_B, DN_20K, DEEP, OFF), @@ -635,32 +587,23 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(SMB_DATA, UP_20K, DEEP, NF1, MASK, SAME), /* LPC_SERIRQ_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1, MASK, SAME), /* CLK_25M_LPC_TPM_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* CLK_25M_LPC_CPLD_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD0_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD1_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD2_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD3_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKRUN# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_FRAME_CPU# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), }; const struct pad_config *variant_early_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/44470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03fd2f9309c04628c46e3473bed280edc57e215c Gerrit-Change-Number: 44470 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020