coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel/tigerlake: Maintain consistent tab in systemagent.h
by Subrata Banik (Code Review) 11 Sep '20

11 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45256 ) Change subject: soc/intel/tigerlake: Maintain consistent tab in systemagent.h ...................................................................... soc/intel/tigerlake: Maintain consistent tab in systemagent.h List of changes: 1. This patch converts inconsistent white space into tab. 2. Combine all MCHBAR offset macros Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I82fc362589389081b1b1856524a972b780af9a13 --- M src/soc/intel/tigerlake/include/soc/systemagent.h 1 file changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45256/1 diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index fca9b2b..437356d 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -15,40 +15,40 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) -#define BIOS_RESET_CPL 0x5da8 +/* MCHBAR offsets */ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 #define IPUVTBAR 0x7880 #define TBT0BAR 0x7888 #define TBT1BAR 0x7890 #define TBT2BAR 0x7898 #define TBT3BAR 0x78A0 + #define MAX_TBT_PCIE_PORT 4 -#define VTBAR_ENABLED 0x01 +#define VTBAR_ENABLED 0x01 #define VTBAR_MASK 0x7ffffff000ull -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -#define IMRBASE 0x6A40 -#define IMRLIMIT 0x6A48 - static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, - { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, - { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, - { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, }; #define V_P2SB_CFG_IBDF_BUS 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/45256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82fc362589389081b1b1856524a972b780af9a13 Gerrit-Change-Number: 45256 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device: Fix incompatible-pointer-types while calling pci_dev_request_...
by Subrata Banik (Code Review) 11 Sep '20

11 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45122 ) Change subject: device: Fix incompatible-pointer-types while calling pci_dev_request_bus_master ...................................................................... device: Fix incompatible-pointer-types while calling pci_dev_request_bus_master Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I3b1ce85b8db1ddf9ac860415edbe64694b91b3d1 --- M src/include/device/pci.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/45122/1 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index ec3d45e..6e28cb7 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -133,7 +133,7 @@ #if ENV_PCI_SIMPLE_DEVICE void pci_dev_request_bus_master(pci_devfn_t dev) #else -void pci_dev_request_bus_master(const struct device *dev) +void pci_dev_request_bus_master(struct device *dev) #endif /* ENV_PCI_SIMPLE_DEVICE */ { if (CONFIG(PCI_ALLOW_BUS_MASTER)) -- To view, visit https://review.coreboot.org/c/coreboot/+/45122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b1ce85b8db1ddf9ac860415edbe64694b91b3d1 Gerrit-Change-Number: 45122 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/volteer2: route GPP_F14 via APIC
by Alex Levin (Code Review) 11 Sep '20

11 Sep '20

Alex Levin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45279 ) Change subject: mb/google/volteer/variants/volteer2: route GPP_F14 via APIC ...................................................................... mb/google/volteer/variants/volteer2: route GPP_F14 via APIC GPP_F14 should be configured to be routed via APIC and not SCI. BUG=b:162528549 TEST=verified on a volteer2 Signed-off-by: Alex Levin <levinale(a)google.com> Change-Id: I7f2c7af230dd75b3cb3806e2b186725d49da9e68 --- M src/mainboard/google/volteer/variants/volteer2/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/45279/1 diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index c7fa706..7255423 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -125,7 +125,7 @@ /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE), /* F15 : GSXSRESET# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_F15, 1, DEEP), /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f2c7af230dd75b3cb3806e2b186725d49da9e68 Gerrit-Change-Number: 45279 Gerrit-PatchSet: 1 Gerrit-Owner: Alex Levin <levinale(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: add willow memory mapping table
by Sheng-Liang Pan (Code Review) 11 Sep '20

11 Sep '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44981 ) Change subject: mb/google/kukui: add willow memory mapping table ...................................................................... mb/google/kukui: add willow memory mapping table add memory mapping table for willow index#0 Samsung K4UBE3D4AA-MGCR 4GB index#2 Micron MT53E1G32D4NQ-4GB index#10 Hynix H9HCNNNCPMMLXR-NEE-4GB BUG=b:160288021 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I5068af12585c098772c3027dcd633723851d4e5f --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/sdram_configs.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/44981/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 01247ca..1abdf83 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -74,6 +74,7 @@ config BOARD_SDRAM_TABLE_OFFSET hex default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE + default 0x20 if BOARD_GOOGLE_WILLOW default 0x0 endif diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 1f9e6bb..4b66a66 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -30,6 +30,12 @@ [0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", [0x14] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", [0x16] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", + + /* Table for willow, offset = 0x20 */ + [0x20] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", + [0x22] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x2a] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + }; static struct sdram_params params; -- To view, visit https://review.coreboot.org/c/coreboot/+/44981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5068af12585c098772c3027dcd633723851d4e5f Gerrit-Change-Number: 44981 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/tigerlake: add S0ix support fsp_params
by Caveh Jalali (Code Review) 11 Sep '20

11 Sep '20

Caveh Jalali has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39367 ) Change subject: src/soc/tigerlake: add S0ix support fsp_params ...................................................................... Abandoned obsolete -- To view, visit https://review.coreboot.org/c/coreboot/+/39367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf29865e80311d6ef52ea0ff2a722f8d4e845dd7 Gerrit-Change-Number: 39367 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/soc/tigerlake: Enabled D3HotEnable in fsp_params
by Caveh Jalali (Code Review) 11 Sep '20

11 Sep '20

Caveh Jalali has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39368 ) Change subject: src/soc/tigerlake: Enabled D3HotEnable in fsp_params ...................................................................... Abandoned obsolete -- To view, visit https://review.coreboot.org/c/coreboot/+/39368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba12339378b38ff850da812135f51a1d8d4130f Gerrit-Change-Number: 39368 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/soc/tigerlake: Enabled D3ColdEnable in fsp_params
by Caveh Jalali (Code Review) 11 Sep '20

11 Sep '20

Caveh Jalali has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39369 ) Change subject: src/soc/tigerlake: Enabled D3ColdEnable in fsp_params ...................................................................... Abandoned obsolete -- To view, visit https://review.coreboot.org/c/coreboot/+/39369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2b1b0b3b50cd8a7b2f974579dc281bcd65c243a Gerrit-Change-Number: 39369 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: trogdor: Strappings_update_final3.1_second_thisistherealone.patch
by Julius Werner (Code Review) 10 Sep '20

10 Sep '20

Hello Douglas Anderson, Philip Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45225 to review the following change. Change subject: trogdor: Strappings_update_final3.1_second_thisistherealone.patch ...................................................................... trogdor: Strappings_update_final3.1_second_thisistherealone.patch Apparently what I thought was lazor-rev2 is actually lazor-rev3 and nobody is really sure what lazor-rev4 is going to be at this point or how we proceed from there. What seems to be somewhat agreed upon is that for now all Lazor revisions use the "old" GPIO mapping and it's not very clear if that's ever going to change for Lazor, so let's take the revision restriction out from Lazor for now. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I4939ccfd8464da6e72b5e01a58489b8c80f5b4df --- M src/mainboard/google/trogdor/boardid.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45225/1 diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c index f60dddbe..edde164 100644 --- a/src/mainboard/google/trogdor/boardid.c +++ b/src/mainboard/google/trogdor/boardid.c @@ -16,11 +16,12 @@ return id; } -/* Whether a revision was built before or after the great pin migration of August 2020. */ +/* Some boards/revisions use one GPIO mapping and others use another. There's no real rhyme or + reason to it. Don't try to think about it too much... */ static bool use_old_pins(void) { return ((CONFIG(BOARD_GOOGLE_TROGDOR) && board_id() < 2) || - (CONFIG(BOARD_GOOGLE_LAZOR) && board_id() < 3) || + CONFIG(BOARD_GOOGLE_LAZOR) || (CONFIG(BOARD_GOOGLE_POMPOM) && board_id() < 1)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4939ccfd8464da6e72b5e01a58489b8c80f5b4df Gerrit-Change-Number: 45225 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp9: gpio: convert gpio.h to a cleaner format
by Michael Niewöhner (Code Review) 10 Sep '20

10 Sep '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Jeremy Soller, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43652 to look at the new patch set (#29). Change subject: mb/system76/lemp9: gpio: convert gpio.h to a cleaner format ...................................................................... mb/system76/lemp9: gpio: convert gpio.h to a cleaner format This converts gpio.h to a compacter, cleaner format by keeping gpios in a single line, where possible. Test: images built with TIMELESS do not differ. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017 --- M src/mainboard/system76/lemp9/gpio.h 1 file changed, 222 insertions(+), 504 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/43652/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/43652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017 Gerrit-Change-Number: 43652 Gerrit-PatchSet: 29 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Moves APCB generation out of picasso
by Rob Barnes (Code Review) 10 Sep '20

10 Sep '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45222 ) Change subject: soc/amd/picasso: Moves APCB generation out of picasso ...................................................................... soc/amd/picasso: Moves APCB generation out of picasso Moved APCB generation out of the picasso makefile and into the mainboard makefile. APCB generation tends to be mainboard specific and does not belong in the soc makefile. BUG=b:168099242 TEST=Build mandolin and check for APCB in coreboot binary Build and boot ezkinil Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/amd/mandolin/Makefile.inc M src/mainboard/google/zork/spd/Makefile.inc M src/soc/amd/picasso/Makefile.inc 3 files changed, 23 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/45222/1 diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 1865e74..6d7bf3a 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -10,8 +10,7 @@ ramstage-y += emmc_gpio.c endif -# APCB_mandolin.bin -APCB_SOURCES = mandolin +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_mandolin.bin PHONY+=add_mchp_fw INTERMEDIATE+=add_mchp_fw diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc index 66957d8..1042d91 100644 --- a/src/mainboard/google/zork/spd/Makefile.inc +++ b/src/mainboard/google/zork/spd/Makefile.inc @@ -2,3 +2,23 @@ # This directory SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd + +APCB_SOURCES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).gen) + +# APCB binary with magic numbers to be replaced by apcb_edit tool +APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin + +$(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)/%.hex \ + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --hex \ + --strip_manufacturer_information \ + --spd_0_0 $< \ + $(if $(APCB_POPULATE_2ND_CHANNEL), --spd_1_0 $<, ) \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f4ec6c9..8789694 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -196,9 +196,8 @@ # # BIOS Directory Table items - proper ordering is managed by amdfwtool # - # type = 0x60 -PSP_APCB_FILES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).bin) +PSP_APCB_FILES=$(APCB_SOURCES) # type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) @@ -383,28 +382,6 @@ --soc-name "Picasso" \ --flashsize $(CONFIG_ROM_SIZE) -# Copy prebuild APCBs if they exist -$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin - cp $< $@ - -# APCB binary with magic numbers to be replaced by apcb_edit tool -APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin - -$(obj)/APCB_%.bin: $$(SPD_SOURCES_DIR)/%.hex \ - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) \ - $@ \ - --hex \ - --strip_manufacturer_information \ - --spd_0_0 $< \ - $(if $(APCB_POPULATE_2ND_CHANNEL), --spd_1_0 $<, ) \ - --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ - --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ - --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ - --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) - $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ @@ -443,6 +420,7 @@ $$(PSP_APCB_FILES) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/45222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c Gerrit-Change-Number: 45222 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2020