Change in coreboot[master]: soc/intel/tigerlake: Maintain consistent tab in systemagent.h
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45256 )
Change subject: soc/intel/tigerlake: Maintain consistent tab in systemagent.h ......................................................................
soc/intel/tigerlake: Maintain consistent tab in systemagent.h
List of changes: 1. This patch converts inconsistent white space into tab. 2. Combine all MCHBAR offset macros
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: I82fc362589389081b1b1856524a972b780af9a13 --- M src/soc/intel/tigerlake/include/soc/systemagent.h 1 file changed, 19 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45256/1
diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index fca9b2b..437356d 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -15,40 +15,40 @@
#define EPBAR 0x40 #define DMIBAR 0x68 -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23)
-#define BIOS_RESET_CPL 0x5da8 +/* MCHBAR offsets */ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 #define IPUVTBAR 0x7880 #define TBT0BAR 0x7888 #define TBT1BAR 0x7890 #define TBT2BAR 0x7898 #define TBT3BAR 0x78A0 + #define MAX_TBT_PCIE_PORT 4
-#define VTBAR_ENABLED 0x01 +#define VTBAR_ENABLED 0x01 #define VTBAR_MASK 0x7ffffff000ull
-#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -#define IMRBASE 0x6A40 -#define IMRLIMIT 0x6A48 - static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, - { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, - { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, - { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, };
#define V_P2SB_CFG_IBDF_BUS 0
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45256 )
Change subject: soc/intel/tigerlake: Maintain consistent tab in systemagent.h ......................................................................
Patch Set 1: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/45256/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45256/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/tigerlake: Maintain consistent tab in systemagent.h I would use:
soc/intel/tigerlake: Clean up systemagent.h
https://review.coreboot.org/c/coreboot/+/45256/1//COMMIT_MSG@10 PS1, Line 10: This patch converts Convert
https://review.coreboot.org/c/coreboot/+/45256/1//COMMIT_MSG@11 PS1, Line 11: Combine Group together
Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45256
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Clean up systemagent.h ......................................................................
soc/intel/tigerlake: Clean up systemagent.h
List of changes: 1. Convert inconsistent white space into tab. 2. Group together all MCHBAR offset macros.
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: I82fc362589389081b1b1856524a972b780af9a13 --- M src/soc/intel/tigerlake/include/soc/systemagent.h 1 file changed, 19 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45256/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45256 )
Change subject: soc/intel/tigerlake: Clean up systemagent.h ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45256/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45256/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/tigerlake: Maintain consistent tab in systemagent.h
I would use: […]
Ack
https://review.coreboot.org/c/coreboot/+/45256/1//COMMIT_MSG@10 PS1, Line 10: This patch converts
Convert
Ack
https://review.coreboot.org/c/coreboot/+/45256/1//COMMIT_MSG@11 PS1, Line 11: Combine
Group together
Ack
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45256 )
Change subject: soc/intel/tigerlake: Clean up systemagent.h ......................................................................
Patch Set 2: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45256 )
Change subject: soc/intel/tigerlake: Clean up systemagent.h ......................................................................
soc/intel/tigerlake: Clean up systemagent.h
List of changes: 1. Convert inconsistent white space into tab. 2. Group together all MCHBAR offset macros.
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: I82fc362589389081b1b1856524a972b780af9a13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45256 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/include/soc/systemagent.h 1 file changed, 19 insertions(+), 19 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index fca9b2b..437356d 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -15,40 +15,40 @@
#define EPBAR 0x40 #define DMIBAR 0x68 -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23)
-#define BIOS_RESET_CPL 0x5da8 +/* MCHBAR offsets */ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 #define IPUVTBAR 0x7880 #define TBT0BAR 0x7888 #define TBT1BAR 0x7890 #define TBT2BAR 0x7898 #define TBT3BAR 0x78A0 + #define MAX_TBT_PCIE_PORT 4
-#define VTBAR_ENABLED 0x01 +#define VTBAR_ENABLED 0x01 #define VTBAR_MASK 0x7ffffff000ull
-#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -#define IMRBASE 0x6A40 -#define IMRLIMIT 0x6A48 - static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, - { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, - { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, - { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, };
#define V_P2SB_CFG_IBDF_BUS 0
-
Angel Pons (Code Review) -
Subrata Banik (Code Review)
-
Tim Wawrzynczak (Code Review)