coreboot-gerrit September 2020

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Change in coreboot[master]: mb/google/zork: Add woomax memory ID 0
by Rob Barnes (Code Review) 11 Sep '20

11 Sep '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45264 ) Change subject: mb/google/zork: Add woomax memory ID 0 ...................................................................... mb/google/zork: Add woomax memory ID 0 Woomax needs memory ID 0 to map to MT40A512M16TB-062E:J. BUG=b:165611555 TEST=None Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: Ibbcef6be382bd6649c93cfe92427f124dd137112 --- M src/mainboard/google/zork/variants/woomax/spd/Makefile.inc M src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45264/1 diff --git a/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc b/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc index dd877fd..91ef5e5 100644 --- a/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) +SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = MT40A512M16TB-062E:J SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = H5AN8G6NCJR-XNC SPD_SOURCES += ddr4-spd-empty.hex # ID = 2(0b0010) SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) diff --git a/src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt index 7d40e2a..c0583f4 100644 --- a/src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt @@ -1,4 +1,5 @@ DRAM Part Name ID to assign +MT40A512M16TB-062E:J 0 (0000) H5AN8G6NCJR-XNC 1 (0001) MT40A512M16TB-062E:J 8 (1000) H5AN8G6NCJR-XNC 9 (1001) diff --git a/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt index 625a8d0..65988e9 100644 --- a/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt @@ -7,6 +7,7 @@ # See util/spd_tools/ddr4/README.md for more details and instructions. # Part Name, Fixed ID (optional) +MT40A512M16TB-062E:J, 0 H5AN8G6NCJR-XNC, 1 MT40A512M16TB-062E:J, 8 H5AN8G6NCJR-XNC, 9 -- To view, visit https://review.coreboot.org/c/coreboot/+/45264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbcef6be382bd6649c93cfe92427f124dd137112 Gerrit-Change-Number: 45264 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/amd/picasso: Fix TSC frequency calculation
by Nikolai Vyssotski (Code Review) 11 Sep '20

11 Sep '20

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45055 ) Change subject: soc/amd/picasso: Fix TSC frequency calculation ...................................................................... soc/amd/picasso: Fix TSC frequency calculation Fix TSC frequency calculation per Picasso PPR. This code was copied from Stoney and was incorrect for Picasso. BUG=b:163423984 TEST=verify Dalboz TSC to be 1GHz BRANCH=zork Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/tsc_freq.c 1 file changed, 11 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45055/1 diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index a86080c..c863657 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -22,9 +22,17 @@ if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); - cpufid = (msr.lo & 0x3f); - cpudid = (msr.lo & 0x1c0) >> 6; + cpufid = (msr.lo & 0xff); + cpudid = (msr.lo & 0x3f00) >> 8; - mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid); + if (!cpudid) + mhz = 0; + else if ((cpudid >= 8) && (cpudid < 0x3c)) + mhz = (unsigned long) ((200 * cpufid) / cpudid); + else { + printk(BIOS_INFO, "Incorrect core frequency divisor %x, assume 1\n", cpudid); + mhz = (unsigned long) (25 * cpufid); + } + return mhz; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55 Gerrit-Change-Number: 45055 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: vc/amd/fsp/picasso: Fix FSP-S UPD header file formatting
by Felix Held (Code Review) 11 Sep '20

11 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45257 ) Change subject: vc/amd/fsp/picasso: Fix FSP-S UPD header file formatting ...................................................................... vc/amd/fsp/picasso: Fix FSP-S UPD header file formatting Use one tab instead of 8 spaces at the beginning of the lines added in commit 39a8040ddc551306d823d52a459fdb5dd717b2fe. Change-Id: I8d7553e1b41dbbbdabd7392028a51e3a0f79c97a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45257/1 diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 34c672d..c1d3db0 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -32,9 +32,9 @@ /** Offset 0x011E**/ uint32_t xhci_oc_pin_select; /** Offset 0x0122**/ uint8_t xhci0_force_gen1; /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; - /** Offset 0x0124**/ uint32_t gnb_ioapic_base; - /** Offset 0x0128**/ uint8_t gnb_ioapic_id; - /** Offset 0x0129**/ uint8_t fch_ioapic_id; + /** Offset 0x0124**/ uint32_t gnb_ioapic_base; + /** Offset 0x0128**/ uint8_t gnb_ioapic_id; + /** Offset 0x0129**/ uint8_t fch_ioapic_id; /** Offset 0x0126**/ uint8_t UnusedUpdSpace0[38]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/45257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d7553e1b41dbbbdabd7392028a51e3a0f79c97a Gerrit-Change-Number: 45257 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/amd/picasso: Assign IOAPIC IDs using FSP
by Marshall Dawson (Code Review) 11 Sep '20

11 Sep '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45115 ) Change subject: soc/amd/picasso: Assign IOAPIC IDs using FSP ...................................................................... soc/amd/picasso: Assign IOAPIC IDs using FSP Add a Kconfig symbol to use for the FCH and GNB IOAPIC IDs, then pass the info to FSP to keep it in sync. The assignment assumes that the FCH IOAPIC is set to CONFIG_MAX_CPUS and the GNB one is the next higher. BUG=b:167421913, b:166519072 TEST=Boot Morphius and verify settings BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/fsp_params.c 3 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45115/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ec5ff76..4a3082b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -243,6 +243,14 @@ hex default 0xfef00000 +config PICASSO_IOAPIC_IDS + hex + default MAX_CPUS + help + The Picasso APU has two IOAPICs, one in the FCH and one in the + northbridge. Set this value for the intended ID to assign to the + FCH IOAPIC. The northbridge's one will be the next higher ID. + config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 1b9c0ca..0f1a4c2 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -51,7 +51,7 @@ /* Write Kern IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + CONFIG_PICASSO_IOAPIC_IDS, IO_APIC_ADDR, 0); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 1dbb8e5..aeccfca 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -122,6 +122,12 @@ } } +static void fsp_assign_ioapic_ids(FSP_S_CONFIG *scfg) +{ + scfg->fch_ioapic_id = CONFIG_PICASSO_IOAPIC_IDS; + scfg->gnb_ioapic_id = CONFIG_PICASSO_IOAPIC_IDS + 1; +} + void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { const struct soc_amd_picasso_config *cfg; @@ -130,5 +136,6 @@ cfg = config_of_soc(); fsps_update_emmc_config(scfg, cfg); fsp_fill_pcie_ddi_descriptors(scfg); + fsp_assign_ioapic_ids(scfg); fsp_usb_oem_customization(scfg, cfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d Gerrit-Change-Number: 45115 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: soc/amd/common/espi_util: slightly refactor espi_open_io_window
by Felix Held (Code Review) 11 Sep '20

11 Sep '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44353 ) Change subject: soc/amd/common/espi_util: slightly refactor espi_open_io_window ...................................................................... soc/amd/common/espi_util: slightly refactor espi_open_io_window Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/44353/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c1145d0..f1afbdb 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -183,9 +183,9 @@ if (std_io != -1) { espi_enable_decode(std_io); return 0; + } else { + return espi_open_generic_io_window(base, size); } - - return espi_open_generic_io_window(base, size); } static int espi_find_mmio_window(uint32_t win_base) -- To view, visit https://review.coreboot.org/c/coreboot/+/44353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487 Gerrit-Change-Number: 44353 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/intel/tglrvp: Add DTT support for tglrvp
by Sumeet R Pawnikar (Code Review) 11 Sep '20

11 Sep '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45290 ) Change subject: mb/intel/tglrvp: Add DTT support for tglrvp ...................................................................... mb/intel/tglrvp: Add DTT support for tglrvp Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control. BRANCH=None BUG=Noe TEST=Build and boot on tglrvp board Change-Id: I4158ab85f7863378d46b957e49f97aeaa96492f5 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M Documentation/soc/amd/family17h.md M src/include/device/pci.h M src/lib/Makefile.inc M src/mainboard/amd/mandolin/Makefile.inc M src/mainboard/google/trogdor/boardid.c M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/zork/spd/Makefile.inc M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/amd/picasso/Makefile.inc M src/soc/intel/tigerlake/include/soc/systemagent.h M util/abuild/abuild 13 files changed, 136 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45290/1 diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md index 23088cd..fffe25b 100755 --- a/Documentation/soc/amd/family17h.md +++ b/Documentation/soc/amd/family17h.md @@ -240,47 +240,12 @@ ## APCB setup APCBs are used to provide the PSP with SPD information and optionally a set of -GPIOs to use for selecting which SPD to load. - -### Prebuilt -The picasso `Makefile` expects APCBs to be located in -`3rdparty/blobs/mainboard/$(MAINBOARDDIR)`. If you have a pre-built binary just -add the following to your mainboard's Makefile. - -``` -# i.e., 3rdparty/blobs/mainboard/amd/mandolin/APCB_mandolin.bin -APCB_SOURCES = mandolin -``` +GPIOs to use for selecting which SPD to load. A list of APCB files should be +specified in `APCB_SOURCES`. ### Generating APCBs If you have a template APCB file, the `apcb_edit` tool can be used to inject the -SPD and GPIOs used to select the correct slot. Entries should match this -pattern `{NAME}_x{1,2}`. There should be a matching SPD hex file in -`SPD_SOURCES_DIR` matching the pattern `{NAME}.spd.hex`. -The `_x{1,2}` suffix denotes single or dual channel. Up to 16 slots can be used. -If a slot is empty, the special empty keyword can be used. This will generate -an APCB with an empty SPD. - -``` -APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 -APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 -APCB_SOURCES += empty # 0b0010 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0011 -``` - -#### APCB Board ID GPIO configuration. -The GPIOs determine which memory SPD will be used during boot. -``` -# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL -# GPIO_NUMBER: FCH GPIO number -# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO -# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO - -APCB_BOARD_ID_GPIO0 = 121 1 0 -APCB_BOARD_ID_GPIO1 = 120 1 0 -APCB_BOARD_ID_GPIO2 = 131 3 0 -APCB_BOARD_ID_GPIO3 = 116 1 0 -``` +SPD and GPIOs used to select the correct slot. ## Footnotes diff --git a/src/include/device/pci.h b/src/include/device/pci.h index ec3d45e..6e28cb7 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -133,7 +133,7 @@ #if ENV_PCI_SIMPLE_DEVICE void pci_dev_request_bus_master(pci_devfn_t dev) #else -void pci_dev_request_bus_master(const struct device *dev) +void pci_dev_request_bus_master(struct device *dev) #endif /* ENV_PCI_SIMPLE_DEVICE */ { if (CONFIG(PCI_ALLOW_BUS_MASTER)) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4ce133a..e23b9de 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -362,7 +362,7 @@ $(LIB_SPD_BIN): $(LIB_SPD_DEPS) for f in $(LIB_SPD_DEPS); \ do for c in $$(cat $$f | grep --binary-files=text -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 1865e74..6d7bf3a 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -10,8 +10,7 @@ ramstage-y += emmc_gpio.c endif -# APCB_mandolin.bin -APCB_SOURCES = mandolin +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_mandolin.bin PHONY+=add_mchp_fw INTERMEDIATE+=add_mchp_fw diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c index f60dddbe..edde164 100644 --- a/src/mainboard/google/trogdor/boardid.c +++ b/src/mainboard/google/trogdor/boardid.c @@ -16,11 +16,12 @@ return id; } -/* Whether a revision was built before or after the great pin migration of August 2020. */ +/* Some boards/revisions use one GPIO mapping and others use another. There's no real rhyme or + reason to it. Don't try to think about it too much... */ static bool use_old_pins(void) { return ((CONFIG(BOARD_GOOGLE_TROGDOR) && board_id() < 2) || - (CONFIG(BOARD_GOOGLE_LAZOR) && board_id() < 3) || + CONFIG(BOARD_GOOGLE_LAZOR) || (CONFIG(BOARD_GOOGLE_POMPOM) && board_id() < 1)); } diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index c7fa706..7255423 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -125,7 +125,7 @@ /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE), /* F15 : GSXSRESET# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_F15, 1, DEEP), /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc index 66957d8..1042d91 100644 --- a/src/mainboard/google/zork/spd/Makefile.inc +++ b/src/mainboard/google/zork/spd/Makefile.inc @@ -2,3 +2,23 @@ # This directory SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd + +APCB_SOURCES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).gen) + +# APCB binary with magic numbers to be replaced by apcb_edit tool +APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin + +$(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)/%.hex \ + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --hex \ + --strip_manufacturer_information \ + --spd_0_0 $< \ + $(if $(APCB_POPULATE_2ND_CHANNEL), --spd_1_0 $<, ) \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index c94cca6..53df820 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -3,16 +3,19 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 + select DPTF_USE_EISA_HID select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_PMC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select SOC_INTEL_TIGERLAKE + select SOC_INTEL_COMMON_BLOCK_DTT select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH select EC_ACPI diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d4390b0..e254e37 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -115,6 +115,24 @@ # Enable S0ix register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 38, + .tdp_pl4 = 71, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 60, + .tdp_pl4 = 105, + }" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -149,7 +167,29 @@ #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up3 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7a5cae1..08c4245 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -109,6 +109,24 @@ # Enable S0ix register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 66, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 40, + .tdp_pl4 = 83, + }" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -143,7 +161,29 @@ #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up3 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 9000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f4ec6c9..eb2be50 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -198,7 +198,7 @@ # # type = 0x60 -PSP_APCB_FILES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).bin) +PSP_APCB_FILES=$(APCB_SOURCES) # type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) @@ -383,28 +383,6 @@ --soc-name "Picasso" \ --flashsize $(CONFIG_ROM_SIZE) -# Copy prebuild APCBs if they exist -$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin - cp $< $@ - -# APCB binary with magic numbers to be replaced by apcb_edit tool -APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin - -$(obj)/APCB_%.bin: $$(SPD_SOURCES_DIR)/%.hex \ - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) \ - $@ \ - --hex \ - --strip_manufacturer_information \ - --spd_0_0 $< \ - $(if $(APCB_POPULATE_2ND_CHANNEL), --spd_1_0 $<, ) \ - --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ - --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ - --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ - --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) - $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ @@ -443,6 +421,7 @@ $$(PSP_APCB_FILES) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index fca9b2b..437356d 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -15,40 +15,40 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) -#define BIOS_RESET_CPL 0x5da8 +/* MCHBAR offsets */ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 #define IPUVTBAR 0x7880 #define TBT0BAR 0x7888 #define TBT1BAR 0x7890 #define TBT2BAR 0x7898 #define TBT3BAR 0x78A0 + #define MAX_TBT_PCIE_PORT 4 -#define VTBAR_ENABLED 0x01 +#define VTBAR_ENABLED 0x01 #define VTBAR_MASK 0x7ffffff000ull -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -#define IMRBASE 0x6A40 -#define IMRLIMIT 0x6A48 - static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, - { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, - { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, - { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, }; #define V_P2SB_CFG_IBDF_BUS 0 diff --git a/util/abuild/abuild b/util/abuild/abuild index 53a988b9..7561495 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -263,10 +263,8 @@ # Disable all other payload config options { echo "# CONFIG_PAYLOAD_SEABIOS is not set" - echo "# CONFIG_PAYLOAD_BAYOU is not set" echo "# CONFIG_PAYLOAD_FILO is not set" echo "# CONFIG_PAYLOAD_GRUB2 is not set" - echo "# CONFIG_PAYLOAD_OPENBIOS is not set" echo "# CONFIG_PAYLOAD_DEPTHCHARGE is not set" echo "# CONFIG_PAYLOAD_LINUXBOOT is not set" echo "# CONFIG_PAYLOAD_UBOOT is not set" -- To view, visit https://review.coreboot.org/c/coreboot/+/45290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4158ab85f7863378d46b957e49f97aeaa96492f5 Gerrit-Change-Number: 45290 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in gerrit-avatars[master]: Add my avatar
by Casper Chang (Code Review) 11 Sep '20

11 Sep '20

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/45231 ) Change subject: Add my avatar ...................................................................... Add my avatar Signed-off-by: Casper Chang <casper_Chang(a)wistron.corp-partner.google.com> Change-Id: I48e9a724ade417a7ece3bc3ba3c667e689cdf9c2 --- A 1002204.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/31/45231/1 diff --git a/1002204.jpg b/1002204.jpg new file mode 100755 index 0000000..8b3f613 --- /dev/null +++ b/1002204.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/45231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: I48e9a724ade417a7ece3bc3ba3c667e689cdf9c2 Gerrit-Change-Number: 45231 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/google/volteer/var/voxel: override VBT selection for voxel.
by Sheng-Liang Pan (Code Review) 11 Sep '20

11 Sep '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45283 ) Change subject: mb/google/volteer/var/voxel: override VBT selection for voxel. ...................................................................... mb/google/volteer/var/voxel: override VBT selection for voxel. WIP Override VBT for Voxel. BUG=b:163074379 TEST=emerge-volteer coreboot-private-files-baseboard-volteer coreboot-coreboot chromeos-bootimage Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Ie65203e285911a872a619cd3ba3438c7bfb24de6 --- M src/mainboard/google/volteer/variants/voxel/Makefile.inc A src/mainboard/google/volteer/variants/voxel/variant.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/45283/1 diff --git a/src/mainboard/google/volteer/variants/voxel/Makefile.inc b/src/mainboard/google/volteer/variants/voxel/Makefile.inc index b0bfc56..e34a40b 100644 --- a/src/mainboard/google/volteer/variants/voxel/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voxel/Makefile.inc @@ -5,3 +5,4 @@ romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/voxel/variant.c b/src/mainboard/google/volteer/variants/voxel/variant.c new file mode 100644 index 0000000..d0e6fef --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/variant.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <ec/google/chromeec/ec.h> +#include <drivers/intel/gma/opregion.h> + +const char *mainboard_vbt_filename(void) +{ + return "vbt-voxel.bin"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie65203e285911a872a619cd3ba3438c7bfb24de6 Gerrit-Change-Number: 45283 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: drivers/spi/tpm: Improve error checking
by Caveh Jalali (Code Review) 11 Sep '20

11 Sep '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45232 ) Change subject: drivers/spi/tpm: Improve error checking ...................................................................... Patch Set 3: (1 comment) > Patch Set 2: > > lgtm, I am just curious where the 2 minute wait was and how does this help to avoid it. the 2 minute wait is in wait_for_status() (same file). with error checking, we bail out of tpm2_process_command() earlier so we never reach the point where wait_for_status() is called. https://review.coreboot.org/c/coreboot/+/45232/2/src/drivers/spi/tpm/tpm.c File src/drivers/spi/tpm/tpm.c: https://review.coreboot.org/c/coreboot/+/45232/2/src/drivers/spi/tpm/tpm.c@… PS2, Line 729: return 1; > nit: blank line before return Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069 Gerrit-Change-Number: 45232 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 11 Sep 2020 04:34:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/spi/tpm: Improve error checking
by Caveh Jalali (Code Review) 11 Sep '20

11 Sep '20

Hello Jes Klinke, build bot (Jenkins), Vadim Bendebury, Tim Wawrzynczak, Christian Walter, Duncan Laurie, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45232 to look at the new patch set (#3). Change subject: drivers/spi/tpm: Improve error checking ...................................................................... drivers/spi/tpm: Improve error checking This adds error checking in paths that previously ignored TPM communication errors. We hit this case occasionally during "Checking cr50 for pending updates"; previously we would go down this path and eventually time out using MAX_STATUS_TIMEOUT, which is 2 minutes. Now, we detect the failure and return with an error indication instead of timing out after a long time. The root cause of the communication error is an open issue. BUG=b:168090038 TEST=booted on volteer, observed error handling when "Checking cr50 for pending updates" fails. Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069 --- M src/drivers/spi/tpm/tpm.c 1 file changed, 39 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45232/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069 Gerrit-Change-Number: 45232 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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