coreboot-gerrit September 2020

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Change in coreboot[master]: mb/siemens/mc_apl2/gpio: Fix code style
by Maxim Polyakov (Code Review) 10 Sep '20

10 Sep '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44470 ) Change subject: mb/siemens/mc_apl2/gpio: Fix code style ...................................................................... mb/siemens/mc_apl2/gpio: Fix code style Use the 96 character limit for pad macros. Change-Id: I03fd2f9309c04628c46e3473bed280edc57e215c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c 1 file changed, 57 insertions(+), 114 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44470/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index 9c1d79a..d3fe627 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -53,11 +53,9 @@ PAD_CFG_NF_IOSSTATE(GPIO_171, UP_20K, DEEP, NF1, HIZCRx1), /* SDCARD_CLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* SDCARD_D0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* SDCARD_D1 */ PAD_CFG_NF_IOSSTATE(GPIO_174, UP_20K, DEEP, NF1, HIZCRx1), /* SDCARD_D2 */ @@ -67,8 +65,7 @@ /* SDCARD_CD_1V8# */ PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CMD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_178, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_178, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* Not connected */ PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_WP_1V8 */ @@ -79,42 +76,31 @@ /* West Community */ /* I2C_PM_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_PM_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM0_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM0_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM1_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM1_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_GP_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_GP_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_LCD_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_LCD_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* Not connected */ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_134, UP_20K, DEEP, Tx0RxDCRx0, MASK), /* Not connected */ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_135, UP_20K, DEEP, Tx0RxDCRx0, MASK), /* GPIO_PWRBTN# */ - PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, - TxDRxE, SAME), + PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), /* HDA_BCLK_1V8 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, DN_20K, DEEP, NF3, MASK, SAME), @@ -147,19 +133,15 @@ PAD_CFG_GPI_INT(OSC_CLK_OUT_4, DN_20K, DEEP, OFF), /* PM_CHARGER_PRSNT */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_AC_PRESENT, DN_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_AC_PRESENT, DN_20K, DEEP, NF1, MASK, SAME), /* PM_BATLOW# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_BATLOW_B, UP_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_BATLOW_B, UP_20K, DEEP, NF1, MASK, SAME), /* PMU_PLTRST# */ PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PLTRST_B, NONE, DEEP, NF1, MASK, SAME), /* PMU_PWRBTN# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PWRBTN_B, UP_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PWRBTN_B, UP_20K, DEEP, NF1, MASK, SAME), /* SYS_RESET# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_RESETBUTTON_B, NONE, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_RESETBUTTON_B, NONE, DEEP, NF1, MASK, SAME), /* PMU_SLP_S0# */ PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_SLP_S0_B, NONE, DEEP, NF1, MASK, SAME), /* PMU_SLP_S3# */ @@ -198,12 +180,9 @@ /* Not connected */ PAD_CFG_NF(GPIO_191, DN_20K, DEEP, NF1), PAD_CFG_NF(GPIO_192, DN_20K, DEEP, NF1), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_193, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_194, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_195, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_193, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_194, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_195, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), /* EDP_VDD_EN_1V8 (DNI) - Alternative stuffing option for * PTN3460 LVDS_VDD_EN. @@ -228,10 +207,8 @@ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), /* USB2_OC0_1V8# - Connected to (USB0_OC#:MUX_SEL[USB2_OTG_0/USB2_6]), * (USB1_OC#:USB1), (USB2_OC#:USB2) @@ -243,34 +220,26 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, MASK, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS0, UP_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS0, UP_20K, DEEP, NF1, TxLASTRxE, SAME), /* EDP_HPD# - from HPDRX pin of PTN3460 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS1, UP_20K, DEEP, NF2, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS1, UP_20K, DEEP, NF2, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS2, UP_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS2, UP_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_RXD, DN_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_RXD, DN_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_TXD, DN_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_TXD, DN_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_CLK, DN_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_CLK, DN_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), PAD_CFG_TERM_GPO(GPIO_214, 1, DN_20K, DEEP), PAD_CFG_TERM_GPO(GPIO_215, 1, DN_20K, DEEP), /* THERMTRIP_1V8# - Connected to CPLD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1, - TxLASTRxE, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1, TxLASTRxE, SAME), /* PROCHOT_CPU# - Connected to CPLD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PROCHOT_B, UP_20K, DEEP, NF1, HIZCRx1, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PROCHOT_B, UP_20K, DEEP, NF1, HIZCRx1, SAME), /* Not connected */ PAD_CFG_GPI_INT(PMIC_I2C_SCL, DN_20K, DEEP, OFF), @@ -342,8 +311,7 @@ /* FST_SPI_CLK_1V8. Goes to both module SPI chip and carrier board. */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_103, NATIVE, DEEP, NF1, MASK, SAME), /* FST_SPI_CLK_FB */ - PAD_CFG_NF_IOSSTATE_IOSTERM(FST_SPI_CLK_FB, NONE, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(FST_SPI_CLK_FB, NONE, DEEP, NF1, MASK, SAME), /* SIO_SPI_CLK_1V8 - Connected to ESPI_CK of SMARC connector. */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD), @@ -436,8 +404,7 @@ * Module. Pulled up on Module. Driven by Open Drain (OD) part on * Carrier. */ - PAD_CFG_GPI_SCI_IOS(GPIO_22, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, - SAME), + PAD_CFG_GPI_SCI_IOS(GPIO_22, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), /* LID_CPU_1V8# - Connect to the SMARC Connector LID# pin. * Lid open/close indication to Module. Low indicates lid closure * (which system may use to initiate a sleep state). Carrier to float @@ -445,8 +412,7 @@ * de-bounced on the Module Pulled up on Module. Driven by OD part on * Carrier. */ - PAD_CFG_GPI_SCI_IOS(GPIO_23, UP_20K, DEEP, EDGE_BOTH, INVERT, TxDRxE, - SAME), + PAD_CFG_GPI_SCI_IOS(GPIO_23, UP_20K, DEEP, EDGE_BOTH, INVERT, TxDRxE, SAME), /* WDT_IRQ1_1V8# (NMI) - Trigger by CPLD Watchdog module when enabled * and timeout. */ @@ -504,11 +470,9 @@ /* MCSI1_RST_1V8# - Reset the MIPI CSI camera interfaces 1 */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_68, 0, DEEP, DN_20K, HIZCRx0, SAME), /* MCSI0_PWR_1V8# - Power for the MIPI CSI camera interfaces 0 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_69, 0, DEEP, DN_20K, Tx1RxDCRx1, - SAME), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_69, 0, DEEP, DN_20K, Tx1RxDCRx1, SAME), /* MCSI1_PWR_1V8# - Power for the MIPI CSI camera interfaces 1 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_70, 0, DEEP, DN_20K, Tx1RxDCRx1, - SAME), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_70, 0, DEEP, DN_20K, Tx1RxDCRx1, SAME), /* Not connected */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_71, 0, DEEP, DN_20K, HIZCRx0, SAME), /* Not connected */ @@ -577,41 +541,29 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, DN_20K, PWROK, NF1, HIZCRx0, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* STRAP_GPIO_39 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* STRAP_GPIO_40 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* CPU_UART1_RX to SMARC Connector SER0_RX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* CPU_UART1_TX to SMARC Connector SER0_TX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART1_RTS_1V8# to SMARC Connector SER0_RTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART1_CTS_1V8# to SMARC Connector SER0_CTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, HIZCRx0, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* CPU_UART2_RX_1V8 to SMARC Connector SER2_RX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* CPU_UART2_TX_1V8 to SMARC Connector SER2_TX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART2_RTS_1V8# to SMARC Connector SER2_RTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_48, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_48, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART2_CTS_1V8# to SMARC Connector SER2_CTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_49, UP_20K, DEEP, NF1, HIZCRx0, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_49, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* Board ID - GPIO_223 */ PAD_CFG_GPI_INT(PMIC_RESET_B, DN_20K, DEEP, OFF), @@ -635,32 +587,23 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(SMB_DATA, UP_20K, DEEP, NF1, MASK, SAME), /* LPC_SERIRQ_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1, MASK, SAME), /* CLK_25M_LPC_TPM_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* CLK_25M_LPC_CPLD_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD0_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD1_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD2_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD3_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKRUN# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_FRAME_CPU# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), }; const struct pad_config *variant_early_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/44470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03fd2f9309c04628c46e3473bed280edc57e215c Gerrit-Change-Number: 44470 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/mc_apl2/gpio: Undo set DRIVER for GPO
by Maxim Polyakov (Code Review) 10 Sep '20

10 Sep '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44469 ) Change subject: mb/siemens/mc_apl2/gpio: Undo set DRIVER for GPO ...................................................................... mb/siemens/mc_apl2/gpio: Undo set DRIVER for GPO GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro with others that do not set the corresponding bit in the Host Software Pad Ownership register. Change-Id: I406a08e526a6c655f38e4c0a355957c98e93881c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c 1 file changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44469/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index aa4a906..9c1d79a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -74,7 +74,7 @@ /* SDCARD_WP_1V8 */ PAD_CFG_GPI_GPIO_DRIVER(GPIO_186, DN_20K, DEEP), /* SD_PWR_EN_1V8 - Always enabled SDCard. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_183, 0, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_183, 0, UP_20K, DEEP) /* West Community */ @@ -208,15 +208,15 @@ /* EDP_VDD_EN_1V8 (DNI) - Alternative stuffing option for * PTN3460 LVDS_VDD_EN. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_196, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_196, 1, UP_20K, DEEP) /* EDP_BKLT_EN_1V8 (DNI) - Alternative stuffing option for * PTN3460 LVDS_BKLT_EN */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_197, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_197, 1, UP_20K, DEEP) /* EDP_BKLT_CTRL_1V8 - Alternative stuffing option for * PTN3460 LVDS_BKLT_CTRL */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_198, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_198, 1, UP_20K, DEEP) /* DDI1_HPD# - Connect to DP1_HPD Hot plug detection signal of SMARC * Connector. @@ -263,8 +263,8 @@ /* Not connected */ PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), - PAD_CFG_GPO_GPIO_DRIVER(GPIO_214, 1, DEEP, DN_20K), - PAD_CFG_GPO_GPIO_DRIVER(GPIO_215, 1, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_214, 1, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPIO_215, 1, DN_20K, DEEP), /* THERMTRIP_1V8# - Connected to CPLD */ PAD_CFG_NF_IOSSTATE_IOSTERM(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1, TxLASTRxE, SAME), @@ -390,15 +390,15 @@ /* OTG_SEL_1V8 - Connected to a USB MUX to select between USB2_DP0 (OTG) * and USB2_DP6. 1:OTG, 0:USB */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_9, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_9, 1, UP_20K, DEEP) /* EN_I2CPM_EXT_1V8 - Connected to OE pin of I2C Re-driver. * Allow/Disallow I2C signal to pass through to SMARC Connector. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_10, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_10, 1, UP_20K, DEEP) /* EN_SMB_EXT_1V8 - Connected to OE pin of I2C Re-driver. * Allow/Disallow SMBUS signal to pass through to SMARC Connector. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_11, 0, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_11, 0, UP_20K, DEEP) /* BOOT_SEL2_1V8# - Three Module pins allow the Carrier board user to * select from eight possible boot devices. */ @@ -413,13 +413,13 @@ */ PAD_CFG_GPI_INT(GPIO_14, UP_20K, DEEP, OFF), /* GPIO_CPLD_TCK_1V8 */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_15, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_15, 0, DN_20K, DEEP), /* GPIO_CPLD_TMS_1V8 */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_16, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_16, 0, DN_20K, DEEP), /* GPIO_CPLD_TDI_1V8 */ PAD_CFG_GPI_INT(GPIO_17, DN_20K, DEEP, OFF), /* GPIO_CPLD_TDO_1V8 */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_18, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_18, 0, DN_20K, DEEP), /* PM_TEST_1V8# connect to the SMARC Connector TEST# pin. * Held low by Carrier to invoke Module vendor specific test function. * Pulled up on Module. Driven by OD part on Carrier. @@ -464,9 +464,9 @@ /* SMB_ALERT_GPIO# */ PAD_CFG_GPI_INT(GPIO_27, UP_20K, DEEP, OFF), /* GPIO_28_DEBUG - Connect to HOOK5 (ClkOut#) pin of XDP connector */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_28, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_28, 1, UP_20K, DEEP) /* GPIO_29_DEBUG - Connect to HOOK4 (ClkOut) pin of XDP connector */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_29, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_29, 0, DN_20K, DEEP), /* Not connected */ PAD_CFG_GPI_INT(GPIO_30, DN_20K, DEEP, OFF), @@ -484,21 +484,21 @@ /* STRAP_GPIO_36 (int. PD) */ PAD_CFG_GPI_INT(GPIO_36, DN_20K, DEEP, OFF), /* Not connected */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_37, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_37, 0, DN_20K, DEEP), /* GPIO_VALID (CPLD=gpio_valid/pi_gpio_en)- This pin Enable the CPLD * GPIO to the SMARC Connector. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_62, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_62, 1, UP_20K, DEEP) /* LVDS_ENABLE_1V8# connect to PTN3460 DP to LVDS converter chip. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_63, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_63, 0, DN_20K, DEEP), /* Not connected */ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_64, DN_20K, DEEP, HIZCRx0, SAME), /* Not connected */ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_65, DN_20K, DEEP, HIZCRx0, SAME), /* CAM_CS0_CS1_SEL - Serial Cameras interfaces Select - to select * between the two MIPI CSI camera interfaces on the SMARC connector. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_66, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_66, 0, DN_20K, DEEP), /* MCSI0_RST_1V8# - Reset the MIPI CSI camera interfaces 0 */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, HIZCRx0, SAME), /* MCSI1_RST_1V8# - Reset the MIPI CSI camera interfaces 1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I406a08e526a6c655f38e4c0a355957c98e93881c Gerrit-Change-Number: 44469 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: vendorcode/intel/fsp/alderlake: Fix FSPS_ARCH_UPD redefinition issue
by Subrata Banik (Code Review) 10 Sep '20

10 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45191 ) Change subject: vendorcode/intel/fsp/alderlake: Fix FSPS_ARCH_UPD redefinition issue ...................................................................... vendorcode/intel/fsp/alderlake: Fix FSPS_ARCH_UPD redefinition issue FSPS_ARCH_UPD struct is part of edk2-stable202005 branch (FspApi.h) hence local definition of FSPS_ARCH_UPD inside FspsUpd.h is causing compilation issue. Change-Id: Id5b3637d9ab6d87aab6da810f9c83d3258900a29 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 1 file changed, 0 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/45191/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 39c360d..7ec577a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -80,36 +80,6 @@ #define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - -/** FSPS_ARCH_UPD -**/ -typedef struct { - -/** Offset 0x0020 - Reserved -**/ - UINT8 Revision; - -/** Offset 0x0021 - Reserved -**/ - UINT8 Reserved[3]; - -/** Offset 0x0024 - Reserved -**/ - UINT32 Length; - -/** Offset 0x0028 - Reserved -**/ - UINT32 FspEventHandler; - -/** Offset 0x002C - Reserved -**/ - UINT8 EnableMultiPhaseSiliconInit; - -/** Offset 0x002D - Reserved -**/ - UINT8 Reserved1[19]; -} FSPS_ARCH_UPD; - /** Fsp S Configuration **/ typedef struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/45191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b3637d9ab6d87aab6da810f9c83d3258900a29 Gerrit-Change-Number: 45191 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/alderlake: Rename pch_init() code
by Subrata Banik (Code Review) 10 Sep '20

10 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45189 ) Change subject: soc/intel/alderlake: Rename pch_init() code ...................................................................... soc/intel/alderlake: Rename pch_init() code Rename the pch_init function to bootblock_pch_init. Change-Id: Id2a89b2f64b58079062d79e07efbdcfad7ed3d2d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/bootblock/bootblock.c M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/alderlake/include/soc/bootblock.h 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45189/1 diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index e7d97c5..96e6268 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -25,7 +25,7 @@ void bootblock_soc_init(void) { report_platform_info(); - pch_init(); + bootblock_pch_init(); /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 8452d83..b7d2c15 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -138,7 +138,7 @@ pch_enable_lpc(); } -void pch_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index 9816b31..087d29f 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -8,7 +8,7 @@ void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -void pch_init(void); +void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/45189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2a89b2f64b58079062d79e07efbdcfad7ed3d2d Gerrit-Change-Number: 45189 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Maintain consistent tab in iomap.h
by Subrata Banik (Code Review) 10 Sep '20

10 Sep '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45194 ) Change subject: soc/intel/tigerlake: Maintain consistent tab in iomap.h ...................................................................... soc/intel/tigerlake: Maintain consistent tab in iomap.h This patch converts inconsistent white space into tab. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: If5e191b92e3e53b43335136ef51bc62589b955a0 --- M src/soc/intel/tigerlake/include/soc/iomap.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/45194/1 diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index cd964f0..6fa29d3 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -53,7 +53,7 @@ #define GFXVT_BASE_ADDRESS 0xfed90000 #define GFXVT_BASE_SIZE 0x1000 -#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_ADDRESS 0xfed92000 #define IPUVT_BASE_SIZE 0x1000 #define VTVC0_BASE_ADDRESS 0xfed91000 -- To view, visit https://review.coreboot.org/c/coreboot/+/45194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5e191b92e3e53b43335136ef51bc62589b955a0 Gerrit-Change-Number: 45194 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: sc7180: Add display hardware pipe line initialization [patch 3 of 3]
by Ravi kumar (Code Review) 09 Sep '20

09 Sep '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39615 ) Change subject: sc7180: Add display hardware pipe line initialization [patch 3 of 3] ...................................................................... sc7180: Add display hardware pipe line initialization [patch 3 of 3] Add sc7180 display hardware pipeline programming support and invoke the display initialization from soc_init Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/display.c A src/soc/qualcomm/sc7180/display/mdss.c A src/soc/qualcomm/sc7180/display/oem_panel.c A src/soc/qualcomm/sc7180/include/soc/display.h A src/soc/qualcomm/sc7180/include/soc/display/panel_sn65dsix6_auo_bll6xak01_dsi_video.h M src/soc/qualcomm/sc7180/soc.c 8 files changed, 1,448 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39615/1 diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index 5ef5360..b07f518 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -14,6 +14,9 @@ select SOC_QUALCOMM_COMMON select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER if SOC_QUALCOMM_SC7180 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 7df4f6e..8bdd329 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -59,6 +59,14 @@ ramstage-y += qupv3_config.c ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/oem_panel.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/mdss.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/target_sc7180.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_panel_display.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/display.c b/src/soc/qualcomm/sc7180/display.c new file mode 100644 index 0000000..1759179 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display.c @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <stdlib.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <soc/mdss_6_2_0.h> +#include <soc/display/panel.h> +#include <soc/display/mipi_dsi.h> +#include <soc/display/panel_display.h> +#include <soc/display/target_sc7180.h> +#include <soc/display.h> + +static struct msm_fb_panel_data panel; +struct panel_struct panelstruct; +static uint8_t display_enable; +static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db; +extern int msm_display_init(struct msm_fb_panel_data *pdata); +int msm_display_config(void); + +static int update_dsi_display_config(void) +{ + /* Place holder to handle dual dsi cases in future */ + int ret = NO_ERROR; + return ret; +} + +static uint32_t mdss_dsi_panel_clock(uint8_t enable, + struct msm_panel_info *pinfo) +{ + /* MDSS Clocks are set in QCLib. DSI clocks are set after programming + * DSI Phy and Pll. This will be place holder if we want to enable + * MDSS Clocks in coreboot later. + */ + return NO_ERROR; +} + +static uint32_t mdss_dsi_panel_reset(uint8_t enable) +{ + uint32_t ret = NO_ERROR; +// if (panelstruct.panelresetseq) //TODO: check if bridge reset seq? + ret = target_panel_reset(enable, panelstruct.panelresetseq, + &panel.panel_info); + return ret; +} + +static int mdss_dsi_panel_power(uint8_t enable, + struct msm_panel_info *pinfo) +{ + int ret = NO_ERROR; + if (enable) { + ret = mdss_dsi_panel_reset(enable); + if (ret) { + printk(BIOS_ERR, "panel reset failed\n"); + return ret; + } + } else { + ret = mdss_dsi_panel_reset(enable); + if (ret) { + printk(BIOS_ERR, "panel reset disable failed\n"); + return ret; + } + } + + return ret; +} + +static int mdss_dsi_panel_pre_init(void) +{ + int ret = NO_ERROR; + if (panelstruct.paneldata->panel_lp11_init) { + ret = mdss_dsi_panel_reset(1); + if (ret) { + printk(BIOS_ERR, "panel reset failed\n"); + return ret; + } + } + if (panelstruct.paneldata->panel_init_delay) + udelay(panelstruct.paneldata->panel_init_delay); + + printk(BIOS_INFO, "Panel pre init done\n"); + return ret; +} + +static int mdss_dsi_bl_enable(uint8_t enable) +{ + int ret = NO_ERROR; + + ret = target_backlight_ctrl(enable); + if (ret) + printk(BIOS_ERR, "Backlight %s failed\n", enable ? "enable" : + "disable"); + return ret; +} + +int msm_display_config(void) +{ + int ret = NO_ERROR; + struct msm_panel_info *pinfo; + pinfo = &(panel.panel_info); + + mdp_set_revision(panel.mdp_rev); + + switch (pinfo->type) { + case MIPI_VIDEO_PANEL: + printk(BIOS_INFO, "Config MIPI_VIDEO_PANEL.\n"); + ret = mdss_dsi_config(&panel); + if (ret) + goto msm_display_config_out; + + if (pinfo->early_config) + ret = pinfo->early_config((void *)pinfo); + + ret = mdp_dsi_video_config(pinfo, &(panel.fb)); + + if (ret) + goto msm_display_config_out; + + break; + default: + return ERROR; + } + if (pinfo->config) + ret = pinfo->config((void *)pinfo); + +msm_display_config_out: + return ret; +} + +int msm_display_init(struct msm_fb_panel_data *pdata) +{ + int ret = NO_ERROR; + + printk(BIOS_INFO, "%s: Display Initialization start\n", __func__); + if (!pdata) { + ret = ERROR; + goto msm_display_init_out; + } + /* Turn on panel */ + if (pdata->power_func) + ret = pdata->power_func(1, &(pdata->panel_info)); + + if (ret) + goto msm_display_init_out; + + /* Enable clock */ + if (pdata->clk_func) + ret = pdata->clk_func(1, &(pdata->panel_info)); + if (ret) + goto msm_display_init_out; + + if (pdata->update_panel_info) + ret = pdata->update_panel_info(); + + if (ret) + goto msm_display_init_out; + + if (pdata->pll_clk_func) + ret = pdata->pll_clk_func(1, &(pdata->panel_info)); + if (ret) + goto msm_display_init_out; + + /* pinfo prepare */ + if (pdata->panel_info.prepare) { + /* this is for edp which pinfo derived from edid */ + ret = pdata->panel_info.prepare(); + pdata->fb.width = pdata->panel_info.xres; + pdata->fb.height = pdata->panel_info.yres; + pdata->fb.stride = pdata->panel_info.xres; + pdata->fb.bpp = pdata->panel_info.bpp; + } + + if (ret) + goto msm_display_init_out; + + ret = msm_display_config(); + + if (ret) + goto msm_display_init_out; + + ret = mdp_dsi_video_on(&(pdata->panel_info)); + + if (ret) + goto msm_display_init_out; + + if (pdata->post_power_func) + ret = pdata->post_power_func(1); + + if (ret) + goto msm_display_init_out; + + /* Turn on backlight */ + if (pdata->bl_func) + ret = pdata->bl_func(1); + if (ret) + goto msm_display_init_out; + +msm_display_init_out: + return ret; +} + +/* This has to be called from soc init, with right MDP rev */ +int display_init(const char *panel_name, uint32_t rev, struct edid *ed) +{ + int ret = NO_ERROR; + int pan_type; + dsi_video_mode_phy_db.pll_type = DSI_PLL_TYPE_10NM; + printk(BIOS_INFO, " display init!\n"); + pan_type = oem_panel_select(panel_name, &panelstruct, + &(panel.panel_info), + &dsi_video_mode_phy_db); + if (pan_type == PANEL_TYPE_DSI) { + if (update_dsi_display_config()) + goto error_display_init; + target_dsi_phy_config(&dsi_video_mode_phy_db); + if (dsi_panel_init(&(panel.panel_info), &panelstruct)) { + printk(BIOS_ERR, "DSI panel init failed!\n"); + ret = ERROR; + goto error_display_init; + } + panel.panel_info.mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db; + panel.pll_clk_func = mdss_dsi_panel_clock; + panel.power_func = mdss_dsi_panel_power; + panel.pre_init_func = mdss_dsi_panel_pre_init; + panel.bl_func = mdss_dsi_bl_enable; + + panel.fb.base = NULL; /* Filled in DC */ + panel.fb.width = panel.panel_info.xres; + panel.fb.height = panel.panel_info.yres; + panel.fb.stride = panel.panel_info.xres; + panel.fb.bpp = panel.panel_info.bpp; + panel.fb.format = panel.panel_info.mipi.dst_format; + panel.fb.sbpp = FRAMEBUFFER_SRC_BPP; + if (ed != NULL) { + ed->mode.ha = panel.panel_info.xres; + ed->mode.va = panel.panel_info.yres; + ed->framebuffer_bits_per_pixel = FRAMEBUFFER_SRC_BPP; + } + } else { + printk(BIOS_ERR, "Target panel init not found!\n"); + ret = ERROR; + goto error_display_init; + } + panel.mdp_rev = rev; + ret = msm_display_init(&panel); + +error_display_init: + display_enable = ret ? 0 : 1; + return ret; +} + +void sc7180_display_init(struct device *dev) +{ + /* Restricting display hw initialization to cheza boards only */ + static struct edid ed; + printk(BIOS_INFO, "sc7180 display init!\n"); + display_init(NULL, MDSS_MDP_HW_REV_620, &ed); + edid_set_framebuffer_bits_per_pixel(&ed, ed.framebuffer_bits_per_pixel, + 0); + set_vbe_mode_info_valid(&ed, (uintptr_t)0); +} diff --git a/src/soc/qualcomm/sc7180/display/mdss.c b/src/soc/qualcomm/sc7180/display/mdss.c new file mode 100644 index 0000000..f949729 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/mdss.c @@ -0,0 +1,679 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <stdlib.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mdss_6_2_0.h> +#include <soc/display/target_sc7180.h> +#include <soc/display/msm_panel.h> +#include <soc/display/mipi_dsi.h> + +#define MDSS_MDP_MAX_PREFILL_FETCH 25 + +uint32_t mdss_mdp_intf_offset(void); + +void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info + *pinfo); + +void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo); + +int mdp_dsi_video_off(struct msm_panel_info *pinfo); + +int mdp_dsi_cmd_off(void); + +static int mdp_rev; + +void mdp_set_revision(int rev) +{ + mdp_rev = rev; +} + +int mdp_get_revision(void) +{ + return mdp_rev; +} + +uint32_t mdss_mdp_intf_offset(void) +{ + return 0; +} + +static uint32_t mdss_mdp_get_ppb_offset(void) +{ + uint32_t mdss_mdp_ppb_off = 0; + uint32_t mdss_mdp_rev = readl(MDP_HW_REV); + + /* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */ + if (mdss_mdp_rev == MDSS_MDP_HW_REV_620) + mdss_mdp_ppb_off = 0x1420; //TODO: check if it is required atall + else + printk(BIOS_ERR, "Invalid PPB0_CONFIG offset\n"); + + return mdss_mdp_ppb_off; +} + +static void mdp_select_pipe_type(struct msm_panel_info *pinfo, + uint32_t *left_pipe, uint32_t *right_pipe) +{ + switch (pinfo->pipe_type) { + + case MDSS_MDP_PIPE_TYPE_DMA: + *left_pipe = MDP_VP_0_DMA_0_BASE; + *right_pipe = MDP_VP_0_DMA_1_BASE; + break; + + case MDSS_MDP_PIPE_TYPE_VIG: + default: + *left_pipe = MDP_VP_0_VIG_0_BASE; + *right_pipe = MDP_VP_0_VIG_1_BASE; + break; + } +} + +static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, + uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) +{ + bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe && + !pinfo->mipi.dual_dsi && + !pinfo->lcdc.split_display; + + *ctl0_reg_val = BIT(17); /*attach ctl path */ + *ctl1_reg_val = BIT(17); + + switch (pinfo->pipe_type) { + + case MDSS_MDP_PIPE_TYPE_DMA: + if (dual_pipe_single_ctl) + *ctl0_reg_val |= BIT(12)| BIT(11) | BIT(6) | BIT(7); + else + *ctl0_reg_val |= BIT(12) | BIT(11) | BIT(6); + + *ctl1_reg_val |= BIT(12)| BIT(7); + + if (pinfo->lcdc.dst_split) + *ctl0_reg_val |= BIT(12); + break; + + case MDSS_MDP_PIPE_TYPE_VIG: + default: + if (dual_pipe_single_ctl) + *ctl0_reg_val |= BIT(0)| BIT(1) |BIT(6) | BIT(7); + else + *ctl0_reg_val |= BIT(0)| BIT(6); + + *ctl1_reg_val |= BIT(7)|BIT(1); + + if (pinfo->lcdc.dst_split) + *ctl0_reg_val |= BIT(1); + + break; + } + + *ctl0_reg_val |= BIT(31); /*Interface flush */ + *ctl1_reg_val |= BIT(31); +} + +static void mdss_source_pipe_config(struct fbcon_config *fb, + struct msm_panel_info *pinfo, + uint32_t pipe_base) +{ + uint32_t img_size, out_size, stride; + uint32_t fb_off = 0; + uint32_t flip_bits = 0; + uint32_t src_xy = 0; + uint32_t dst_xy = 0; + uint32_t height, width; + + height = fb->height - pinfo->border_top - pinfo->border_bottom; + width = fb->width - pinfo->border_left - pinfo->border_right; + + /* write active region size*/ + img_size = (height << 16) | width; + out_size = img_size; + + if (pinfo->lcdc.dual_pipe) { + + if ((pipe_base == MDP_VP_0_DMA_1_BASE) || + (pipe_base == MDP_VP_0_VIG_1_BASE)) { + fb_off = (pinfo->xres / 2); + out_size = (height << 16) + (pinfo->lm_split[1]); + } + else { + out_size = (height << 16) + (pinfo->lm_split[0]); + } + } + + stride = (fb->stride * fb->sbpp/8); + + if (fb_off == 0) { /* left */ + dst_xy = (pinfo->border_top << 16) | pinfo->border_left; + src_xy = dst_xy; + } else { /* right */ + dst_xy = (pinfo->border_top << 16); + src_xy = (pinfo->border_top << 16) | fb_off; + } + + printk(BIOS_INFO, "%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", + __func__, out_size, fb_off, src_xy, dst_xy); + + writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); + + writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); + writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); + writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY); + writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY); + + /* Tight Packing 4bpp Alpha 8-bit A R B G */ + writel(0x000236ff, pipe_base + PIPE_SSPP_SRC_FORMAT); + writel(0x03020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); + + /* bit(0) is set if hflip is required. + * bit(1) is set if vflip is required. + */ + if (pinfo->orientation & 0x1) + flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR; + if (pinfo->orientation & 0x2) + flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD; + + flip_bits |= BIT(31); + writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C0_REQ); + writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C1C2_REQ); + writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C3_REQ); + writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE); + +} + +static void mdss_vbif_setup(void) +{ + writel(0x33333333, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); + writel(0x00333333, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); +} + +static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) +{ + uint32_t hsync_period, vsync_period; + uint32_t hsync_start_x, hsync_end_x; + uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; + uint32_t adjust_xres = 0; + uint32_t upper = 0, lower = 0; + + struct lcdc_panel_info *lcdc = NULL; + struct intf_timing_params itp = {0}; + + if (pinfo == NULL) + return; + + lcdc = &(pinfo->lcdc); + if (lcdc == NULL) + return; + + adjust_xres = pinfo->xres; + if (pinfo->lcdc.split_display) { + if (pinfo->lcdc.dst_split) { + adjust_xres /= 2; + } else if (pinfo->lcdc.dual_pipe) { + if (intf_base == + (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) + adjust_xres = pinfo->lm_split[0]; + else + adjust_xres = pinfo->lm_split[1]; + } + + if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) { + if (pinfo->lcdc.pipe_swap) { + lower |= BIT(4); + upper |= BIT(8); + } else { + lower |= BIT(8); + upper |= BIT(4); + } + writel(lower, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); + writel(upper, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); + writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); + } + } + + if (pinfo->lcdc.dst_split && + (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) { + uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); + + writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CNTL */ + writel(BIT(16) | (0x3 << 20), REG_MDP(ppb_offset + 0x4)); + } + + itp.xres = adjust_xres; + itp.yres = pinfo->yres; + itp.width = (adjust_xres + pinfo->lcdc.xres_pad); + + if (pinfo->compression_mode == COMPRESSION_DSC) { + itp.xres = pinfo->dsc.pclk_per_line; + itp.width = pinfo->dsc.pclk_per_line; + } + + itp.height = pinfo->yres + pinfo->lcdc.yres_pad; + itp.h_back_porch = pinfo->lcdc.h_back_porch; + itp.h_front_porch = pinfo->lcdc.h_front_porch; + itp.v_back_porch = pinfo->lcdc.v_back_porch; + itp.v_front_porch = pinfo->lcdc.v_front_porch; + itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; + itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; + + itp.border_clr = pinfo->lcdc.border_clr; + itp.underflow_clr = pinfo->lcdc.underflow_clr; + itp.hsync_skew = pinfo->lcdc.hsync_skew; + + hsync_period = itp.hsync_pulse_width + itp.h_back_porch + + itp.width + itp.h_front_porch; + + vsync_period = itp.vsync_pulse_width + itp.v_back_porch + + itp.height + itp.v_front_porch; + + hsync_start_x = itp.hsync_pulse_width + + itp.h_back_porch; + hsync_end_x = hsync_period - itp.h_front_porch - 1; + + display_vstart = (itp.vsync_pulse_width + + itp.v_back_porch) * + hsync_period + itp.hsync_skew; + + display_vend = ((vsync_period - itp.v_front_porch) * hsync_period) + + itp.hsync_skew - 1; + + if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) { /* eDP */ + display_vstart += itp.hsync_pulse_width + itp.h_back_porch; + display_vend -= itp.h_front_porch; + } + + hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width; + display_hctl = (hsync_end_x << 16) | hsync_start_x; + + writel(hsync_ctl, MDP_HSYNC_CTL + intf_base); + writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + + intf_base); + writel(itp.vsync_pulse_width*hsync_period, + MDP_VSYNC_PULSE_WIDTH_F0 + + intf_base); + writel(display_hctl, MDP_DISPLAY_HCTL + intf_base); + writel(display_vstart, MDP_DISPLAY_V_START_F0 + + intf_base); + writel(display_vend, MDP_DISPLAY_V_END_F0 + + intf_base); + writel(itp.underflow_clr, MDP_UNDERFFLOW_COLOR + intf_base); + writel(0x2100, MDP_PANEL_FORMAT + intf_base); +} + +static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo, + uint32_t intf_base) +{ + uint32_t v_total, h_total, fetch_start, vfp_start; + uint32_t prefetch_avail, prefetch_needed; + uint32_t adjust_xres = 0; + uint32_t fetch_enable = BIT(31); + + struct lcdc_panel_info *lcdc = NULL; + + if (pinfo == NULL) + return; + + lcdc = &(pinfo->lcdc); + if (lcdc == NULL) + return; + + /* + * MDP programmable fetch is for MDP with rev >= 1.05. + * Programmable fetch is not needed if vertical back porch + * plus vertical puls width is >= 25. + */ + if ((lcdc->v_back_porch + lcdc->v_pulse_width) >= MDSS_MDP_MAX_PREFILL_FETCH) + return; + + adjust_xres = pinfo->xres; + if (pinfo->lcdc.split_display) { + if (pinfo->lcdc.dst_split) { + adjust_xres /= 2; + } else if (pinfo->lcdc.dual_pipe) { + if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) + adjust_xres = pinfo->lm_split[0]; + else + adjust_xres = pinfo->lm_split[1]; + } + } + + if (pinfo->compression_mode == COMPRESSION_DSC) + adjust_xres = pinfo->dsc.pclk_per_line; + + /* + * Fetch should always be outside the active lines. If the fetching + * is programmed within active region, hardware behavior is unknown. + */ + v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres + + lcdc->v_front_porch; + h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres + + lcdc->h_front_porch; + vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres; + + prefetch_avail = v_total - vfp_start; + prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - lcdc->v_back_porch - + lcdc->v_pulse_width; + + /* + * In some cases, vertical front porch is too high. In such cases limit + * the mdp fetch lines as the last (25 - vbp - vpw) lines of + * vertical front porch. + */ + if (prefetch_avail > prefetch_needed) + prefetch_avail = prefetch_needed; + + fetch_start = (v_total - prefetch_avail) * h_total+ h_total + 1; + + if (pinfo->dfps.panel_dfps.enabled) + fetch_enable |= BIT(23); //TODO: this shoudld not be enabled ? + + writel(fetch_start, MDP_PROG_FETCH_START + intf_base); + + writel(fetch_enable, MDP_INTF_CONFIG + intf_base); + +} + +void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info + *pinfo) +{ + uint32_t mdp_rgb_size, height, width; + uint32_t left_staging_level, right_staging_level; + + height = fb->height; + width = fb->width; + + if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) + width = pinfo->lm_split[0]; + + /* write active region size*/ + mdp_rgb_size = (height << 16) | width; + + writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); + writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); + + for (int i = 0; i < 6; i++) { + writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP(i)); + writel(0x00ff0000, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_CONST_ALPHA(i)); + } + + left_staging_level =BIT(24); //attach border + right_staging_level=BIT(24); + + switch (pinfo->pipe_type) { + case MDSS_MDP_PIPE_TYPE_DMA: + left_staging_level |= BIT(18); + right_staging_level |= BIT(21); + break; + case MDSS_MDP_PIPE_TYPE_VIG: + default: + left_staging_level |= BIT(1); + right_staging_level |= BIT(3); + break; + } + + /* + * When ping-pong split is enabled and two pipes are used, + * both the pipes need to be staged on the same layer mixer. + */ + if (pinfo->lcdc.dual_pipe && pinfo->lcdc.dst_split) + left_staging_level |= right_staging_level; + + /* Base layer for layer mixer 0 */ + writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); + + if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) { + /* write active region size*/ + mdp_rgb_size = (height << 16) | pinfo->lm_split[1]; + + writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); + writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); + + for (int i = 0; i < 6; i++) { + writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP(i)); + writel(0x00ff0000, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_CONST_ALPHA(i)); + } + + /* Base layer for layer mixer 1 */ + if (pinfo->lcdc.split_display) + writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); + else + writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); + } +} + +void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo) +{ + writel(0x00000003, MDSS_VBIF_RT_BASE + 0x550); + writel(0x11111113, MDSS_VBIF_RT_BASE + 0x558); + writel(0x22222224, MDSS_VBIF_RT_BASE + 0x560); + writel(0x33333334, MDSS_VBIF_RT_BASE + 0x568); + writel(0x44444445, MDSS_VBIF_RT_BASE + 0x570); + writel(0x77777776, MDSS_VBIF_RT_BASE + 0x588); + writel(0x00000003, MDSS_VBIF_RT_BASE + 0x590); + writel(0x11111113, MDSS_VBIF_RT_BASE + 0x598); + writel(0x22222224, MDSS_VBIF_RT_BASE + 0x5a0); + writel(0x33333334, MDSS_VBIF_RT_BASE + 0x5a8); + writel(0x44444445, MDSS_VBIF_RT_BASE + 0x5b0); + writel(0x77777776, MDSS_VBIF_RT_BASE + 0x5c8); + +} + +static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, + int is_main_ctl) +{ + uint32_t mctl_intf_sel; + uint32_t sctl_intf_sel; + + if ((pinfo->dest == DISPLAY_2) || + ((pinfo->dest == DISPLAY_1) && (pinfo->lcdc.pipe_swap))) { + mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ + sctl_intf_sel = BIT(5); /* Interface 1 */ + } else { + mctl_intf_sel = BIT(5); /* Interface 1 */ + sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ + } + printk(BIOS_INFO, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__, + (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1", + (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1"); + return is_main_ctl ? mctl_intf_sel : sctl_intf_sel; +} + +static void mdp_set_intf_base(struct msm_panel_info *pinfo, + uint32_t *intf_base, uint32_t *sintf_base) +{ + if (pinfo->dest == DISPLAY_2) { + *intf_base = MDP_INTF_2_BASE; + *sintf_base = MDP_INTF_1_BASE; + } else { + *intf_base = MDP_INTF_1_BASE; + *sintf_base = MDP_INTF_2_BASE; + } +} + +int mdp_dsi_video_config(struct msm_panel_info *pinfo, + struct fbcon_config *fb) +{ + uint32_t intf_sel, sintf_sel; + uint32_t intf_base, sintf_base; + uint32_t left_pipe, right_pipe; + uint32_t reg; + + mdp_set_intf_base(pinfo, &intf_base, &sintf_base); + + mdss_intf_tg_setup(pinfo, intf_base); + mdss_intf_fetch_start_config(pinfo, intf_base); + + if (pinfo->mipi.dual_dsi) { + mdss_intf_tg_setup(pinfo, sintf_base); + mdss_intf_fetch_start_config(pinfo, sintf_base); + } + + mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); + mdss_vbif_setup(); + mdss_vbif_qos_remapper_setup(pinfo); + + mdss_source_pipe_config(fb, pinfo, left_pipe); + + if (pinfo->lcdc.dual_pipe) + mdss_source_pipe_config(fb, pinfo, right_pipe); + + mdss_layer_mixer_setup(fb, pinfo); + reg = mdss_mdp_ctl_out_sel(pinfo, 1); /*Selecting interface 1 */ + + /* enable 3D mux for dual_pipe but single interface config */ + if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && + !pinfo->lcdc.split_display) { + + if (pinfo->num_dsc_enc != 2) + reg |= BIT(19) | BIT(20); + } + + writel(0x0F0000, MDP_INTF_1_BASE + INTF_MUX); + writel(0x0, MDP_CTL_0_BASE + CTL_TOP); + writel(BIT(1), MDP_CTL_0_BASE + CTL_INTF_ACTIVE); /*Selecting interface 1 */ + + if ((pinfo->compression_mode == COMPRESSION_DSC) && + pinfo->dsc.mdp_dsc_config) { + struct dsc_desc *dsc = &pinfo->dsc; + + if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && + !pinfo->lcdc.split_display && (pinfo->num_dsc_enc == 2)) { + dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, + MDP_DSC_0_BASE, true, true); + + dsc->mdp_dsc_config(pinfo, MDP_PP_1_BASE, + MDP_DSC_1_BASE, true, true); + + } else if (pinfo->lcdc.dual_pipe && pinfo->mipi.dual_dsi && + pinfo->lcdc.split_display && (pinfo->num_dsc_enc == 1)) { + dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, + MDP_DSC_0_BASE, false, false); + dsc->mdp_dsc_config(pinfo, MDP_PP_1_BASE, + MDP_DSC_1_BASE, false, false); + + } else { + dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, + MDP_DSC_0_BASE, false, false); + } + } + + /* + * if dst_split is enabled, intf 1 & 2 needs to be enabled but + * CTL_1 path should not be set since CTL_0 itself is going + * to split after DSPP block and drive both intf. + */ + if (pinfo->mipi.dual_dsi) { + if (!pinfo->lcdc.dst_split) { + reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 0); + writel(reg, MDP_CTL_1_BASE + CTL_TOP); + } + + intf_sel |= sintf_sel; /* INTF 2 enable */ + } + + return 0; +} + +int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, + struct fbcon_config *fb) +{ + int ret = NO_ERROR; + return ret; +} + +int mdp_dsi_video_on(struct msm_panel_info *pinfo) +{ + uint32_t ctl0_reg_val, ctl1_reg_val; + + writel(0x2, MDP_CTL_0_BASE + CTL_INTF_FLUSH); + mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); + writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); + + if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split){ + writel(0x4, MDP_CTL_1_BASE + CTL_INTF_FLUSH); + writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); + } + + return NO_ERROR; +} + +static void mdp_set_cmd_autorefresh_mode(struct msm_panel_info *pinfo) +{ + uint32_t total_lines = 0, vclks_line = 0, cfg = 0; + + if (!pinfo || (pinfo->type != MIPI_CMD_PANEL) || !pinfo->autorefresh_enable) + return; + + total_lines = pinfo->lcdc.v_front_porch + + pinfo->lcdc.v_back_porch + + pinfo->lcdc.v_pulse_width + + pinfo->border_top + pinfo->border_bottom + + pinfo->yres; + + total_lines *= pinfo->mipi.frame_rate; + + vclks_line = (total_lines) ? 19200000 / total_lines : 0; + vclks_line = vclks_line * pinfo->mipi.frame_rate * 100 / 6000; + + cfg = BIT(19) | vclks_line; + + /* Configure tearcheck VSYNC param */ + writel(cfg, MDP_REG_PP_0_SYNC_CONFIG_VSYNC); + + if (pinfo->lcdc.dst_split) + writel(cfg, MDP_REG_PP_SLAVE_SYNC_CONFIG_VSYNC); + + if (pinfo->lcdc.dual_pipe) + writel(cfg, MDP_REG_PP_1_SYNC_CONFIG_VSYNC); + dsb(); + + /* Enable autorefresh mode */ + writel((BIT(31) | pinfo->autorefresh_framenum), + MDP_REG_PP_0_AUTOREFRESH_CONFIG); + + if (pinfo->lcdc.dst_split) + writel((BIT(31) | pinfo->autorefresh_framenum), + MDP_REG_PP_SLAVE_AUTOREFRESH_CONFIG); + + if (pinfo->lcdc.dual_pipe) + writel((BIT(31) | pinfo->autorefresh_framenum), + MDP_REG_PP_1_AUTOREFRESH_CONFIG); + + dsb(); +} + +int mdp_dma_on(struct msm_panel_info *pinfo) +{ + uint32_t ctl0_reg_val, ctl1_reg_val; + + mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); + + writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); + + if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) + writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); + + if (pinfo->autorefresh_enable) + mdp_set_cmd_autorefresh_mode(pinfo); + + writel(0x01, MDP_CTL_0_BASE + CTL_START); + + return NO_ERROR; +} + diff --git a/src/soc/qualcomm/sc7180/display/oem_panel.c b/src/soc/qualcomm/sc7180/display/oem_panel.c new file mode 100644 index 0000000..da90398 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/oem_panel.c @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/mmio.h> +#include <lib.h> +#include <stdlib.h> +#include <console/console.h> +#include <delay.h> +#include <soc/display/msm_panel.h> +#include <soc/display/mipi_dsi.h> +#include <soc/display/target_sc7180.h> +#include <soc/display/panel_display.h> +#include <soc/mdss_6_2_0.h> +#include <soc/display/panel_sn65dsix6_auo_bll6xak01_dsi_video.h> + +enum { + HW_PLATFORM_MTP, + HW_PLATFORM_PROTO, +}; + +enum { + SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_PANEL, + UNKNOWN_PANEL +}; + +/* + * The list of panels that are supported on this target. + */ +static struct panel_list supp_panels[] = { + {"sn65dsix6_auo_b116xak01_dsi_video", + SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_PANEL}, +}; + +static uint32_t panel_id; +#define SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_PANEL_DELAY 40 + +int oem_panel_bridge_chip_init(struct msm_panel_info *pinfo); + +int oem_panel_rotation(void) +{ + return NO_ERROR; +} + +int oem_panel_on(void) +{ + if (panel_id == SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_PANEL) { + /* needs extra delay to avoid unexpected artifacts */ + mdelay(SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_PANEL_DELAY); + } + + return NO_ERROR; +} + +int oem_panel_off(void) +{ + return NO_ERROR; +} + +static int init_panel_data(struct panel_struct *panelstruct, + struct msm_panel_info *pinfo, + struct mdss_dsi_phy_ctrl *phy_db) +{ + int pan_type = PANEL_TYPE_DSI; + + switch (panel_id) { + case SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_PANEL: + pan_type = PANEL_TYPE_DSI; + panelstruct->paneldata + = &sn65dsix6_auo_b116xak01_dsi_video_panel_data; + panelstruct->paneldata->panel_with_enable_gpio = 0; + panelstruct->panelres + = &sn65dsix6_auo_b116xak01_dsi_video_panel_res; + panelstruct->color + = &sn65dsix6_auo_b116xak01_dsi_video_color; + panelstruct->videopanel + = &sn65dsix6_auo_b116xak01_dsi_video_panel; + panelstruct->commandpanel + = &sn65dsix6_auo_b116xak01_dsi_video_command_panel; + panelstruct->state + = &sn65dsix6_auo_b116xak01_dsi_video_state; + panelstruct->laneconfig + = &sn65dsix6_auo_b116xak01_dsi_video_lane_config; + panelstruct->paneltiminginfo + = &sn65dsix6_auo_b116xak01_dsi_video_timing_info; + panelstruct->panelresetseq + = &sn65dsix6_auo_b116xak01_dsi_video_panel_reset_seq; + pinfo->mipi.panel_on_cmds + = sn65dsix6_auo_b116xak01_dsi_video_on_command; + pinfo->mipi.num_of_panel_on_cmds + = SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_ON_COMMAND; + pinfo->mipi.panel_off_cmds + = sn65dsix6_auo_b116xak01_dsi_video_off_command; + pinfo->mipi.num_of_panel_off_cmds + = SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_OFF_COMMAND; + memcpy(phy_db->timing, + sn65dsix6_auo_b116xak01_dsi_video_timings, + MAX_TIMING_CONFIG * sizeof(uint32_t)); + break; + default: + case UNKNOWN_PANEL: + pan_type = PANEL_TYPE_UNKNOWN; + break; + } + + return pan_type; +} + +int oem_panel_bridge_chip_init(struct msm_panel_info *pinfo) +{ + return target_set_switch_gpio(1); +} + +int oem_panel_select(const char *panel_name, struct panel_struct *panelstruct, + struct msm_panel_info *pinfo, + struct mdss_dsi_phy_ctrl *phy_db) +{ + uint32_t hw_id = HW_PLATFORM_PROTO; + int32_t panel_override_id; + uint32_t ret = 0; + + phy_db->pll_type = DSI_PLL_TYPE_10NM; + + if (panel_name) { + panel_override_id = panel_name_to_id(supp_panels, + ARRAY_SIZE(supp_panels), panel_name); + + if (panel_override_id < 0) { + printk(BIOS_ERR, "Not able to search the panel:%s\n", + panel_name); + } else if (panel_override_id < UNKNOWN_PANEL) { + panel_id = panel_override_id; + printk(BIOS_INFO, "OEM panel override:%s\n", + panel_name); + goto panel_init; + } + } + + switch (hw_id) { + case HW_PLATFORM_PROTO: + panel_id = SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_PANEL; + pinfo->has_bridge_chip = true; + break; + case HW_PLATFORM_MTP: + default: + printk(BIOS_ERR, "Display not enabled for %d HW type\n" + , hw_id); + return PANEL_TYPE_UNKNOWN; + } + +panel_init: + if (pinfo->has_bridge_chip) { + ret = oem_panel_bridge_chip_init(pinfo); + if (ret) { + printk(BIOS_ERR, "Error initializing bridge chip\n"); + return ret; + } + } + return init_panel_data(panelstruct, pinfo, phy_db); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/display.h b/src/soc/qualcomm/sc7180/include/soc/display.h new file mode 100644 index 0000000..20cd748 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QCOM_SC7180_DISPLAY_H__ +#define __SOC_QCOM_SC7180_DISPLAY_H__ + +#include <edid.h> + +void sc7180_display_init(struct device *dev); +int display_init(const char *panel_name, uint32_t rev, struct edid *ed); + +#endif + diff --git a/src/soc/qualcomm/sc7180/include/soc/display/panel_sn65dsix6_auo_bll6xak01_dsi_video.h b/src/soc/qualcomm/sc7180/include/soc/display/panel_sn65dsix6_auo_bll6xak01_dsi_video.h new file mode 100644 index 0000000..a783e03 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/panel_sn65dsix6_auo_bll6xak01_dsi_video.h @@ -0,0 +1,281 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2020 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PANEL_SN65DSIX6_AUO_BLL6XAK01_DSI_VIDEO_H_ +#define _PANEL_SN65DSIX6_AUO_BLL6XAK01_DSI_VIDEO_H_ + +#include "panel.h" + +static char panel_node_id[256] = "qcom,dsi_sn65dsix6_auo_b116xak01_video"; +static char panel_controller[256] = "dsi:0:"; /* panel_controller */ +static char panel_compatible[256] = "qcom,mdss-dsi-panel"; +static char panel_destination[256] = "DISPLAY_1"; +static char slave_panel_node_id[256] = "qcom,dsi_sn65dsix6_auo_b116xak01_video"; + +static struct panel_config sn65dsix6_auo_b116xak01_dsi_video_panel_data = { + panel_node_id, + panel_controller, + panel_compatible, + 10, /* panel_interface */ + 0, /* panel_type */ + panel_destination, + 0, /* panel_orientation */ + 0, /* panel_clockrate */ + 60, /* panel_framerate */ + 0, /* panel_channelid */ + 0, /* dsi_virtualchannel_id */ + 0, /* panel_broadcast_mode */ + 0, /* panel_lp11_init */ + 0, /* panel_init_delay */ + 0, /* dsi_stream */ + 0, /* interleave_mode */ + 0, /* panel_bitclock_freq */ + 0, /* panel_operating_mode */ + 0, /* panel_with_enable_gpio */ + 0, /* mode_gpio_state */ + slave_panel_node_id, +}; + +static struct panel_resolution sn65dsix6_auo_b116xak01_dsi_video_panel_res = { + 1366, /* panel_width .*/ + 768, /* panel_height .*/ + 48, /* hfront_porch .*/ + 10, /* hback_porch .*/ + 32, /* hpulse_width .*/ + 0, /* hsync_skew .*/ + 4, /* vfront_porch .*/ + 15, /* vback_porch .*/ + 6, /* vpulse_width .*/ + 0, /* hleft_border .*/ + 0, /* hright_border .*/ + 0, /* vtop_border .*/ + 0, /* vbottom_border .*/ + 0, /* hactive_res */ + 0, /* uint16_t vactive_res */ + 0, /* invert_data_polarity */ + 0, /* invert_vsync_polarity */ + 0, /* invert_hsync_polarity */ +}; + +static struct color_info sn65dsix6_auo_b116xak01_dsi_video_color = { + 24, /* color_format */ + 0, /* color_order */ + 0, /* underflow_color */ + 0, /* border_color */ + 0, /* pixel_packing */ + 0, /* pixel_alignment */ +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd1[] = { + 0x5c, 0x01, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd2[] = { + 0x0a, 0x02, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd3[] = { + 0x10, 0x20, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd4[] = { + 0x12, 0x29, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd5[] = { + 0x5a, 0x05, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd6[] = { + 0x93, 0x10, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd7[] = { + 0x94, 0x81, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd8[] = { + 0x0d, 0x01, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd9[] = { + 0x64, 0x01, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd10[] = { + 0x74, 0x00, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd11[] = { + 0x75, 0x01, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd12[] = { + 0x76, 0x0a, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd13[] = { + 0x77, 0x01, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd14[] = { + 0x78, 0x81, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd15[] = { + 0x96, 0x0a, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd16[] = { + 0x20, 0x56, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd17[] = { + 0x21, 0x05, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd18[] = { + 0x24, 0x00, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd19[] = { + 0x25, 0x03, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd20[] = { + 0x2c, 0x20, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd21[] = { + 0x2d, 0x00, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd22[] = { + 0x30, 0x06, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd23[] = { + 0x31, 0x00, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd24[] = { + 0x34, 0x0a, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd25[] = { + 0x36, 0x0f, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd26[] = { + 0x38, 0x30, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd27[] = { + 0x3a, 0x04, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd28[] = { + 0x5b, 0x01, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd29[] = { + 0x3c, 0x00, 0x23, 0x80 +}; + +static char sn65dsix6_auo_b116xak01_dsi_video_on_cmd30[] = { + 0x5a, 0x0d, 0x23, 0x80 +}; + +static struct mipi_dsi_cmd sn65dsix6_auo_b116xak01_dsi_video_on_command[] = { + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd1, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd2, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd3, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd4, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd5, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd6, 0xff}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd7, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd8, 0xff}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd9, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd10, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd11, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd12, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd13, 0xff}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd14, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd15, 0xff}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd16, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd17, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd18, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd19, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd20, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd21, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd22, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd23, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd24, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd25, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd26, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd27, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd28, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd29, 0x10}, + {0x4, sn65dsix6_auo_b116xak01_dsi_video_on_cmd30, 0x10}, +}; + +#define SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_ON_COMMAND 30 + +static struct mipi_dsi_cmd sn65dsix6_auo_b116xak01_dsi_video_off_command[] = { +}; + +#define SN65DSIX6_AUO_B116XAK01_DSI_VIDEO_OFF_COMMAND 0 + +static struct command_state sn65dsix6_auo_b116xak01_dsi_video_state = { + 0, 1 +}; + +static struct commandpanel_info sn65dsix6_auo_b116xak01_dsi_video_command_panel = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static struct videopanel_info sn65dsix6_auo_b116xak01_dsi_video_panel = { + 0, /* hsync_pulse */ + 0, /* hfp_power_mode */ + 0, /* hbp_power_mode */ + 0, /* hsa_power_mode */ + 1, /* bllp_eof_power_mode */ + 1, /* bllp_power_mode */ + 0, /* traffic_mode */ + 0, /* dma_delayafter_vsync */ + 0x9, /* bllp_eof_power */ +}; + +static struct lane_configuration sn65dsix6_auo_b116xak01_dsi_video_lane_config = { +/* For Proto0, due to the incorrect schematic we have to set + force_clk_lane_hs because we are supporting only 384Mhz continuous clock +*/ + 4, 0, 1, 1, 1, 1, 1 +}; + +static const uint32_t sn65dsix6_auo_b116xak01_dsi_video_timings[] = { + 0x0, 0x11, 0x3, 0x5, 0x1E, 0x1E, 0x4, 0x4, 0x2, 0x3, 0x4 +}; + +static struct panel_timing sn65dsix6_auo_b116xak01_dsi_video_timing_info = { + 0x0, 0x04, 0x0c, 0x2d +}; + +static struct panel_reset_sequence + sn65dsix6_auo_b116xak01_dsi_video_panel_reset_seq = { + {1, 0, 1, }, {20, 20, 50, }, 2 +}; + +#endif diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index fbcfc6e..c0b11ae 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (C) 2018-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -19,6 +19,7 @@ #include <soc/mmu_common.h> #include <soc/symbols.h> #include <soc/aop.h> +#include <soc/display.h> static void soc_read_resources(struct device *dev) { @@ -33,6 +34,9 @@ static void soc_init(struct device *dev) { aop_fw_load_reset(); +#if CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT) + sc7180_display_init(dev); +#endif } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/39615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e Gerrit-Change-Number: 39615 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

9 53

Change in coreboot[master]: sc7180: Add support for sn65dsi86 bridge.
by Ravi kumar (Code Review) 09 Sep '20

09 Sep '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42899 ) Change subject: sc7180: Add support for sn65dsi86 bridge. ...................................................................... sc7180: Add support for sn65dsi86 bridge. Add sn65dsi86 bridge driver to enable the eDP bridge. Change-Id: I36a68f3241f0ba316c261a73c2f6d30fe6c3ccdc Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org> --- A src/drivers/ti/sn65dsi86bridge/Kconfig A src/drivers/ti/sn65dsi86bridge/Makefile.inc A src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c A src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h 4 files changed, 548 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42899/1 diff --git a/src/drivers/ti/sn65dsi86bridge/Kconfig b/src/drivers/ti/sn65dsi86bridge/Kconfig new file mode 100644 index 0000000..1a37409 --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/Kconfig @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config DRIVERS_TI_SN65DSI86BRIDGE + bool + default y + help + TI SN65DSI86BRIDGE diff --git a/src/drivers/ti/sn65dsi86bridge/Makefile.inc b/src/drivers/ti/sn65dsi86bridge/Makefile.inc new file mode 100644 index 0000000..c46eb6d --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_TI_SN65DSI86BRIDGE) += sn65dsi86bridge.c \ No newline at end of file diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c new file mode 100644 index 0000000..3fda4f9 --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -0,0 +1,398 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <endian.h> +#include <device/i2c_simple.h> +#include <edid.h> +#include <timer.h> +#include <types.h> +#include <soc/addressmap.h> +#include "sn65dsi86bridge.h" + +#define bridge_debug(x...) do {if (0) printk(BIOS_DEBUG, x); } while (0) + +#define BRIDGE_GETHIGHERBYTE(x) (uint8_t)((x&0xFF00)>>8) +#define BRIDGE_GETLOWERBYTE(x) (uint8_t)((x&0x00FF)) + +/* fudge factor required to account for 8b/10b encoding */ +#define DP_CLK_FUDGE_NUM 10 +#define DP_CLK_FUDGE_DEN 8 + +/* DPCD */ +#define DP_BRIDGE_DPCD_REV 0x700 +#define DP_BRIDGE_11 0x00 +#define DP_BRIDGE_12 0x01 +#define DP_BRIDGE_13 0x02 +#define DP_BRIDGE_14 0x03 +#define DP_BRIDGE_CONFIGURATION_SET 0x10a +#define DP_MAX_LINK_RATE 0x001 +#define DP_MAX_LANE_COUNT 0x002 +#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ +#define DP_MAX_LINK_RATE 0x001 +#define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ + +/* link configuration */ +#define DP_LINK_BW_SET 0x100 +#define DP_LINK_BW_1_62 0x06 +#define DP_LINK_BW_2_7 0x0a +#define DP_LINK_BW_5_4 0x14 + +#define AUX_CMD_SEND 0x1 +#define MIN_DSI_CLK_FREQ_MHZ 40 + +/* + * LUT index corresponds to register value and + * LUT values corresponds to dp data rate supported + * by the bridge in Mbps unit. + */ +static const unsigned int sn65dsi86_bridge_dp_rate_lut[] = { + 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 +}; + +enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out) +{ + int ret; + u8 edid[EDID_LENGTH * 2]; + int edid_size = EDID_LENGTH; + + /* Send I2C command to Disable the HPD */ + i2c_writeb(bus, chip, SN_HPD_DISABLE_REG, 0x1); + + /* Send I2C command to claim EDID I2c slave */ + i2c_writeb(bus, chip, I2C_CLAIM_ADDR_EN1, (EDID_I2C_ADDR << 1) | 0x1); + + /* read EDID */ + ret = i2c_read_bytes(bus, EDID_I2C_ADDR, 0x0, edid, EDID_LENGTH); + if (ret != 0) { + printk(BIOS_ERR, "ERROR: Failed to read EDID.\n"); + return CB_ERR; + } + + if (edid[EDID_EXTENSION_FLAG]) { + edid_size += EDID_LENGTH; + ret = i2c_read_bytes(bus, EDID_I2C_ADDR, EDID_LENGTH, + &edid[EDID_LENGTH], EDID_LENGTH); + if (ret != 0) { + printk(BIOS_ERR, "Failed to read EDID ext block.\n"); + return CB_ERR; + } + } + + if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) { + printk(BIOS_ERR, "ERROR: Failed to decode EDID.\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} + +static void sn65dsi86_bridge_dpcd_request(uint8_t bus, + uint8_t chip, + unsigned int dpcd_reg, + unsigned int len, + enum dpcd_request request, + uint8_t *data) +{ + int i; + uint32_t length; + uint8_t buf; + uint8_t reg; + + while (len) { + length = MIN(len, 16); + + i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (dpcd_reg >> 16) & 0xF); + i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (dpcd_reg >> 8) & 0xFF); + i2c_writeb(bus, chip, SN_AUX_ADDR_7_0_REG, (dpcd_reg) & 0xFF); + i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length); /* size of 1 Byte data */ + if (request == DPCD_WRITE) { + reg = SN_AUX_WDATA_REG_0; + for (i = 0; i < length; i++) + i2c_writeb(bus, chip, reg++, *data++); + + i2c_writeb(bus, chip, + SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_WRITE << 4)); + } else { + i2c_writeb(bus, chip, + SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_READ << 4)); + if (!wait_ms(100, + !i2c_readb(bus, chip, SN_AUX_CMD_REG, + &buf) && !(buf & AUX_CMD_SEND))) { + printk(BIOS_ERR, "ERROR: aux command send failed\n"); + } + + reg = SN_AUX_RDATA_REG_0; + for (i = 0; i < length; i++) { + i2c_readb(bus, chip, reg++, &buf); + *data++ = buf; + } + } + + len -= length; + } +} + +static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate_valid[]) +{ + unsigned int rate_per_200khz; + unsigned int rate_mhz; + uint8_t dpcd_val; + int i, j; + + sn65dsi86_bridge_dpcd_request(bus, chip, + DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val); + if (dpcd_val >= DP_BRIDGE_14) { + /* eDP 1.4 devices must provide a custom table */ + uint8_t sink_rates[DP_MAX_SUPPORTED_RATES * 2]; + + sn65dsi86_bridge_dpcd_request(bus, chip, DP_SUPPORTED_LINK_RATES, + ARRAY_SIZE(sink_rates), + DPCD_READ, sink_rates); + for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { + rate_per_200khz = le16_to_cpu(sink_rates[i]); + + if (!rate_per_200khz) + break; + + rate_mhz = rate_per_200khz * 200 / 1000; + for (j = 0; + j < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut); + j++) { + if (sn65dsi86_bridge_dp_rate_lut[j] == rate_mhz) + rate_valid[j] = true; + } + } + + for (i = 0; i < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut); i++) { + if (rate_valid[i]) + return; + } + + printk(BIOS_ERR, "No matching eDP rates in table; falling back\n"); + } + + /* On older versions best we can do is use DP_MAX_LINK_RATE */ + sn65dsi86_bridge_dpcd_request(bus, chip, + DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); + + switch (dpcd_val) { + default: + printk(BIOS_ERR, + "Unexpected max rate (%#x); assuming 5.4 GHz\n", + (int)dpcd_val); + /* fall through */ + case DP_LINK_BW_5_4: + rate_valid[7] = 1; + /* fall through */ + case DP_LINK_BW_2_7: + rate_valid[4] = 1; + /* fall through */ + case DP_LINK_BW_1_62: + rate_valid[1] = 1; + break; + } +} + +static void sn65dsi86_bridge_set_dsi_clock_range(uint8_t bus, uint8_t chip, + struct edid *edid, + int num_of_lanes, int bpp) +{ + uint64_t pixel_clk_hz; + uint64_t stream_bit_rate_mhz; + uint64_t min_req_dsi_clk; + + pixel_clk_hz = edid->mode.pixel_clock * 1000; + stream_bit_rate_mhz = (pixel_clk_hz / 1000000) * bpp; + + /* For TI the clock frequencies are half the bit rates */ + min_req_dsi_clk = stream_bit_rate_mhz / (num_of_lanes * 2); + + /* for each increment in val, frequency increases by 5MHz */ + min_req_dsi_clk = (MIN_DSI_CLK_FREQ_MHZ / 5) + + (((min_req_dsi_clk - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); + + i2c_writeb(bus, chip, SN_DSIA_CLK_FREQ_REG, min_req_dsi_clk); +} + +static void sn65dsi86_bridge_set_dp_clock_range(uint8_t bus, uint8_t chip, + struct edid *edid, int num_of_lanes) +{ + uint64_t stream_bit_rate_khz; + bool rate_valid[ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut)] = { }; + uint64_t dp_rate_mhz; + int dp_rate_idx, i; + + stream_bit_rate_khz = edid->mode.pixel_clock * 18; + + /* Calculate minimum DP data rate, taking 80% as per DP spec */ + dp_rate_mhz = DIV_ROUND_UP(stream_bit_rate_khz * DP_CLK_FUDGE_NUM, + 1000 * num_of_lanes * DP_CLK_FUDGE_DEN); + + for (i = 0; i < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut) - 1; i++) + if (sn65dsi86_bridge_dp_rate_lut[i] > dp_rate_mhz) + break; + + sn65dsi86_bridge_valid_dp_rates(bus, chip, rate_valid); + + /* Train until we run out of rates */ + for (dp_rate_idx = i; + dp_rate_idx < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut); + dp_rate_idx++) + if (rate_valid[dp_rate_idx]) + break; + + if(dp_rate_idx < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut)) + i2c_write_field(bus, chip, SN_DATARATE_CONFIG_REG, dp_rate_idx, 8, 5); + else + printk(BIOS_ERR, "ERROR: valid dp rate not found"); +} + +static void sn65dsi86_bridge_set_bridge_active_timing(uint8_t bus, + uint8_t chip, + struct edid *edid) +{ + i2c_writeb(bus, chip, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.ha)); + i2c_writeb(bus, chip, SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.ha)); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.va)); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.va)); + i2c_writeb(bus, chip, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.hspw)); + i2c_writeb(bus, chip, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.hspw)); + i2c_writeb(bus, chip, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.vspw)); + i2c_writeb(bus, chip, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.vspw)); + i2c_writeb(bus, chip, SN_CHA_HORIZONTAL_BACK_PORCH_REG, + edid->mode.hbl - edid->mode.hso - edid->mode.hspw); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_BACK_PORCH_REG, + edid->mode.vbl - edid->mode.vso - edid->mode.vspw); + i2c_writeb(bus, chip, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, + edid->mode.hso); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_FRONT_PORCH_REG, + edid->mode.vso); +} + +static void sn65dsi86_bridge_link_training(uint8_t bus, uint8_t chip) +{ + uint8_t buf; + + /* enable pll lock */ + i2c_writeb(bus, chip, SN_PLL_ENABLE_REG, 0x1); + + if (!wait_ms(500, + !(i2c_readb(bus, chip, SN_DPPLL_SRC_REG, &buf)) && + (buf & BIT(7)))) { + printk(BIOS_ERR, "ERROR: PLL lock failure\n"); + } + + /* + * The SN65DSI86 only supports ASSR Display Authentication method and + * this method is enabled by default. An eDP panel must support this + * authentication method. We need to enable this method in the eDP panel + * at DisplayPort address 0x0010A prior to link training. + */ + buf = 0x1; + sn65dsi86_bridge_dpcd_request(bus, chip, + DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf); + + /* semi auto link training mode */ + i2c_writeb(bus, chip, SN_ML_TX_MODE_REG, 0xa); + + if (!wait_ms(500, + !(i2c_readb(bus, chip, SN_ML_TX_MODE_REG, &buf)) && + (buf & NORMAL_MODE))) { + printk(BIOS_ERR, "ERROR: Link training failed"); + } + +} + +static enum cb_err sn65dsi86_bridge_get_plug_in_status(uint8_t bus, uint8_t chip) +{ + int val; + uint8_t buf; + + val = i2c_readb(bus, chip, SN_HPD_DISABLE_REG, &buf); + if (val == 0 && (buf & HPD_DISABLE)) + return CB_SUCCESS; + + return CB_ERR; +} + +/* + * support bridge HPD function + * some hardware version do not support bridge hdp, + * we use 360ms to try to get the hpd single now, + * if we can not get bridge hpd single, it will delay 360ms, + * also meet the bridge power timing request, to compatible + * all of the hardware version + */ +static void sn65dsi86_bridge_wait_hpd(uint8_t bus, uint8_t chip) +{ + if (wait_ms(360, sn65dsi86_bridge_get_plug_in_status(bus, chip))) + return; + + printk(BIOS_WARNING, "HPD detection failed, force hpd\n"); + + /* Force HPD */ + i2c_write_field(bus, chip, SN_HPD_DISABLE_REG, HPD_DISABLE, 1, 0 ); +} + +static void sn65dsi86_bridge_assr_config(uint8_t bus, uint8_t chip, int enable) +{ + if (enable) + i2c_write_field(bus, chip, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1, 3); + else + i2c_write_field(bus, chip, SN_ENH_FRAME_REG, VSTREAM_DISABLE, 1, 3); +} + +static int sn65dsi86_bridge_dp_lane_config(uint8_t bus, uint8_t chip) +{ + uint8_t data; + + sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LANE_COUNT, 1, DPCD_READ, &data); + i2c_write_field(bus, chip, SN_SSC_CONFIG_REG, MIN(data, 3), 3, 4); + + return data; +} + +void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, + struct edid *edid, uint32_t num_of_lanes, + uint8_t ref_clk, uint32_t bpp) +{ + int dp_lanes; + + sn65dsi86_bridge_wait_hpd(bus, chip); + + /* set refclk to 19.2 MHZ */ + i2c_write_field(bus, chip, SN_DPPLL_SRC_REG, ref_clk, 7, 1); + + /* DSI Lanes config */ + i2c_write_field(bus, chip, SN_DSI_LANES_REG, (4 - num_of_lanes), 3, 3); + + /* DP Lane config */ + dp_lanes = sn65dsi86_bridge_dp_lane_config(bus, chip); + + sn65dsi86_bridge_set_dsi_clock_range(bus, chip, edid, num_of_lanes ,bpp); + + sn65dsi86_bridge_set_dp_clock_range(bus, chip, edid, dp_lanes); + + /* Disable vstream */ + sn65dsi86_bridge_assr_config(bus, chip, 0); + sn65dsi86_bridge_link_training(bus, chip); + sn65dsi86_bridge_set_bridge_active_timing(bus, chip, edid); + + /* DP BPP config */ + i2c_writeb(bus, chip, SN_DATA_FORMAT_REG, (uint8_t)0x01); + + /* color bar disabled */ + i2c_writeb(bus, chip, SN_COLOR_BAR_REG, 0x5); + + /* Enable vstream */ + sn65dsi86_bridge_assr_config(bus, chip, 1); +} diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h new file mode 100644 index 0000000..b8a9b6e --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __TI_SN65DSI86BRIDGE_H +#define __TI_SN65DSI86BRIDGE_H + +#include <edid.h> + +enum bridge_regs { + SN_DPPLL_SRC_REG = 0x0A, + SN_PLL_ENABLE_REG = 0x0D, + SN_DSI_LANES_REG = 0x10, + SN_DSIA_CLK_FREQ_REG = 0x12, + SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG = 0x20, + SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG = 0x21, + SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG = 0x24, + SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG = 0x25, + SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG = 0x2C, + SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG = 0x2D, + SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG = 0x30, + SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG = 0x31, + SN_CHA_HORIZONTAL_BACK_PORCH_REG = 0x34, + SN_CHA_VERTICAL_BACK_PORCH_REG = 0x36, + SN_CHA_HORIZONTAL_FRONT_PORCH_REG = 0x38, + SN_CHA_VERTICAL_FRONT_PORCH_REG = 0x3A, + SN_COLOR_BAR_REG = 0x3C, + SN_ENH_FRAME_REG = 0x5A, + SN_DATA_FORMAT_REG = 0x5B, + SN_HPD_DISABLE_REG = 0x5C, + SN_AUX_WDATA_REG_0 = 0x64, + SN_AUX_WDATA_REG_1 = 0x65, + SN_AUX_WDATA_REG_2 = 0x66, + SN_AUX_WDATA_REG_3 = 0x67, + SN_AUX_WDATA_REG_4 = 0x68, + SN_AUX_WDATA_REG_5 = 0x69, + SN_AUX_WDATA_REG_6 = 0x6A, + SN_AUX_WDATA_REG_7 = 0x6B, + SN_AUX_WDATA_REG_8 = 0x6C, + SN_AUX_WDATA_REG_9 = 0x6D, + SN_AUX_WDATA_REG_10 = 0x6E, + SN_AUX_WDATA_REG_11 = 0x6F, + SN_AUX_WDATA_REG_12 = 0x70, + SN_AUX_WDATA_REG_13 = 0x71, + SN_AUX_WDATA_REG_14 = 0x72, + SN_AUX_WDATA_REG_15 = 0x73, + SN_AUX_ADDR_19_16_REG = 0x74, + SN_AUX_ADDR_15_8_REG = 0x75, + SN_AUX_ADDR_7_0_REG = 0x76, + SN_AUX_LENGTH_REG = 0x77, + SN_AUX_CMD_REG = 0x78, + SN_AUX_RDATA_REG_0 = 0x79, + SN_AUX_RDATA_REG_1 = 0x7A, + SN_AUX_RDATA_REG_2 = 0x7B, + SN_AUX_RDATA_REG_3 = 0x7C, + SN_AUX_RDATA_REG_4 = 0x7D, + SN_AUX_RDATA_REG_5 = 0x7E, + SN_AUX_RDATA_REG_6 = 0x7F, + SN_AUX_RDATA_REG_7 = 0x80, + SN_AUX_RDATA_REG_8 = 0x81, + SN_AUX_RDATA_REG_9 = 0x82, + SN_AUX_RDATA_REG_10 = 0x83, + SN_AUX_RDATA_REG_11 = 0x84, + SN_AUX_RDATA_REG_12 = 0x85, + SN_AUX_RDATA_REG_13 = 0x86, + SN_AUX_RDATA_REG_14 = 0x87, + SN_AUX_RDATA_REG_15 = 0x88, + SN_SSC_CONFIG_REG = 0x93, + SN_DATARATE_CONFIG_REG = 0x94, + SN_ML_TX_MODE_REG = 0x96, + SN_AUX_CMD_STATUS_REG = 0xF4, +}; + +enum { + HPD_ENABLE = 0x0, + HPD_DISABLE = 0x1 , +}; + +enum { + SOT_ERR_TOL_DSI = 0x0, + CHB_DSI_LANES = 0x1, + CHA_DSI_LANES = 0x2, + DSI_CHANNEL_MODE = 0x3, + LEFT_RIGHT_PIXELS = 0x4, +}; + +enum vstream_config { + VSTREAM_DISABLE = 0, + VSTREAM_ENABLE = 1, +}; + +enum dp_pll_clk_src { + SN65_SEL_12MHZ = 0x0, + SN65_SEL_19MHZ = 0x1, + SN65_SEL_26MHZ = 0x2, + SN65_SEL_27MHZ = 0x3, + SN65_SEL_38MHZ = 0x4, +}; + +enum i2c_over_aux { + I2C_OVER_AUX_WRITE_MOT_0 = 0x0, + I2C_OVER_AUX_READ_MOT_0 = 0x1, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x4, + I2C_OVER_AUX_WRITE_MOT_1 = 0x5, + I2C_OVER_AUX_READ_MOT_1 = 0x6, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x7, + NATIVE_AUX_WRITE = 0x8, + NATIVE_AUX_READ = 0x9, +}; + +enum ml_tx_mode { + MAIN_LINK_OFF = 0x0, + NORMAL_MODE = 0x1, + TPS1 = 0x2, + TPS2 = 0x3, + TPS3 = 0x4, + PRBS7 = 0x5, + HBR2_COMPLIANCE_EYE_PATTERN = 0x6, + SYMBOL_ERR_RATE_MEASUREMENT_PATTERN = 0x7, + CUTSOM_PATTERN = 0x8, + FAST_LINK_TRAINING = 0x9, + SEMI_AUTO_LINK_TRAINING = 0xa, + REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb, +}; + +enum dpcd_request { + DPCD_READ = 0x0, + DPCD_WRITE = 0x1, +}; + +enum { + EDID_LENGTH = 128, + EDID_I2C_ADDR = 0x50, + I2C_CLAIM_ADDR_EN1 = 0x60, + EDID_EXTENSION_FLAG = 0x7e, +}; + +void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, + struct edid *edid, uint32_t num_of_lines, + uint8_t ref_clk, uint32_t bpp); +enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out); +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a68f3241f0ba316c261a73c2f6d30fe6c3ccdc Gerrit-Change-Number: 42899 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 31

Change in coreboot[master]: mb/intel/tglrvp: Enable HECI interface
by Tim Wawrzynczak (Code Review) 09 Sep '20

09 Sep '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42307 ) Change subject: mb/intel/tglrvp: Enable HECI interface ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Gerrit-Change-Number: 42307 Gerrit-PatchSet: 6 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 10 Sep 2020 00:25:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7180: enable bl31
by mturney mturney (Code Review) 09 Sep '20

09 Sep '20

Hello ashk(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35504 to review the following change. Change subject: sc7180: enable bl31 ...................................................................... sc7180: enable bl31 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/28014/44 Change-Id: Ia961ee0e30478e21fd786ce464655977449df510 Signed-off-by: ashk <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35504/1 diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index df5d116..28f7522 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -6,6 +6,7 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select GENERIC_GPIO_LIB select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index f4e6f05..e47f881 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -72,7 +72,7 @@ REGION(dram_reserved1, 0x80820000, 0x20000, 0x1000) REGION(dram_reserved, 0x80900000, 0x200000, 0x1000) /* Various hardware/software subsystems make use of this area */ - BL31(0x85000000, 0x1A800000) + BL31(0x80C00000, 0x1A800000) POSTRAM_CBFS_CACHE(0x9F800000, 384K) RAMSTAGE(0x9F860000, 2M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/35504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia961ee0e30478e21fd786ce464655977449df510 Gerrit-Change-Number: 35504 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

7 24

Change in coreboot[master]: HACK trogdor: Memlayout changed to support QcLib Size increase
by mturney mturney (Code Review) 09 Sep '20

09 Sep '20

Hello ashk(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36277 to review the following change. Change subject: HACK trogdor: Memlayout changed to support QcLib Size increase ...................................................................... HACK trogdor: Memlayout changed to support QcLib Size increase Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4 Signed-off-by: Ashwin Kumar <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36277/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index ce260aa..6ca3e95 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -59,10 +59,10 @@ REGION(ddr_training, 0x14850000, 8K, 4K) REGION(qclib_serial_log, 0x14852000, 4K, 4K) REGION(ddr_information, 0x14853000, 1K, 1K) - REGION(dcb, 0x14870000, 16K, 4K) - REGION(pmic, 0x14874000, 44K, 4K) - REGION(limits_cfg, 0x1487F000, 4K, 4K) - REGION(qclib, 0x14880000, 512K, 4K) + REGION(dcb, 0x1485b000, 16K, 4K) + REGION(pmic, 0x1485f000, 44K, 4K) + REGION(limits_cfg, 0x1486a000, 4K, 4K) + REGION(qclib, 0x1486b000, 596K, 4K) BSRAM_END(0x14900000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/36277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4 Gerrit-Change-Number: 36277 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-MessageType: newchange

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