coreboot-gerrit September 2020

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Change in coreboot[master]: drivers/ti/sn65dsi86bridge: Fix broken HPD by just delaying
by Douglas Anderson (Code Review) 29 Sep '20

29 Sep '20

Douglas Anderson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45744 ) Change subject: drivers/ti/sn65dsi86bridge: Fix broken HPD by just delaying ...................................................................... drivers/ti/sn65dsi86bridge: Fix broken HPD by just delaying The HPD code we had was hilariously broken. 1. sn65dsi86_bridge_get_plug_in_status() - didn't actually check anything useful. It read the i2c part, and then checked bit 0 (not bit 4). Bit 0 is where we have manually programmed the HPD disable. Bit 4 is the actual value read from HPD. Thus it would only return CB_SUCCESS we have already programmed the HPD disable (we haven't). So it will always return CB_ERR 2. The return value of sn65dsi86_bridge_get_plug_in_status() is used directly as the stop condition for wait_ms(). That means that the error return causes us to stop waiting. So if we fix sn65dsi86_bridge_get_plug_in_status() then we'll end up exiting right away. HPD is pretty useless on this bridge chip and on every panel I've seen so far a 200 ms delay is fine. Let's just do that. Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Change-Id: Id8b497c5ce9b6d92141b42438787485096dbcb8a --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c 1 file changed, 20 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/45744/1 diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index e0058c4..dce3718 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -426,30 +426,28 @@ } -static enum cb_err sn65dsi86_bridge_get_plug_in_status(uint8_t bus, uint8_t chip) -{ - int val; - uint8_t buf; - - val = i2c_readb(bus, chip, SN_HPD_DISABLE_REG, &buf); - if (val == 0 && (buf & HPD_DISABLE)) - return CB_SUCCESS; - - return CB_ERR; -} - -/* - * support bridge HPD function some hardware versions do not support bridge hdp, - * we use 360ms to try to get the hpd single now, if we can not get bridge hpd single, - * it will delay 360ms, also meet the bridge power timing request, to be compatible - * all of the hardware versions - */ static void sn65dsi86_bridge_wait_hpd(uint8_t bus, uint8_t chip) { - if (wait_ms(400, sn65dsi86_bridge_get_plug_in_status(bus, chip))) - return; - - printk(BIOS_WARNING, "HPD detection failed, force hpd\n"); + /* + * From the Linux kernel driver: + * + * HPD on this bridge chip is a bit useless. This is an eDP bridge + * so the HPD is an internal signal that's only there to signal that + * the panel is done powering up. ...but the bridge chip debounces + * this signal by between 100 ms and 400 ms (depending on process, + * voltage, and temperate--I measured it at about 200 ms). One + * particular panel asserted HPD 84 ms after it was powered on meaning + * that we saw HPD 284 ms after power on. + * + * Some boards may route HPD to a 2nd place on the board so it can + * be polled faster, but since we're not in a crazy hurry let's just + * hardcode a delay. + * + * Every panel datasheet I've seen says that HPD will be asserted + * within 200 ms. Let's just hardcode the delay and then tell the + * bridge to ignore HPD. + */ + mdelay(200); /* Force HPD */ i2c_write_field(bus, chip, SN_HPD_DISABLE_REG, HPD_DISABLE, 1, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/45744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8b497c5ce9b6d92141b42438787485096dbcb8a Gerrit-Change-Number: 45744 Gerrit-PatchSet: 1 Gerrit-Owner: Douglas Anderson <dianders(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Christian Walter (Code Review) 29 Sep '20

29 Sep '20

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 66: (1 comment) https://review.coreboot.org/c/coreboot/+/37441/64/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md: https://review.coreboot.org/c/coreboot/+/37441/64/Documentation/mainboard/s… PS64, Line 31: 0x235=03 and 0x13E=84 > I don't know. […] It is the TPM on SPI Enable Flag, and Setting the SPI Frequency to 40Mhz. Vendor Firmware does enable this during runtime - but we need to patch it in the IFD. -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 66 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 28 Sep 2020 21:54:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/lynxpoint: Expand RCBA register list
by Angel Pons (Code Review) 29 Sep '20

29 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40062 ) Change subject: sb/intel/lynxpoint: Expand RCBA register list ...................................................................... sb/intel/lynxpoint: Expand RCBA register list Some registers do not seem to exist, and many were missing. Change-Id: I6757f4a748cde9f3bed3bacf32112f3259de1d87 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pch.h 1 file changed, 91 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40062/1 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 0a62803..6d6590a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -445,45 +445,11 @@ /* Southbridge IO BARs */ +#define PMBASE 0x40 #define GPIOBASE 0x48 -#define PMBASE 0x40 +#define CIR0050 0x0050 /* 32bit */ -#define VCH 0x0000 /* 32bit */ -#define VCAP1 0x0004 /* 32bit */ -#define VCAP2 0x0008 /* 32bit */ -#define PVC 0x000c /* 16bit */ -#define PVS 0x000e /* 16bit */ - -#define V0CAP 0x0010 /* 32bit */ -#define V0CTL 0x0014 /* 32bit */ -#define V0STS 0x001a /* 16bit */ - -#define V1CAP 0x001c /* 32bit */ -#define V1CTL 0x0020 /* 32bit */ -#define V1STS 0x0026 /* 16bit */ - -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - -#define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ /* Root Port configuratinon space hide */ @@ -495,6 +461,9 @@ /* Root Port function number mask */ #define RPFN_FNMASK(port) (7 << ((port) * 4)) +#define CIR0900 0x0900 /* 32bit */ +#define CIR1100 0x1100 /* 32bit */ + #define TRSR 0x1e00 /* 8bit */ #define TRCR 0x1e10 /* 64bit */ #define TWDR 0x1e18 /* 64bit */ @@ -504,6 +473,41 @@ #define IOTR2 0x1e90 /* 64bit */ #define IOTR3 0x1e98 /* 64bit */ +#define V0CTL 0x2014 /* 32bit */ +#define V0STS 0x201a /* 16bit */ + +#define V1CTL 0x2020 /* 32bit */ +#define V1STS 0x2026 /* 16bit */ + +#define VPCTL 0x2030 /* 32bit */ +#define VPSTS 0x2038 /* 16bit */ + +#define VMCTL 0x2040 /* 32bit */ +#define VMSTS 0x2048 /* 16bit */ + +#define CIR2088 0x2088 +#define REC 0x20ac +#define LCAP 0x21a4 +#define LCTL 0x21a8 +#define DMIC 0x2234 +#define CIR2238 0x2238 +#define CIR228C 0x228c +#define DMC 0x2304 +#define CIR2314 0x2314 +#define CIR2320 0x2320 + +/* IO Buffer Programming */ +#define IOBPIRI 0x2330 +#define IOBPD 0x2334 +#define IOBPS 0x2338 +#define IOBPS_READY 0x0001 +#define IOBPS_TX_MASK 0x0006 +#define IOBPS_MASK 0xff00 +#define IOBPS_READ 0x0600 +#define IOBPS_WRITE 0x0700 +#define IOBPU 0x233a +#define IOBPU_MAGIC 0xf000 + #define TCTL 0x3000 /* 8bit */ #define NOINT 0 @@ -526,18 +530,6 @@ #define PIRQG 6 #define PIRQH 7 -/* IO Buffer Programming */ -#define IOBPIRI 0x2330 -#define IOBPD 0x2334 -#define IOBPS 0x2338 -#define IOBPS_READY 0x0001 -#define IOBPS_TX_MASK 0x0006 -#define IOBPS_MASK 0xff00 -#define IOBPS_READ 0x0600 -#define IOBPS_WRITE 0x0700 -#define IOBPU 0x233a -#define IOBPU_MAGIC 0xf000 - #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ #define D31IP_SIP2 20 /* SATA Pin 2 */ @@ -581,26 +573,66 @@ #define D20IR 0x3160 /* 16bit */ #define D21IR 0x3164 /* 16bit */ #define D19IR 0x3168 /* 16bit */ -#define ACPIIRQEN 0x31e0 /* 32bit */ -#define OIC 0x31fe /* 16bit */ -#define PMSYNC_CONFIG 0x33c4 /* 32bit */ -#define PMSYNC_CONFIG2 0x33cc /* 32bit */ -#define SOFT_RESET_CTRL 0x38f4 -#define SOFT_RESET_DATA 0x38f8 -#define DIR_ROUTE(a,b,c,d) \ - (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) +#define ACPIIRQEN 0x31e0 /* 32bit */ + +#define OIC 0x31fe /* 16bit */ + +#define PRSTS 0x3310 +#define CIR3314 0x3314 +#define PM_CFG 0x3318 +#define CIR3324 0x3324 +#define DEEP_S3_POL 0x3328 +#define DEEP_S4_POL 0x332c +#define DEEP_S5_POL 0x3330 +#define PM_CFG2 0x333c +#define CIR3340 0x3340 +#define CIR3344 0x3344 +#define CIR3348 0x3348 +#define CIR3350 0x3350 +#define CIR3360 0x3360 +#define CIR3368 0x3368 +#define CIR3378 0x3378 +#define CIR337C 0x337c +#define CIR3388 0x3388 +#define CIR3390 0x3390 +#define CIR33A0 0x33a0 +#define CIR33B0 0x33b0 +#define CIR33C0 0x33c0 +#define PMSYNC_CONFIG 0x33c4 /* 32bit */ +#define PMSYNC 0x33c8 +#define PMSYNC_CONFIG2 0x33cc /* 32bit */ +#define CIR33D0 0x33d0 +#define CIR33D4 0x33d4 #define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ #define GCS 0x3410 /* 32bit */ #define BUC 0x3414 /* 32bit */ -#define PCH_DISABLE_GBE (1 << 5) +#define PCH_DISABLE_GBE (1 << 5) +#define RC 0x3400 /* 32bit */ +#define HPTC 0x3404 /* 32bit */ +#define GCS 0x3410 /* 32bit */ +#define BUC 0x3414 /* 32bit */ #define FD 0x3418 /* 32bit */ +#define CG 0x341c /* 32bit */ +#define FDSW 0x3420 #define DISPBDF 0x3424 /* 16bit */ #define FD2 0x3428 /* 32bit */ -#define CG 0x341c /* 32bit */ +#define GSX_CTRL 0x3454 + +#define CIR3A28 0x3a28 +#define CIR3A2C 0x3a2c +#define CIR3A6C 0x3a6c +#define CIR3A80 0x3a80 +#define CIR3A84 0x3a84 +#define CIR3A88 0x3a88 + +#define SOFT_RESET_CTRL 0x38f4 +#define SOFT_RESET_DATA 0x38f8 + +#define DIR_ROUTE(a, b, c, d) \ + (((d) << DIR_IDR) | ((c) << DIR_ICR) | ((b) << DIR_IBR) | ((a) << DIR_IAR)) /* Function Disable 1 RCBA 0x3418 */ #define PCH_DISABLE_ALWAYS (1 << 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/40062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6757f4a748cde9f3bed3bacf32112f3259de1d87 Gerrit-Change-Number: 40062 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Angel Pons (Code Review) 29 Sep '20

29 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 66: (8 comments) https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/gpio.c: https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 9: /* GPP_A0 - ESPI_ALERT1# */ > done for x11 lga1151. […] Gone. https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 6: > what about GPE config? What is it necessary for? https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 23: register "PcieRpEnable[1]" = "1" : register "PcieRpEnable[5]" = "1" : register "PcieRpEnable[8]" = "1" : register "PcieRpEnable[20]" = "1" : register "PcieRpEnable[21]" = "1" > These should be moved into the corresponding PCIe root port devices, alongside the clkreq and clksrc […] Ack. ClkReq/ClkSrc doesn't seem to follow RP mapping, and has been left out for now. https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 10: port" = "1" : register "SataPortsEnable[0]" = "1" : register "SataPortsEnable[1]" = "1" : register "SataPortsEnable[2]" = "1" : register "SataPortsEnable[3]" = "1" : register "SataPortsEnable[4]" = "1" : register "SataPortsEnable[5]" = "1" : register "SataPortsEnable[6]" = "1" : register "SataPortsEnable[7]" = "1" : : register "PchHdaDspEnable" = "0" : register "PchHdaAudioLinkHda" = "1" : : register "PcieRpEnable[1]" = "1" : register "PcieRpEnable[5]" = "1" : register "PcieRpEnable[8]" = "1" : register "PcieRpEnable[20]" = "1" : register "PcieRpEnable[21]" = "1" : : register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80" : register "PcieClkSrcUsage[6]" = "0x80" : register "PcieClkSrcUsage[7]" = "0x80" : register "PcieClkSrcUsage[8]" = "0x80" : register "PcieClkSrcUsage[9]" = "0x80" : register "PcieClkSrcUsage[10]" = "0x80" : register "PcieClkSrcUsage[11]" = "0x80" : register "PcieClkSrcUsage[12]" = "0x80" : register "PcieClkSrcUsage[13]" = "0x80" : register "PcieClkSrcUsage[14]" = "0x80" : register "PcieClkSrcUsage[15]" = "0x80" : : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : register "PcieClkSrcClkReq[6]" = "6" : register "PcieClkSrcClkReq[7]" = "7" : register "PcieClkSrcClkReq[8]" = "8" : register "PcieClkSrcClkReq[9]" = "9" : register "PcieClkSrcClkReq[10]" = "10" : register "PcieClkSrcClkReq[11]" = "11" : register "PcieClkSrcClkReq[12]" = "12" : register "PcieClkSrcClkReq[13]" = "13" : register "PcieClkSrcClkReq[14]" = "14" : register "PcieClkSrcClkReq[15]" = "1 > alignment? Ack https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 29: register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80" : register "PcieClkSrcUsage[6]" = "0x80" : register "PcieClkSrcUsage[7]" = "0x80" : register "PcieClkSrcUsage[8]" = "0x80" : register "PcieClkSrcUsage[9]" = "0x80" : register "PcieClkSrcUsage[10]" = "0x80" : register "PcieClkSrcUsage[11]" = "0x80" : register "PcieClkSrcUsage[12]" = "0x80" : register "PcieClkSrcUsage[13]" = "0x80" : register "PcieClkSrcUsage[14]" = "0x80" : register "PcieClkSrcUsage[15]" = "0x80" : : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : register "PcieClkSrcClkReq[6]" = "6" : register "PcieClkSrcClkReq[7]" = "7" : register "PcieClkSrcClkReq[8]" = "8" : register "PcieClkSrcClkReq[9]" = "9" : register "PcieClkSrcClkReq[10]" = "10" : register "PcieClkSrcClkReq[11]" = "11" : register "PcieClkSrcClkReq[12]" = "12" : register "PcieClkSrcClkReq[13]" = "13" : register "PcieClkSrcClkReq[14]" = "14" : register "PcieClkSrcClkReq[15]" = "15" > Drop clksrc and clkreq for unused ports, shouldn't be needed. Given the non-linear mapping between PCIe RPs and clksrc/clkreq pins, it is not trivial to determine which of them are unused without access to the board. https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 100: # Enable "Intel Speed Shift Technology" : register "speed_shift_enable" = "1" : > move to series? Ack https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 104: register "HeciEnabled" = "1" > Put this inside the ME Interface 1 device in devicetree Ack https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 109: register "InternalGfx" = "1" > Put this inside the iGPU device in the devicetree Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 66 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 28 Sep 2020 21:35:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Angel Pons (Code Review) 29 Sep '20

29 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 66: (15 comments) https://review.coreboot.org/c/coreboot/+/37441/64/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md: https://review.coreboot.org/c/coreboot/+/37441/64/Documentation/mainboard/s… PS64, Line 31: 0x235=03 and 0x13E=84 > o. […] I don't know. Probably fTPM https://review.coreboot.org/c/coreboot/+/37441/64/Documentation/mainboard/s… PS64, Line 41: Coffe > Coffee Ack https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 3: > lockdown missing This should be a Kconfig setting. https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 10: device pci 01.0 on end > missing comment Ack https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/… PS64, Line 16: device pci 14.2 on end > missing comment Ack https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 10: device pci 01.0 on end > Missing comment. Ack https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 16: device pci 14.2 on end > Missing comment. I've no idea of what this is https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 19: device pci 16.0 on end # Management Engine Interface > Add interface number Ack https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 20: device pci 16.1 on end # Management Engine Interface > Same Ack https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 21: device pci 16.4 on end # Management Engine Interface > Same Ack https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 23: device pci 1c.1 on > Missing comment. Ack https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 20: register "PchHdaDspEnable" = "0" > drop disabled options Ack https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 29: register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80" : register "PcieClkSrcUsage[6]" = "0x80" : register "PcieClkSrcUsage[7]" = "0x80" : register "PcieClkSrcUsage[8]" = "0x80" : register "PcieClkSrcUsage[9]" = "0x80" : register "PcieClkSrcUsage[10]" = "0x80" : register "PcieClkSrcUsage[11]" = "0x80" : register "PcieClkSrcUsage[12]" = "0x80" : register "PcieClkSrcUsage[13]" = "0x80" : register "PcieClkSrcUsage[14]" = "0x80" : register "PcieClkSrcUsage[15]" = "0x80" : : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : register "PcieClkSrcClkReq[6]" = "6" : register "PcieClkSrcClkReq[7]" = "7" : register "PcieClkSrcClkReq[8]" = "8" : register "PcieClkSrcClkReq[9]" = "9" : register "PcieClkSrcClkReq[10]" = "10" : register "PcieClkSrcClkReq[11]" = "11" : register "PcieClkSrcClkReq[12]" = "12" : register "PcieClkSrcClkReq[13]" = "13" : register "PcieClkSrcClkReq[14]" = "14" : register "PcieClkSrcClkReq[15]" = "15" : > drop the ones for disabled ports Looks like the clksrc/clkreq mapping isn't linear. https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 110: : # Disable S0ix : register "s0ix_enable" = "0" : > drop disabled functions Ack https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 114: device domain 0 on > Please add root port numbers. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 66 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 28 Sep 2020 21:32:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Angel Pons (Code Review) 29 Sep '20

29 Sep '20

Angel Pons has uploaded a new patch set (#66) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F This is a µATX UP server mainboard with a LGA1151 socket and four DDR4 DIMM slots. Unlike existing boards, this one supports Coffee Lake CPUs instead of Skylake and Kaby Lake, thus it is not added as a variant. Working: - Aspeed AST2500 graphics output - Serial console - SuperIO devicetree config - Boots into Linux 5.5 - Tested payload EDK II - SATA ports - USB ports - IPMI KCS - LinuxBoot - No ACPI error in Windows/Linux - Windows 10 support - TPM Support (w/ patched IFD) - Patch IFD at 0x235=0x03 and 0x13E=0x84 Tested with Intel Xeon E-2186G and 64 GB of ECC UDIMMs. Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f_flash.jpg M MAINTAINERS A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c A src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb A src/mainboard/supermicro/x11-lga1151v2-series/dsdt.asl A src/mainboard/supermicro/x11-lga1151v2-series/gpio.h A src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c A src/mainboard/supermicro/x11-lga1151v2-series/romstage.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb 18 files changed, 788 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37441/66 -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 66 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] mb/asrock/h110m: add libgfxinit support
by Angel Pons (Code Review) 29 Sep '20

29 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39104 ) Change subject: [WIP] mb/asrock/h110m: add libgfxinit support ...................................................................... Patch Set 13: (2 comments) https://review.coreboot.org/c/coreboot/+/39104/13//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39104/13//COMMIT_MSG@14 PS13, Line 14: - EDP_TXN[2] -> EDP_VGA_TX0# : - EDP_TXN[3] -> EDP_VGA_TX1# : - EDP_TXP[2] -> EDP_VGA_TX0 : - EDP_TXP[2] -> EDP_VGA_TX1 Where does this come from? https://review.coreboot.org/c/coreboot/+/39104/13/src/mainboard/asrock/h110… File src/mainboard/asrock/h110m/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/39104/13/src/mainboard/asrock/h110… PS13, Line 12: (DP2, -- DVI (DDI2) : HDMI3, -- HDMI (DDI3) : eDP, -- eDP->VGA (PTN3356R1BS) : others => Disabled); On SKL/KBL-S there are three DDIs plus one eDP port. Two of these DDIs are used for HDMI/DVI, and either the third DDI or eDP is wired to the DP-to-VGA converter. There should be two HDMIx entries and either one DPx or eDP. -- To view, visit https://review.coreboot.org/c/coreboot/+/39104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d87413f87d00986111ecb7b046423ff5eac1bf1 Gerrit-Change-Number: 39104 Gerrit-PatchSet: 13 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 28 Sep 2020 21:10:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/asrock/h110m: add libgfxinit support
by Maxim Polyakov (Code Review) 29 Sep '20

29 Sep '20

Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39104 to look at the new patch set (#13). Change subject: [WIP] mb/asrock/h110m: add libgfxinit support ...................................................................... [WIP] mb/asrock/h110m: add libgfxinit support Add libgfxinit support for Asrock H110M-DVS-R2 [1]. - DVI (DDI2); - HDMI (DDI3); - VGA (eDP): PTN3356R1BS, ROM-based low-power DisplayPort to VGA adapter [2]; - EDP_TXN[2] -> EDP_VGA_TX0# - EDP_TXN[3] -> EDP_VGA_TX1# - EDP_TXP[2] -> EDP_VGA_TX0 - EDP_TXP[2] -> EDP_VGA_TX1 [1] https://www.2by2.be/images/photolib/604201.jpg [2] https://www.nxp.com/docs/en/data-sheet/PTN3356R1.pdf Change-Id: I4d87413f87d00986111ecb7b046423ff5eac1bf1 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/gma-mainboard.ads 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/39104/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/39104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d87413f87d00986111ecb7b046423ff5eac1bf1 Gerrit-Change-Number: 39104 Gerrit-PatchSet: 13 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [WIP] mb/asrock/h110m: add libgfxinit support
by Maxim Polyakov (Code Review) 29 Sep '20

29 Sep '20

Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39104 to look at the new patch set (#12). Change subject: [WIP] mb/asrock/h110m: add libgfxinit support ...................................................................... [WIP] mb/asrock/h110m: add libgfxinit support - DVI/HDMI port; - HDMI port; - VGA: PTN3356R1BS, ROM-based low-power DisplayPort to VGA adapter [1]; - EDP_TXN[2] -> EDP_VGA_TX0# - EDP_TXN[3] -> EDP_VGA_TX1# - EDP_TXP[2] -> EDP_VGA_TX0 - EDP_TXP[2] -> EDP_VGA_TX1 [1] https://www.nxp.com/docs/en/data-sheet/PTN3356R1.pdf Change-Id: I4d87413f87d00986111ecb7b046423ff5eac1bf1 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/gma-mainboard.ads 2 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/39104/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/39104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d87413f87d00986111ecb7b046423ff5eac1bf1 Gerrit-Change-Number: 39104 Gerrit-PatchSet: 12 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/xeon_sp: Improve performance efficiencies
by John Zhao (Code Review) 29 Sep '20

29 Sep '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45608 ) Change subject: soc/intel/xeon_sp: Improve performance efficiencies ...................................................................... soc/intel/xeon_sp: Improve performance efficiencies Coverity detects performance inefficiencies as IIO_RESOUCE_INSTANCE structure (size 623 bytes) is PASS_BY_VALUE. Fix it with PASS_BY_REFERENCE. Found-by: Coverity CID 1432759 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I9ae9ae38fe2c13c5433aa5e1dcbb30ebd30622ab --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45608/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index cd497c5..21ca119 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -605,16 +605,16 @@ * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, - int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, + int port, int stack, IIO_RESOURCE_INSTANCE *iio_resource, uint32_t pcie_seg, bool is_atsr, bool *first) { if (get_stack_for_port(port) != stack) return 0; - const uint32_t bus = iio_resource.StackRes[stack].BusBase; - const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; - const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; + const uint32_t bus = iio_resource->StackRes[stack].BusBase; + const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device; + const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function; const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); @@ -707,7 +707,7 @@ hob->PlatformData.IIO_resource[socket]; for (int p = PORT_0; p < MAX_PORTS; ++p) current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, - iio_resource, pcie_seg, false, NULL); + &iio_resource, pcie_seg, false, NULL); // Add VMD if (hob->PlatformData.VMDStackEnable[socket][stack] && @@ -771,7 +771,7 @@ if (socket == 0 && p == PORT_0) continue; current += acpi_create_dmar_ds_pci_br_for_port(current, p, - stack, iio_resource, pcie_seg, true, &first); + stack, &iio_resource, pcie_seg, true, &first); } } if (tmp != current) -- To view, visit https://review.coreboot.org/c/coreboot/+/45608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ae9ae38fe2c13c5433aa5e1dcbb30ebd30622ab Gerrit-Change-Number: 45608 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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