coreboot-gerrit September 2020

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Change in coreboot[master]: Revert "soc/intel/xeon_sp: Improve performance efficiencies"
by Subrata Banik (Code Review) 29 Sep '20

29 Sep '20

Hello build bot (Jenkins), Marc Jones, Patrick Georgi, Jonathan Zhang, John Zhao, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44998 to review the following change. Change subject: Revert "soc/intel/xeon_sp: Improve performance efficiencies" ...................................................................... Revert "soc/intel/xeon_sp: Improve performance efficiencies" This reverts commit d51449d017410fedb55e93f71fb322749ba888b5. Reason for revert: <https://qa.coreboot.org/job/coreboot/16544/> Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4 --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44998/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 1b6f1a3..cd497c5 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -605,16 +605,16 @@ * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, - int port, int stack, const IIO_RESOURCE_INSTANCE *iio_resource, uint32_t pcie_seg, + int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, bool is_atsr, bool *first) { if (get_stack_for_port(port) != stack) return 0; - const uint32_t bus = iio_resource->StackRes[stack].BusBase; - const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device; - const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function; + const uint32_t bus = iio_resource.StackRes[stack].BusBase; + const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; + const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); @@ -703,8 +703,8 @@ // Add PCIe Ports if (socket != 0 || stack != CSTACK) { - const IIO_RESOURCE_INSTANCE *iio_resource = - &hob->PlatformData.IIO_resource[socket]; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; for (int p = PORT_0; p < MAX_PORTS; ++p) current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, iio_resource, pcie_seg, false, NULL); @@ -748,12 +748,12 @@ uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; unsigned long tmp = current; bool first = true; - const IIO_RESOURCE_INSTANCE *iio_resource = - &hob->PlatformData.IIO_resource[socket]; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t bus = iio_resource->StackRes[stack].BusBase; - uint32_t vtd_base = iio_resource->StackRes[stack].VtdBarAddress; + uint32_t bus = iio_resource.StackRes[stack].BusBase; + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; if (!vtd_base) continue; uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); @@ -821,10 +821,10 @@ assert(hob != NULL && hob_size != 0); for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - IIO_RESOURCE_INSTANCE *iio_resource = - &hob->PlatformData.IIO_resource[socket]; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t vtd_base = iio_resource->StackRes[stack].VtdBarAddress; + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; if (!vtd_base) continue; -- To view, visit https://review.coreboot.org/c/coreboot/+/44998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4 Gerrit-Change-Number: 44998 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/smbios: Add SMBIOS Thread Count
by Francois Toguo Fotso (Code Review) 29 Sep '20

29 Sep '20

Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45564 ) Change subject: arch/x86/smbios: Add SMBIOS Thread Count ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/45564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e00ba706eecdc850a2c6a4d876a7732dcc8f755 Gerrit-Change-Number: 45564 Gerrit-PatchSet: 5 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Sep 2020 18:48:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 29 Sep '20

29 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries ...................................................................... Patch Set 5: > Patch Set 1: Code-Review+1 > > looking fwd to get this CL in. Thanks for picking this Can you check this again, please? -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Sep 2020 15:47:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/intelp2m/apl: Remove unused plat-spec function
by Maxim Polyakov (Code Review) 29 Sep '20

29 Sep '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44473 ) Change subject: util/intelp2m/apl: Remove unused plat-spec function ...................................................................... util/intelp2m/apl: Remove unused plat-spec function Change-Id: I42074387a08b66b038ad2939f31be263eaa3af0e Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/platforms/apl/macro.go 1 file changed, 0 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44473/1 diff --git a/util/intelp2m/platforms/apl/macro.go b/util/intelp2m/platforms/apl/macro.go index 4288fa4..0364067 100644 --- a/util/intelp2m/platforms/apl/macro.go +++ b/util/intelp2m/platforms/apl/macro.go @@ -37,32 +37,6 @@ // remmap is not required because it is the same as common. func (PlatformSpecific) RemmapRstSrc() {} -// Adds the PADRSTCFG parameter from DW0 to the macro as a new argument -// return: macro -func (PlatformSpecific) Rstsrc() { - macro := common.GetMacro() - dw0 := macro.Register(PAD_CFG_DW0) - // See src/soc/intel/apollolake/gpio_apl.c: - // static const struct reset_mapping rst_map[] = { - // { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, - // { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, - // { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, - // }; - - var resetsrc = map[uint8]string{ - 0: "PWROK", - 1: "DEEP", - 2: "PLTRST", - } - str, valid := resetsrc[dw0.GetResetConfig()] - if !valid { - // 3h = Reserved (implement as setting 0h) - dw0.CntrMaskFieldsClear(common.PadRstCfgMask) - str = "PWROK" - } - macro.Separator().Add(str) -} - // Adds The Pad Termination (TERM) parameter from DW1 to the macro as a new argument // return: macro func (PlatformSpecific) Pull() { -- To view, visit https://review.coreboot.org/c/coreboot/+/44473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42074387a08b66b038ad2939f31be263eaa3af0e Gerrit-Change-Number: 44473 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/fizz/endeavour/gpio: Fix code style
by Maxim Polyakov (Code Review) 29 Sep '20

29 Sep '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44468 ) Change subject: mb/google/fizz/endeavour/gpio: Fix code style ...................................................................... mb/google/fizz/endeavour/gpio: Fix code style Use the 96 character limit. Change-Id: I865288051869e50602a579a6999b1b23ef68ec2f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/google/fizz/variants/endeavour/gpio.c 1 file changed, 30 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/44468/1 diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index 716be3f..13f3b26 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -14,15 +14,13 @@ /* ESPI_IO3 */ /* ESPI_CS# */ /* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, - EDGE), /* SD_CDZ */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, EDGE), /* SD_CDZ */ /* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ /* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ /* BM_BUSY# */ PAD_CFG_NC(GPP_A12), -/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, - DEEP), /* eSPI mode */ +/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ /* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), @@ -39,30 +37,20 @@ /* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ /* CPU_GP2 */ PAD_CFG_NC(GPP_B3), /* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, - NF1), /* CLK_PCIE_LAN_REQ# */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, - NF1), /* PCIE_CLKREQ_SSD# */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, - NF1), /* PCIE_CLKREQ_TPU# */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, - NF1), /* PCIE_CLKREQ_POE# */ -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, - NF1), /* PCIE_CLKREQ_TPU1# */ -/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, - NF1), /* PCIE_CLKREQ_WLAN# */ +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU# */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* PCIE_CLKREQ_POE# */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU1# */ +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ -/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_CS_L */ -/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_CLK */ -/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_MISO */ -/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_MOSI */ +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ /* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP98 */ /* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), /* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), @@ -75,21 +63,16 @@ /* SML0CLK */ PAD_CFG_NC(GPP_C3), /* SML0DATA */ PAD_CFG_NC(GPP_C4), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, - DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP99 */ /* UART0_RXD */ PAD_CFG_NC(GPP_C8), /* UART0_TXD */ PAD_CFG_NC(GPP_C9), /* UART0_RTS# */ PAD_CFG_NC(GPP_C10), /* UART0_CTS# */ PAD_CFG_NC(GPP_C11), -/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, - DEEP), /* SKU_ID0 */ -/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, - DEEP), /* SKU_ID1 */ -/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, - DEEP), /* SKU_ID2 */ -/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, - DEEP), /* SKU_ID3 */ +/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ +/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* SKU_ID1 */ +/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* SKU_ID2 */ +/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TPU_SDA */ /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* PCH_I2C_TPU_SCL */ /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */ @@ -97,8 +80,7 @@ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP93 */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, - DEEP), /* SCREW_SPI_WP_STATUS */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ /* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP106 */ /* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP102 */ @@ -109,14 +91,10 @@ /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), /* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), /* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, - PLTRST, EDGE), /* HP_IRQ_GPIO */ -/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, - DEEP), /* OEM_ID1 */ -/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, - DEEP), /* OEM_ID2 */ -/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, - DEEP), /* OEM_ID3 */ +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), /* HP_IRQ_GPIO */ +/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ +/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ +/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ /* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), /* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), /* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), @@ -129,10 +107,8 @@ /* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP94 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, - NF1), /* MB_PCIE_SATA#_DET */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* TPU_RST_PIN40 */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ @@ -142,14 +118,10 @@ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */ /* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */ -/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, - NF1), /* Rear Dual-Stack USB Ports */ -/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, - NF1), /* Rear Single USB Port */ -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, - NF1), /* DDI1_HDMI_HPD */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, - NF1), /* DDI2_HDMI_HPD */ +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* Rear Single USB Port */ +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI1_HDMI_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HDMI_HPD */ /* DDPD_HPD2 */ PAD_CFG_GPI_APIC(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */ /* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP1021 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), @@ -170,10 +142,8 @@ /* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */ /* I2C4_SDA */ PAD_CFG_NC(GPP_F8), /* I2C4_SCL */ PAD_CFG_NC(GPP_F9), -/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, - NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ -/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, - NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ +/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ +/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ /* EMMC_CMD */ PAD_CFG_NC(GPP_F12), /* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), /* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -- To view, visit https://review.coreboot.org/c/coreboot/+/44468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I865288051869e50602a579a6999b1b23ef68ec2f Gerrit-Change-Number: 44468 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: Intel GBE 82579LM bincfg set and spec
by Tom Hiller (Code Review) 28 Sep '20

28 Sep '20

Tom Hiller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44510 ) Change subject: Intel GBE 82579LM bincfg set and spec ...................................................................... Intel GBE 82579LM bincfg set and spec Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963 Signed-off-by: Tom Hiller <thrilleratplay(a)gmail.com> --- M util/bincfg/Makefile A util/bincfg/gbe-82579LM.set A util/bincfg/gbe-82579LM.spec 3 files changed, 451 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44510/1 diff --git a/util/bincfg/Makefile b/util/bincfg/Makefile index 1b3e936..b35cd3e 100644 --- a/util/bincfg/Makefile +++ b/util/bincfg/Makefile @@ -19,6 +19,13 @@ cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin rm -f gbe1.bin +# Use this target to generate GbE for X200 +gen-gbe-82579LM: + ./bincfg gbe-82579LM.spec gbe-82579LM.set gbe1.bin + # duplicate binary as per spec + cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin + rm -f gbe1.bin + # Use this target to generate IFD for X200 gen-ifd-x200: ./bincfg ifd-x200.spec ifd-x200.set flashregion_0_fd.bin diff --git a/util/bincfg/gbe-82579LM.set b/util/bincfg/gbe-82579LM.set new file mode 100644 index 0000000..01ae470 --- /dev/null +++ b/util/bincfg/gbe-82579LM.set @@ -0,0 +1,288 @@ +# SPDX-License-Identifier: GPL-3.0-or-later + +# +# Datasheets: +# +# https://cdrdv2.intel.com/v1/dl/getContent/613456 + +# The datasheet says that this spec covers the following pci ids: +# 8086:1502 - Intel 82579LM gigabit ethernet controller +# 8086:1503 - Intel 82579V gigabit ethernet controller + +# Naming convention +# * Word groups separated by a blank line +# * Word groups with known meaning given a prefix +# * prefix will be defined in comment before group +# * Variable names to be named using a prefix, descriptive name and bit offset +# within the word, separated by an underscore. +# * Example: "prefix_description_0" +# * Unidentified reserved word groups will be named reserved and LAN Word +# * EXCEPTION: Word 0x24, Word 0x25, Word 0x26 also include bit offset +# within the word +# Offset hex address, separated by an underscore. +# * Example: "reserved_x03" +# * Nonprefixed names will be named reserved and LAN Word Offset hex address, +# separated by an underscore. +# * Example: "imageversioninfo_x05" +# * Unspecified words are prefixed with "offset_" + +# GbE values for 82579LM +{ + # This example sets MAC address to 00:DE:AD:C0:FF:EE + # USE YOUR DEVICES MAC ADDRESS!! + # prefix: "mac_" + "mac_address_0" = 0x00, + "mac_address_1" = 0xDE, + "mac_address_2" = 0xAD, + "mac_address_3" = 0xC0, + "mac_address_4" = 0xFF, + "mac_address_5" = 0xEE, + + # Reserved (Word 0x3) + "reserved_x03" = 0x0800, + + # Reserved (Word 0x04) + "reserved_x04" = 0xffff, + + # Image Version Information (Word 0x05) + "imageversioninfo_x05" = 0x00D3, + + "reserved_x06" = 0xffff, + "reserved_x07" = 0xffff, + + # PBA Low and PBA High (Words 0x08 and 0x09) + # prefix: "pba_" + "pba_low_x08" = 0xffff, + "pba_high_x09" = 0xffff, + + # PCI Init Control Word (Word 0x0A) + # prefix: "pci_" + "pci_loaddeviceid_0" = 1, + "pci_loadsubsystemid_1" = 1, + "pci_reserved_2" = 0, + "pci_reserved_3" = 0x0, + "pci_pmenable_6" = 1, + "pci_auxpwr_7" = 1, + "pci_reserved_8" = 0x10, + + # ************* Configurable PCI IDs **************** + # TODO: make command line switch for these + # Subsystem ID (Word 0x0B) + "subsystemid_x0B" = 0, + # Subsystem Vendor ID (Word 0x0C) + "subsystemvendorid_x0C" = 0x8086, + # Device ID (Word 0x0D) + # TODO: 82579V uses "deviceid_x0D" = 0x1503, + "deviceid_x0D" = 0x1502, + # ************* END Configurable PCI IDs **************** + + # Words 0x0E and 0x0F Are Reserved + "reserved_x0E" = 0x0, + "reserved_x0F" = 0x0, + + # LAN Power Consumption (Word 0x10) + # prefix: "lanpwr_" + "lanpwr_d3pwr_0" = 0x2, + "lanpwr_reserved_5" = 0, + "lanpwr_d0pwr_8" = 0x7, + + # Word 0x12 and Word 0x11 Are Reserved + "reserved_x11" = 0x0000, + "reserved_x12" = 0x0000, + + # Shared Init Control Word (Word 0x13) + # prefix: "sicw_" + "sicw_dynamicclock_0" = 1, + "sicw_clkcnt_1" = 0, + "sicw_reserved_2" = 1, + "sicw_fullduplex_3" = 0, + "sicw_forcespeed_4" = 0, + "sicw_reserved_5" = 0, + "sicw_phydeviceype_6" = 0, + "sicw_reserved_8" = 1, + "sicw_phy_enpwrdown_9" = 0, + "sicw_reserved_10" = 1, + "sicw_macsecdisable_13" = 1, + "sicw_sign_14" = 0x2, + + # Extended Configuration Word 1 (Word 0x14) + # prefix: "ecw1_" + "ecw1_extcfgptr_0" = 0x0028, + "ecw1_oemload_12" = 1, + "ecw1_phyload_13" = 1, + "ecw1_reserved_14" = 0, + + # Extended Configuration Word 2 (Word 0x15) + # prefix: "ecw2_" + "ecw2_reserved_0" = 0x00, + "ecw2_extphylen_8" = 0x12, + + # Extended Configuration Word 3 (Word 0x16) + # prefix: "ecw3_" + "ecw3_extcfg1_0" = 0x00, + + # OEM Configuration Defaults (Word 0x17) + # prefix: "oem_" + "oem_reserved_0" = 0x000, + "oem_lpluenind0a_9" = 0, + "oem_lplueninnond0a_10" = 1, + "oem_gbedisinnond0a_11" = 1, + "oem_reserved_12" = 0, + "oem_gbedis_14" = 0, + "oem_reserved_15" = 0, + + # LED 0 - 2 Configuration Defaults (Word 0x18) + # prefix: "l02_" + # Lenovo default values + "l02_led0mode_0" = 0x4, + "l02_led0invert_3" = 0, + "l02_led0blink_4" = 0, + "l02_led1mode_5" = 0x3, + "l02_led1invert_8" = 0, + "l02_led1blink_9" = 1, + "l02_led2mode_10" = 0x2, + "l02_led2invert_13" = 1, + "l02_led2blink_14" = 0, + "l02_blinkrate_15" = 0, + + # Intel default Values + #"l02_led0mode_0" = 0x4, + #"l02_led0invert_3" = 0, + #"l02_led0blink_4" = 1, + #"l02_led1mode_5" = 0x7, + #"l02_led1invert_8" = 0, + #"l02_led1blink_9" = 0, + #"l02_led2mode_10" = 0x6, + #"l02_led2invert_13" = 0, + #"l02_led2blink_14" = 0, + #"l02_blinkrate_15" = 0, + + + # Reserved (Word 0x19) + # NOTE: bit 6 must be 1 for validation. See datasheet. + "reserved_x19" = 0x2B40, + + # Reserved (Word 0x1A) + # Advanced Power Management Wake Up Enable + # prefix: "amp_" + "amp_enable_0" = 1, + "amp_reserved_1" = 0x0421, + + # Reserved (Word 0x1B) + "reserved_x1B" = 0x0113, + + # Reserved (Word 0x1C) + "reserved_x1C" = 0x1502, + + # Reserved (Word 0x1D) + "reserved_x1D" = 0xBAAD, + + # Reserved (Word 0x1E) + "reserved_x1E" = 0x1502, + + # Reserved (Word 0x1F) + "reserved_x1F" = 0x1503, + + # Reserved (Word 0x20) + "reserved_x20" = 0xBAAD, + + # Reserved (Word 0x21) + "reserved_x21" = 0xBAAD, + + # Reserved (Word 0x22) + "reserved_x22" = 0xBAAD, + + # Reserved (Word 0x23) + "reserved_x23" = 0x1502, + + # Reserved (Word 0x24) + "reserved_x24_0" = 0x0000, + "reserved_x24_14" = 0, + "reserved_x24_15" = 1, + + # Reserved (Word 0x25) + "reserved_x25_0" = 0x0000, + "reserved_x25_4" = 1, + "reserved_x25_5" = 0, + "reserved_x25_7" = 1, + "reserved_x25_8" = 0x00, + "reserved_x25_15" = 1, + + # Reserved (Word 0x26) + "reserved_x26_0" = 0x00, + "reserved_x26_9" = 1, + "reserved_x26_10" = 1, + "reserved_x26_11" = 1, + "reserved_x26_12" = 0, + "reserved_x26_14" = 1, + "reserved_x26_15" = 0, + + # Reserved (Word 0x27) + "reserved_x27" = 0x80, + + # Offsets 0x28-0x2F + "offset_x28" = 0x0000, + "offset_x29" = 0x0000, + "offset_x2A" = 0x0000, + "offset_x2B" = 0x0000, + "offset_x2C" = 0x0000, + "offset_x2D" = 0x0000, + "offset_x2E" = 0x0000, + "offset_x2F" = 0x0000, + + # Boot Agent Main Setup Options (Word 0x30) + # Hardcoded PXE setup (disabled) + # prefix: "pxe30_" + "pxe30_protocolsel_0" = 0, + "pxe30_reserved_2" = 0, + "pxe30_defbootsel_3" = 0x3, + "pxe30_reserved_5" = 0, + "pxe30_prompttime_6" = 0x3, + "pxe30_dispsetup_8" = 0, + "pxe30_reserved_9" = 0, + "pxe30_forcespeed_10" = 0, + "pxe30_forcefullduplex_12" = 0, + "pxe30_reserved_13" = 0, + "pxe30_reserved_14" = 0, + + # Boot Agent Configuration Customization Options (Word 0x31) + # prefix: "pxe31_" + "pxe31_disablemenu_0" = 1, + "pxe31_disabletitle_1" = 1, + "pxe31_disableprotsel_2" = 0, + "pxe31_disbootorder_3" = 0, + "pxe31_dislegacywak_4" = 0, + "pxe31_disableflasicwpro_5" = 0, + "pxe31_reserved_6" = 0, + "pxe31_ibootagentmode_8" = 0, + "pxe31_contretrydis_11" = 0, + "pxe31_reserved_12" = 0, + "pxe31_signature_14" = 10, + + # Boot Agent Configuration Customization Options (Word 0x32) + # prefix: "pxe32_" + "pxe32_buildnum_0" = 0x28, + "pxe32_minorversion_8" = 0x2, + "pxe32_majorversion_12" = 0x1, + + # IBA Capabilities (Word 0x33) + # prefix: "pxe33_" + "pxe33_basecodepresent_0" = 1, + "pxe33_undipresent_1" = 1, + "pxe33_reserved_2" = 1, + "pxe33_efiundipresent_3" = 0, + "pxe33_iscsi_4" = 0, + "pxe33_reserved_5" = 0, + "pxe33_signature_14" = 10, + + "pxe_padding"[11] = 0xffff, + + # Checksum is generated by bincfg + # "checksum_gbe" = xxx, + + # G3 -> S5 PHY Configuration + "g3_s5_phy_conf"[0x16] = 0, + + # Padding 0xf80 bytes + "padding"[0xf6a] = 0xff +} diff --git a/util/bincfg/gbe-82579LM.spec b/util/bincfg/gbe-82579LM.spec new file mode 100644 index 0000000..778d580 --- /dev/null +++ b/util/bincfg/gbe-82579LM.spec @@ -0,0 +1,156 @@ +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# +# Datasheets: +# +# https://cdrdv2.intel.com/v1/dl/getContent/613456 + +# The datasheet says that this spec covers the following pci ids: +# 8086:1502 - Intel 82579LM gigabit ethernet controller +# 8086:1503 - Intel 82579V gigabit ethernet controller + +# GbE SPEC for 82579LM/82579V +{ + "mac_address_"[6] : 8, + "reserved_x03" : 16, + "reserved_x04" : 16, + "imageversioninfo_x05" : 16, + "reserved_x06" : 16, + "reserved_x07" : 16, + "pba_low_x08" : 16, + "pba_high_x09" : 16, + "pci_loaddeviceid_0" : 1, + "pci_loadsubsystemid_1" : 1, + "pci_reserved_2" : 1, + "pci_reserved_3" : 3, + "pci_pmenable_6" : 1, + "pci_auxpwr_7" : 1, + "pci_reserved_8" : 8, + "subsystemid_x0B" : 16, + "subsystemvendorid_x0C" : 16, + "deviceid_x0D" : 16, + "reserved_x0E" : 16, + "reserved_x0F" : 16, + "lanpwr_d3pwr_0" : 5, + "lanpwr_reserved_5" : 3, + "lanpwr_d0pwr_8" : 8, + "reserved_x11" : 16, + "reserved_x12" : 16, + "sicw_dynamicclock_0" : 1, + "sicw_clkcnt_1" : 1, + "sicw_reserved_2" : 1, + "sicw_fullduplex_3" : 1, + "sicw_forcespeed_4" : 1, + "sicw_reserved_5" : 1, + "sicw_phydeviceype_6" : 2, + "sicw_reserved_8" : 1, + "sicw_phy_enpwrdown_9" : 1, + "sicw_reserved_10" : 3, + "sicw_macsecdisable_13" : 1, + "sicw_sign_14" : 2, + "ecw1_extcfgptr_0" : 12, + "ecw1_oemload_12" : 1, + "ecw1_phyload_13" : 1, + "ecw1_reserved_14" : 2, + "ecw2_reserved_0" : 8, + "ecw2_extphylen_8" : 8, + "ecw3_extcfg1_0" : 16, + "oem_reserved_0" : 9, + "oem_lpluenind0a_9" : 1, + "oem_lplueninnond0a_10" : 1, + "oem_gbedisinnond0a_11" : 1, + "oem_reserved_12" : 2, + "oem_gbedis_14" : 1, + "oem_reserved_15" : 1, + "l02_led0mode_0" : 3, + "l02_led0invert_3" : 1, + "l02_led0blink_4" : 1, + "l02_led1mode_5" : 3, + "l02_led1invert_8" : 1, + "l02_led1blink_9" : 1, + "l02_led2mode_10" : 3, + "l02_led2invert_13" : 1, + "l02_led2blink_14" : 1, + "l02_blinkrate_15" : 1, + "reserved_x19" : 16, + "amp_enable_0" : 1, + "amp_reserved_1" : 15, + "reserved_x1B" : 16, + "reserved_x1C" : 16, + "reserved_x1D" : 16, + "reserved_x1E" : 16, + "reserved_x1F" : 16, + "reserved_x20" : 16, + "reserved_x21" : 16, + "reserved_x22" : 16, + "reserved_x23" : 16, + "reserved_x24_0" : 14, + "reserved_x24_14" : 1, + "reserved_x24_15" : 1, + "reserved_x25_0" : 4, + "reserved_x25_4" : 1, + "reserved_x25_5" : 2, + "reserved_x25_7" : 1, + "reserved_x25_8" : 7, + "reserved_x25_15" : 1, + "reserved_x26_0" : 9, + "reserved_x26_9" : 1, + "reserved_x26_10" : 1, + "reserved_x26_11" : 1, + "reserved_x26_12" : 2, + "reserved_x26_14" : 1, + "reserved_x26_15" : 1, + "reserved_x27" : 16, + "offset_x28" : 16, + "offset_x29" : 16, + "offset_x2A" : 16, + "offset_x2B" : 16, + "offset_x2C" : 16, + "offset_x2D" : 16, + "offset_x2E" : 16, + "offset_x2F" : 16, + "pxe30_protocolsel_0" : 2, + "pxe30_reserved_2" : 1, + "pxe30_defbootsel_3" : 2, + "pxe30_reserved_5" : 1, + "pxe30_prompttime_6" : 2, + "pxe30_dispsetup_8" : 1, + "pxe30_reserved_9" : 1, + "pxe30_forcespeed_10" : 2, + "pxe30_forcefullduplex_12" : 1, + "pxe30_reserved_13" : 1, + "pxe30_reserved_14" : 2, + "pxe31_disablemenu_0" : 1, + "pxe31_disabletitle_1" : 1, + "pxe31_disableprotsel_2" : 1, + "pxe31_disbootorder_3" : 1, + "pxe31_dislegacywak_4" : 1, + "pxe31_disableflasicwpro_5" : 1, + "pxe31_reserved_6" : 2, + "pxe31_ibootagentmode_8" : 3, + "pxe31_contretrydis_11" : 1, + "pxe31_reserved_12" : 2, + "pxe31_signature_14" : 2, + "pxe32_buildnum_0" : 8, + "pxe32_minorversion_8" : 4, + "pxe32_majorversion_12" : 4, + "pxe33_basecodepresent_0" : 1, + "pxe33_undipresent_1" : 1, + "pxe33_reserved_2" : 1, + "pxe33_efiundipresent_3" : 1, + "pxe33_iscsi_4" : 1, + "pxe33_reserved_5" : 9, + "pxe33_signature_14" : 2, + "pxe_padding"[11] : 16, + "checksum_gbe" : 16, + "g3_s5_phy_conf"[0x16] : 8, + "padding"[0xf6a] : 8 +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963 Gerrit-Change-Number: 44510 Gerrit-PatchSet: 1 Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-MessageType: newchange

3 17

Change in coreboot[master]: util/intelp2m: Remove unnecessary tabs
by Maxim Polyakov (Code Review) 28 Sep '20

28 Sep '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44474 ) Change subject: util/intelp2m: Remove unnecessary tabs ...................................................................... util/intelp2m: Remove unnecessary tabs Change-Id: I5aa4b9ac4fa1ceb6f3c2ade214d47b29246ece55 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/parser/template.go 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/44474/1 diff --git a/util/intelp2m/parser/template.go b/util/intelp2m/parser/template.go index bc7d702..3248152 100644 --- a/util/intelp2m/parser/template.go +++ b/util/intelp2m/parser/template.go @@ -123,10 +123,10 @@ // 0x0088: 0x00ffffff (HOSTSW_OWN_GPP_F) // 0x0100: 0x00000000 (GPI_IS_GPP_A) if fields := strings.FieldsFunc(line, tokenCheck); len(fields) == 3 { - *name = fields[2] - fmt.Sscanf(fields[1], "0x%x", value) - fmt.Sscanf(fields[0], "0x%x", offset) - return 0 + *name = fields[2] + fmt.Sscanf(fields[1], "0x%x", value) + fmt.Sscanf(fields[0], "0x%x", offset) + return 0 } return -1 } -- To view, visit https://review.coreboot.org/c/coreboot/+/44474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5aa4b9ac4fa1ceb6f3c2ade214d47b29246ece55 Gerrit-Change-Number: 44474 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: mb/google/octopus/variants/fleex: Only do LTE power off for LTE sku
by EricR Lai (Code Review) 28 Sep '20

28 Sep '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45687 ) Change subject: mb/google/octopus/variants/fleex: Only do LTE power off for LTE sku ...................................................................... mb/google/octopus/variants/fleex: Only do LTE power off for LTE sku Only do LTE power off for LTE sku in order to save extra 130ms delay for power off. BUG=b:168075958 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: If983185ff2f09fb1b2553c6ff1a1473d3254de4b --- M src/mainboard/google/octopus/variants/fleex/variant.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45687/1 diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c index 1b0784c..92e6c4c 100644 --- a/src/mainboard/google/octopus/variants/fleex/variant.c +++ b/src/mainboard/google/octopus/variants/fleex/variant.c @@ -2,27 +2,29 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> -#include <delay.h> #include <ec/google/chromeec/ec.h> -#include <gpio.h> #include <sar.h> +static bool is_lte_sku() +{ + return (google_chromeec_get_board_sku() == 4); +} + void variant_smi_sleep(u8 slp_typ) { /* Currently use cases here all target to S5 therefore we do early return * here for saving one transaction to the EC for getting SKU ID. */ if (slp_typ != ACPI_S5) return; - - power_off_lte_module(); + if (is_lte_sku()) + power_off_lte_module(); } const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = google_chromeec_get_board_sku(); - if (sku_id != 4) + if (!is_lte_sku()) filename = "wifi_sar-fleex.hex"; return filename; -- To view, visit https://review.coreboot.org/c/coreboot/+/45687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If983185ff2f09fb1b2553c6ff1a1473d3254de4b Gerrit-Change-Number: 45687 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/clevo/cml-u/Kconfig: Remove MAINBOARD_SMBIOS_PRODUCT_NAME
by HAOUAS Elyes (Code Review) 28 Sep '20

28 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45758 ) Change subject: mb/clevo/cml-u/Kconfig: Remove MAINBOARD_SMBIOS_PRODUCT_NAME ...................................................................... mb/clevo/cml-u/Kconfig: Remove MAINBOARD_SMBIOS_PRODUCT_NAME MAINBOARD_SMBIOS_PRODUCT_NAME is duplicated. Change-Id: I011f83c4d4e0657256839db207bfd1517922744c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/clevo/cml-u/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45758/1 diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index bc75df9..ae79794 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -29,10 +29,6 @@ string default "L140CU" if BOARD_CLEVO_L140CU -config MAINBOARD_SMBIOS_PRODUCT_NAME - string - default "L140CU" if BOARD_CLEVO_L140CU - config MAINBOARD_VERSION string default "2.1A" if BOARD_CLEVO_L140CU -- To view, visit https://review.coreboot.org/c/coreboot/+/45758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011f83c4d4e0657256839db207bfd1517922744c Gerrit-Change-Number: 45758 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/amd/picasso: Set eMMC preset UPDs
by Raul Rangel (Code Review) 28 Sep '20

28 Sep '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45661 ) Change subject: soc/amd/picasso: Set eMMC preset UPDs ...................................................................... soc/amd/picasso: Set eMMC preset UPDs Now that all boards have bootable driver strengths and init frequency, we can pass them to FSP. BUG=b:159823235 TEST=Boot ezkinil to kernel and print presets. SDHC0x8F0 Initialization 3.3V or 1.8V => 0x03ff 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x3ff: SdClkFreq SDHC0x8F2 Default Speed 3.3V => 0x0004 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x4: SdClkFreq SDHC0x8F4 High Speed 3.3V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x8F6 SDR12 1.8V => 0x0008 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x8: SdClkFreq SDHC0x8F8 SDR25 1.8V => 0x0004 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x4: SdClkFreq SDHC0x8FA SDR50 1.8V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x8FC SDR104 1.8V => 0x4000 14 => 0x1 [A]: DvrStrength 10 => 0: ClkGen 00 => 0: SdClkFreq SDHC0x8FE DDR50 1.8V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x900 HS400 => 0x4000 14 => 0x1 [A]: DvrStrength 10 => 0: ClkGen 00 => 0: SdClkFreq Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5fe5c0a5a5ecf292ce8703e9c9ea80b6f1b6440e --- M src/soc/amd/picasso/fsp_params.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/45661/1 diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index b21f237..95e691d 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -55,6 +55,11 @@ } scfg->emmc0_mode = val; + scfg->emmc0_sdr104_hs400_driver_strength = + cfg->emmc_config.sdr104_hs400_driver_strength; + scfg->emmc0_ddr50_driver_strength = cfg->emmc_config.ddr50_driver_strength; + scfg->emmc0_sdr50_driver_strength = cfg->emmc_config.sdr50_driver_strength; + scfg->emmc0_init_khz_preset = cfg->emmc_config.init_khz_preset; } static void fill_dxio_descriptors(FSP_S_CONFIG *scfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/45661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fe5c0a5a5ecf292ce8703e9c9ea80b6f1b6440e Gerrit-Change-Number: 45661 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020