Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45098 )
Change subject: mb/google/zork: Set eMMC drive strength preset to A
......................................................................
mb/google/zork: Set eMMC drive strength preset to A
This change has no effect on depthcharge or the kernel. They don't
currently look at the preset values.
BUG=b:159823235
TEST=Boot Ezkinil and dump SDHCI preset registers. Verified they are all
set to A.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906
---
M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45098/1
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index 4edbfa4..0c3276b 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -42,6 +42,7 @@
register "emmc_config" = "{
.timing = SD_EMMC_EMMC_HS400,
+ .preset_drive_strength = SD_EMMC_DRIVE_STRENGTH_A,
}"
register "xhci0_force_gen1" = "0"
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 05bee6b..d78c432 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -42,6 +42,7 @@
register "emmc_config" = "{
.timing = SD_EMMC_EMMC_HS400,
+ .preset_drive_strength = SD_EMMC_DRIVE_STRENGTH_A,
}"
register "xhci0_force_gen1" = "0"
--
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Gerrit-Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906
Gerrit-Change-Number: 45098
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Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
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Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45097 )
Change subject: soc/amd/picasso: Add emmc_config->preset_drive_strength
......................................................................
soc/amd/picasso: Add emmc_config->preset_drive_strength
This change allows passing in the preset drive strength to FSP.
BUG=b:159823235
TEST=Made sure presets are unchanged.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45097/1
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index efac418..c70de65 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -153,6 +153,24 @@
SD_EMMC_EMMC_HS400,
SD_EMMC_EMMC_HS300,
} timing;
+
+ /*
+ * Sets the drive strength reflected in the UHS-I SDHCI Preset Value
+ * Registers. The drive strength is also set in the undocumented EMMCCFG
+ * HS400 preset register. It is not possible to read this value from the
+ * SDHCI Preset Value Registers.
+ *
+ * According to the SDHCI spec:
+ * The host should select the weakest drive strength that meets rise /
+ * fall time requirement at system operating frequency.
+ */
+ enum {
+ SD_EMMC_DRIVE_STRENGTH_DEFAULT,
+ SD_EMMC_DRIVE_STRENGTH_B,
+ SD_EMMC_DRIVE_STRENGTH_A,
+ SD_EMMC_DRIVE_STRENGTH_C,
+ SD_EMMC_DRIVE_STRENGTH_D,
+ } preset_drive_strength;
} emmc_config;
uint8_t xhci0_force_gen1;
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 1e4f2a5..c7c3657 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -54,6 +54,8 @@
}
scfg->emmc0_mode = val;
+
+ scfg->emmc0_drive_strength = cfg->emmc_config.preset_drive_strength;
}
static void fill_dxio_descriptors(FSP_S_CONFIG *scfg,
--
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Gerrit-Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4
Gerrit-Change-Number: 45097
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Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
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Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45591 )
Change subject: soc/intel/xeon_sp/cpx: add ACPI name for CSTACK
......................................................................
soc/intel/xeon_sp/cpx: add ACPI name for CSTACK
Add ACPI name for CSTACK. The name is PC00 to match with ACPI table
generated.
The PCIe domain has multiple PCIe stacks. devicetree.cb at the moment
does not support multiple PCIe stacks, eg. IIO stacks. For now, assign
the name to PCIe domain. In future, the name needs to be assigned to
CSTACK.
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
Change-Id: I24a6f29734452426218419cdcf66702edde96f46
---
M src/soc/intel/xeon_sp/cpx/chip.c
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/45591/1
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 2c445f9..5ee7f6c 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -492,11 +492,23 @@
/* not implemented yet */
}
+#if CONFIG(HAVE_ACPI_TABLES)
+static const char *soc_acpi_name(const struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return "PC00";
+ return NULL;
+}
+#endif
+
static struct device_operations pci_domain_ops = {
.read_resources = &pci_domain_read_resources,
.set_resources = &xeonsp_cpx_pci_domain_set_resources,
.scan_bus = &xeonsp_cpx_pci_domain_scan_bus,
+#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = &northbridge_write_acpi_tables,
+ .acpi_name = soc_acpi_name
+#endif
};
static struct device_operations cpu_bus_ops = {
--
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Gerrit-Change-Id: I24a6f29734452426218419cdcf66702edde96f46
Gerrit-Change-Number: 45591
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Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45707 )
Change subject: doc/mb/ocp: update deltalake server documentation
......................................................................
doc/mb/ocp: update deltalake server documentation
Upon completion of 2nd build/test/release cycle of Deltalake server
alternative firmware engineering, update the document.
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
Change-Id: I1806526bd477ed407bb7fd36c7fe4ce0e57b72f0
---
M Documentation/mainboard/ocp/deltalake.md
1 file changed, 13 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/45707/1
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md
index 0bc5735..a9d44d7 100644
--- a/Documentation/mainboard/ocp/deltalake.md
+++ b/Documentation/mainboard/ocp/deltalake.md
@@ -14,8 +14,9 @@
Yosemite-V3 has multiple configurations. Depending on configurations, it may
host up to 4 Delta Lake servers in one sled.
-Yosemite-V3 and Delta Lake are currently in DVT phase. Facebook, Intel and partners
-jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative solution.
+The Yosemite-V3 program has reached DVT exit. Facebook, Intel and partners
+jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative
+solution. This development is moving toward EVT exit equivalent status.
## Required blobs
@@ -60,7 +61,6 @@
- Type 8 -- Port Connector Information
- Type 9 -- PCI Slot Information
- Type 11 -- OEM String
- - Type 13 -- BIOS Language Information
- Type 32 -- System Boot Information
- Type 38 -- IPMI Device Information
- Type 127 -- End-of-Table
@@ -87,12 +87,19 @@
- Power button
- localboot
- netboot from IPv6
+- TPM
## Stress/performance tests passed
-- OS warm reboot overnight (6 hours)
+- OS warm reboot (300 cycles)
+- DC reboot (300 cycles)
+- AC reboot (300 cycle)
- Mprime test (6 hours)
+- StressAppTest (6 hours)
+- Ptugen (6 hours)
- MLC (Intel Memory Latency Check)
- Linkpack
+- Iperf(IPv6)
+- FIO
## Firmware configurations
[ChromeOS VPD] is used to store most of the firmware configurations.
@@ -105,8 +112,6 @@
- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h.
## Known issues
-- ME based power capping. This is a bug in ME. An IPS ticket is filed
- with Intel.
- HECI is not set up correctly, so BMC is not able to get PCH and DIMM
temperature sensor readings. An IPS ticket is filed.
@@ -116,8 +121,8 @@
- Type 17 -- Memory Device
- Type 19 -- Memory Array Mapped Address
- Type 41 -- Onboard Devices Extended Information
-- Hardware error injection, detection, reporting
-- PFR/CBnT
+- Verified measurement through CBnT
+- Boot guard of CBnT
- RO_VPD region as well as other RO regions are not write protected.
## Technology
--
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45702 )
Change subject: include/cpu/x86/tsc: Fix rdtsc on x86_64
......................................................................
include/cpu/x86/tsc: Fix rdtsc on x86_64
The used assembler code only work on x86_32.
Use the inline function to provide valid rdtsc readings on both
x86_32 and x86_64.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: Icf706d6fb751372651e5e56d1856ddad688d9fa3
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/include/cpu/x86/tsc.h
1 file changed, 2 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45702/1
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 6943b93..87a8761 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -43,13 +43,8 @@
static inline unsigned long long rdtscll(void)
{
- unsigned long long val;
- asm volatile (
- TSC_SYNC
- "rdtsc"
- : "=A" (val)
- );
- return val;
+ const tsc_t res = rdtsc();
+ return ((unsigned long long)res.lo)|(((unsigned long long)res.hi) << 32);
}
static inline uint64_t tsc_to_uint64(tsc_t tstamp)
--
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