coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/delbin: Use Genesys Logic GL9755
by Ravishankar Sarawadi (Code Review) 28 Sep '20

28 Sep '20

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45708 ) Change subject: mb/google/delbin: Use Genesys Logic GL9755 ...................................................................... mb/google/delbin: Use Genesys Logic GL9755 Enable newly added PCIe Gen2 to SD 4.0 card reader controller GL9755 for Delbin. BUG=b:166141961 TEST=Boot to kernel on Delbin board. Check PC10 in IDON. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I2589ab2334625ec0d20dbdd5f3a31d98235aad2d --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45708/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 10a9411..be8d2f6 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -5,6 +5,7 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 + select DRIVERS_GENESYSLOGIC_GL9755 config BOARD_GOOGLE_ELDRID bool "-> Eldrid" -- To view, visit https://review.coreboot.org/c/coreboot/+/45708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2589ab2334625ec0d20dbdd5f3a31d98235aad2d Gerrit-Change-Number: 45708 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/Kconfig: Move pagetables down by 4K
by Patrick Rudolph (Code Review) 28 Sep '20

28 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37394 ) Change subject: arch/x86/Kconfig: Move pagetables down by 4K ...................................................................... arch/x86/Kconfig: Move pagetables down by 4K In case of 64K bootblock the pagetables doesn't fit, as the CBFS header also needs a few bytes. Fixes build error on platforms that use 64KiB bootblock. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37394/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 0e6f486..1e27970 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -68,7 +68,7 @@ config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" depends on ARCH_BOOTBLOCK_X86_64 - default 0xfffea000 + default 0xfffe9000 help The position where to place pagetables. Needs to be known at compile time. Must not overlap other files in CBFS. -- To view, visit https://review.coreboot.org/c/coreboot/+/37394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f Gerrit-Change-Number: 37394 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuni...
by Matt DeVillier (Code Review) 28 Sep '20

28 Sep '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45696 ) Change subject: mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params ...................................................................... mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params Some Librem Minis exhibit issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this, so limiting SATA speeds to 3Gbps is no longer needed. Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7 Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_whl/ramstage.c M src/mainboard/purism/librem_whl/romstage.c 2 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45696/1 diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_whl/ramstage.c index 07ede66..56ed1b7 100644 --- a/src/mainboard/purism/librem_whl/ramstage.c +++ b/src/mainboard/purism/librem_whl/ramstage.c @@ -10,7 +10,4 @@ size_t num_gpios; const struct pad_config *gpio_table = variant_gpio_table(&num_gpios); cnl_configure_pads(gpio_table, num_gpios); - - /* Limit SATA speed to 3Gbps until correct HSIO PHY settings determined */ - params->SataSpeedLimit = 2; } diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_whl/romstage.c index 9f8d600..c45f138 100644 --- a/src/mainboard/purism/librem_whl/romstage.c +++ b/src/mainboard/purism/librem_whl/romstage.c @@ -48,5 +48,12 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + cannonlake_memcfg_init(mem_cfg, &memcfg); + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20 Gerrit-Change-Number: 45696 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_skl: Enable and set SATA tuning params
by Matt DeVillier (Code Review) 28 Sep '20

28 Sep '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45695 ) Change subject: mb/purism/librem_skl: Enable and set SATA tuning params ...................................................................... mb/purism/librem_skl: Enable and set SATA tuning params Some Librems have issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this. Test: build/boot Librem 15v3 with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7 Change-Id: I078deeff7fc54694393b5b16c41c5d622b332781 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_skl/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/45695/1 diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index de493b0..7be8325 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -64,4 +64,10 @@ mem_cfg->DqPinsInterleaved = TRUE; mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I078deeff7fc54694393b5b16c41c5d622b332781 Gerrit-Change-Number: 45695 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/eldrid: Configure GPP_S4 and GPP_S5
by Nick Chen (Code Review) 28 Sep '20

28 Sep '20

Nick Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45689 ) Change subject: mb/google/volteer/variants/eldrid: Configure GPP_S4 and GPP_S5 ...................................................................... mb/google/volteer/variants/eldrid: Configure GPP_S4 and GPP_S5 GPP_S4 and GPP_S5 use as DMIC pins that need to be defined as NF2 BUG=b:168564129 Signed-off-by: nick_xr_chen <nick_xr_chen(a)wistron.corp-partner.google.com> Change-Id: Ia1fca960ac85f253882f0aa68b370eed49ac67b7 --- M src/mainboard/google/volteer/variants/eldrid/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45689/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c index 8ea1444e..4f6650b 100644 --- a/src/mainboard/google/volteer/variants/eldrid/gpio.c +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -154,9 +154,9 @@ /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA_R */ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* S4 : SNDW2_CLK ==> PCH_DMIC_CAM_SCL_R */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* S5 : SNDW2_DATA ==> PCH_DMIC_CAM_SDA_R */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/45689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1fca960ac85f253882f0aa68b370eed49ac67b7 Gerrit-Change-Number: 45689 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/terrador: Enable audio SMBIOS OEM string
by Kevin Cheng (Code Review) 28 Sep '20

28 Sep '20

Kevin Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45673 ) Change subject: mb/google/volteer/var/terrador: Enable audio SMBIOS OEM string ...................................................................... mb/google/volteer/var/terrador: Enable audio SMBIOS OEM string It needs to use probe statement in overridetree.cb to enable the cache of fw_config field implemented by cb:44782 and cb:44783. BUG=b:161963281 TEST= dmidecode -t 11 shows correct audio fw_config. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: DB_USB-USB4_GEN2 String 2: AUDIO-MAX98373_ALC5682I_I2S_UP4 Signed-off-by: Kevin Cheng <kevin.cheng(a)intel.com> Change-Id: I68c19b67d945aaca3e9ebec87eb27a4b07e1a49e --- M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/todor/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45673/1 diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index a42664e..95f1f8a 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -38,6 +38,7 @@ register "desc" = ""Right Speaker Amp"" register "name" = ""MAXR"" device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 end end chip drivers/i2c/max98373 @@ -47,6 +48,7 @@ register "desc" = ""Left Speaker Amp"" register "name" = ""MAXL"" device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 end end end # I2C #0 0xA0E8 diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index a42664e..95f1f8a 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -38,6 +38,7 @@ register "desc" = ""Right Speaker Amp"" register "name" = ""MAXR"" device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 end end chip drivers/i2c/max98373 @@ -47,6 +48,7 @@ register "desc" = ""Left Speaker Amp"" register "name" = ""MAXL"" device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 end end end # I2C #0 0xA0E8 -- To view, visit https://review.coreboot.org/c/coreboot/+/45673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68c19b67d945aaca3e9ebec87eb27a4b07e1a49e Gerrit-Change-Number: 45673 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Cheng <kevin.cheng(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: update GPIO config for berknip
by Kevin Chiu (Code Review) 28 Sep '20

28 Sep '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45642 ) Change subject: mb/google/zork: update GPIO config for berknip ...................................................................... mb/google/zork: update GPIO config for berknip update telemetry to improve the performance. BUG=b:168581158 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Ib93905cd89132664b06f2476e94494e96980642c Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/berknip/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45642/1 diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 868db9b..9562939 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -15,9 +15,9 @@ register "stapm_time_constant" = "200" #second register "sustained_power_limit" = "12000" #mw - register "telemetry_vddcr_vdd_slope" = "62451" #mA + register "telemetry_vddcr_vdd_slope" = "65599" #mA register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "27301" #mA + register "telemetry_vddcr_soc_slope" = "29788" #mA register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/45642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib93905cd89132664b06f2476e94494e96980642c Gerrit-Change-Number: 45642 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/mainboard: Fix OCP Delta Lake Link
by Christian Walter (Code Review) 28 Sep '20

28 Sep '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45659 ) Change subject: Documentation/mainboard: Fix OCP Delta Lake Link ...................................................................... Documentation/mainboard: Fix OCP Delta Lake Link Change-Id: I379d6a7b72a0398c34ea8eeda09ccd663fc372ce Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M Documentation/mainboard/index.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45659/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0eefee8..998de61 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -118,6 +118,7 @@ ## OCP +- [Delta Lake](ocp/deltalake.md) - [Tioga Pass](ocp/tiogapass.md) ## Open Cellular -- To view, visit https://review.coreboot.org/c/coreboot/+/45659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I379d6a7b72a0398c34ea8eeda09ccd663fc372ce Gerrit-Change-Number: 45659 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/magolor: apply DPTF setting
by Ren Kuo (Code Review) 28 Sep '20

28 Sep '20

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45453 ) Change subject: mb/google/dedede/var/magolor: apply DPTF setting ...................................................................... mb/google/dedede/var/magolor: apply DPTF setting add the tcc, critical, passive policy, and pl values BUG=b:168353037 TEST=build and verify by thermal tool Change-Id: I887d494ff097a881d519a456f24578a278323051 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45453/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 0daaea3..3a61981 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -40,7 +40,49 @@ }, }" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "tcc_offset" = "15" # TCC of 90C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 7000, + .max_power = 12000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 3000 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + device generic 0 on end + end + end # SA Thermal device device pci 05.0 on # IPU - MIPI Camera chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" -- To view, visit https://review.coreboot.org/c/coreboot/+/45453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I887d494ff097a881d519a456f24578a278323051 Gerrit-Change-Number: 45453 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Add ACPI support for camera in magolor
by Ren Kuo (Code Review) 28 Sep '20

28 Sep '20

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45329 ) Change subject: mb/google/dedede: Add ACPI support for camera in magolor ...................................................................... mb/google/dedede: Add ACPI support for camera in magolor 1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU 2. add IPU/VCM/NVM/CAM1 in devicetree BUG=b:166527568 TEST= build and verify by cam ap on DUT Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: Ica6aa8ddc03a1dab5b548a759825dd3a4de3101f --- M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/variants/magolor/overridetree.cb 2 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45329/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 40738a0..d25db10 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -59,3 +59,5 @@ bool "-> Magolor" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 9b7f1f4..92d1e0e 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -41,6 +41,20 @@ }" device domain 0 on + device pci 05.0 on # IPU - MIPI Camera + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{1,2}" + register "cio2_lane_endpoint[1]" = ""^I2C3.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -131,6 +145,75 @@ device i2c 39 on end end end # I2C 2 + device pci 15.3 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C64"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + + device i2c 50 on end + end + end # I2C 3 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/45329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica6aa8ddc03a1dab5b548a759825dd3a4de3101f Gerrit-Change-Number: 45329 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020