coreboot-gerrit September 2020

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Change in coreboot[master]: mb/google/vilboz: update telemetry settings
by chris wang (Code Review) 28 Sep '20

28 Sep '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44804 to review the following change. Change subject: mb/google/vilboz: update telemetry settings ...................................................................... mb/google/vilboz: update telemetry settings Update telemetry setting for second SDLE testing. BUG=b:160698427 BRANCH=None TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I4cf5b8f090befd6a3c4990f44f2f200bc66aa1f4 --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44804/1 diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 00adb23..b547590 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -18,10 +18,10 @@ # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "32453" #mA - register "telemetry_vddcr_vdd_offset" = "168" - register "telemetry_vddcr_soc_slope" = "22644" #mA - register "telemetry_vddcr_soc_offset" = "-70" + register "telemetry_vddcr_vdd_slope" = "32643" #mA + register "telemetry_vddcr_vdd_offset" = "208" + register "telemetry_vddcr_soc_slope" = "22742" #mA + register "telemetry_vddcr_soc_offset" = "-83" # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cf5b8f090befd6a3c4990f44f2f200bc66aa1f4 Gerrit-Change-Number: 44804 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: drivers/spi: Check return value for error handling
by John Zhao (Code Review) 28 Sep '20

28 Sep '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45620 ) Change subject: drivers/spi: Check return value for error handling ...................................................................... drivers/spi: Check return value for error handling Coverity detects calling function spi_sdcard_do_command without checking return value. Fix this issue by chekcing return value for error handling. Found-by: Coverity CID 1407737 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ie0d28806b5c0b4c6d509e583d115358864eeff80 --- M src/drivers/spi/spi_sdcard.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/45620/1 diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c index 4eb033e..a670111 100644 --- a/src/drivers/spi/spi_sdcard.c +++ b/src/drivers/spi/spi_sdcard.c @@ -354,7 +354,9 @@ uint32_t *out_register) { /* CMD55 */ - spi_sdcard_do_command(card, APP_CMD, 0, NULL); + if (spi_sdcard_do_command(card, APP_CMD, 0, NULL)) + return -1; + return spi_sdcard_do_command_help(card, 1, cmd, argument, out_register); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0d28806b5c0b4c6d509e583d115358864eeff80 Gerrit-Change-Number: 45620 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: cpu/intel/206ax: Fix get_cores_per_package
by Evgeny Zinoviev (Code Review) 28 Sep '20

28 Sep '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42413 ) Change subject: cpu/intel/206ax: Fix get_cores_per_package ...................................................................... cpu/intel/206ax: Fix get_cores_per_package Current implementation uses CPUID 0Bh function that returns numbers of logical cores of requested level. The problem with this approach is that this value doesn't change when HyperThreading is disabled (it's in the Intel docs), so it breaks generate_cpu_entries(). Use MSR 0x35 instead, which returns correct number of logical processors with and without HT. Related to #29669. Change-Id: Ib32c2d40408cfa42ca43ab42ed661c168e579ada Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/cpu/intel/model_206ax/acpi.c 1 file changed, 5 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42413/1 diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 9ff0673..44b3360 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -14,18 +14,13 @@ static int get_cores_per_package(void) { - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; + msr_t msr; + int logical_cores; - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; + msr = rdmsr(MSR_CORE_THREAD_COUNT); + logical_cores = msr.lo & 0xffff; - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; + return logical_cores; } static void generate_cstate_entries(acpi_cstate_t *cstates, -- To view, visit https://review.coreboot.org/c/coreboot/+/42413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib32c2d40408cfa42ca43ab42ed661c168e579ada Gerrit-Change-Number: 42413 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: mb/google/zork: update telemetry settings for dirinboz
by Kevin Chiu (Code Review) 28 Sep '20

28 Sep '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45581 ) Change subject: mb/google/zork: update telemetry settings for dirinboz ...................................................................... mb/google/zork: update telemetry settings for dirinboz update telemetry to improve the performance. BUG=b:154863613 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I464b90550aaa1666ce3f2393856bf46fe7686d1d Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/45581/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 05c5110..ead478c 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -17,6 +17,10 @@ # End : OPN Performance Configuration + register "telemetry_vddcr_vdd_slope" = "42465" #mA + register "telemetry_vddcr_vdd_offset" = "69" + register "telemetry_vddcr_soc_slope" = "42667" #mA + register "telemetry_vddcr_soc_offset" = "167" # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/45581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I464b90550aaa1666ce3f2393856bf46fe7686d1d Gerrit-Change-Number: 45581 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/google/dedede/var/drawcia: Enable EC keyboard backlight
by Chen Wisley (Code Review) 28 Sep '20

28 Sep '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45570 ) Change subject: mb/google/dedede/var/drawcia: Enable EC keyboard backlight ...................................................................... mb/google/dedede/var/drawcia: Enable EC keyboard backlight BUG=b:168847046 TEST=emerge-dedede coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I16ed22aa5e270ad2d5c964764cc134b72941d4e4 --- M src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45570/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h b/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h index 08870e0..27c930d 100644 --- a/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h @@ -5,4 +5,7 @@ #include <baseboard/ec.h> +/* Enable Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16ed22aa5e270ad2d5c964764cc134b72941d4e4 Gerrit-Change-Number: 45570 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: src/arch/x86:Add support for low power idle table
by Shaunak Saha (Code Review) 28 Sep '20

28 Sep '20

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 4: Thanks for all the comments I am trying to change the patch as per the comments and verify. Will update soon with the data and doubts if any. -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 28 Sep 2020 07:31:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork/vilboz: Add new memory part H5ANAG6NDMR-XNC
by Amanda Hwang (Code Review) 28 Sep '20

28 Sep '20

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45682 ) Change subject: mb/google/zork/vilboz: Add new memory part H5ANAG6NDMR-XNC ...................................................................... mb/google/zork/vilboz: Add new memory part H5ANAG6NDMR-XNC Add new ID for memory part H5ANAG6NDMR-XNC. Command to generate files: go build gen_part_id.go local variant=vilboz ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:165611994 TEST=none Change-Id: Iaf613d54bf23b637e38917937ce3e78702b26a28 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc M src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/45682/1 diff --git a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc index 8868a69..c7890d0 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc @@ -9,3 +9,4 @@ SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = MT40A512M16TB-062E:J SPD_SOURCES += ddr4-spd-7.hex # ID = 5(0b0101) Parts = K4AAG165WA-BCWE SPD_SOURCES += ddr4-spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NDMR-XNC diff --git a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt index bfbe034..8afd956 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt @@ -4,3 +4,4 @@ MT40A512M16TB-062E:J 4 (0100) K4AAG165WA-BCWE 5 (0101) MT40A1G16KD-062E:E 6 (0110) +H5ANAG6NDMR-XNC 7 (0111) diff --git a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt index 08f4891..2b8d6df 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt @@ -12,3 +12,4 @@ MT40A512M16TB-062E:J, 4 K4AAG165WA-BCWE, 5 MT40A1G16KD-062E:E, 6 +H5ANAG6NDMR-XNC, 7 -- To view, visit https://review.coreboot.org/c/coreboot/+/45682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf613d54bf23b637e38917937ce3e78702b26a28 Gerrit-Change-Number: 45682 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: mb/google/zork/vilboz: Remove unused memory part IDs
by Amanda Hwang (Code Review) 28 Sep '20

28 Sep '20

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45679 ) Change subject: mb/google/zork/vilboz: Remove unused memory part IDs ...................................................................... mb/google/zork/vilboz: Remove unused memory part IDs These parts have not been used in any vilboz devices. Removing so IDs can be assigned more efficiently. Command to generate files: go build gen_part_id.go local variant=vilboz ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:165611994 TEST=none Change-Id: I99614acaf45db0556120c883577494d9f753ea12 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc M src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt 3 files changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/45679/1 diff --git a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc index 7328545..8868a69 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc @@ -2,8 +2,8 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC -SPD_SOURCES += ddr4-spd-6.hex # ID = 1(0b0001) Parts = H5ANAG6NCMR-VKC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCWE SPD_SOURCES += ddr4-spd-1.hex # ID = 3(0b0011) Parts = H5AN8G6NDJR-XNC SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = MT40A512M16TB-062E:J diff --git a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt index 6eb4bf3..bfbe034 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt @@ -1,6 +1,4 @@ DRAM Part Name ID to assign -H5AN8G6NCJR-VKC 0 (0000) -H5ANAG6NCMR-VKC 1 (0001) K4A8G165WC-BCWE 2 (0010) H5AN8G6NDJR-XNC 3 (0011) MT40A512M16TB-062E:J 4 (0100) diff --git a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt index 6afaeed..08f4891 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt @@ -7,8 +7,6 @@ # See util/spd_tools/ddr4/README.md for more details and instructions. # Part Name, Fixed ID (optional) -H5AN8G6NCJR-VKC, 0 -H5ANAG6NCMR-VKC, 1 K4A8G165WC-BCWE, 2 H5AN8G6NDJR-XNC, 3 MT40A512M16TB-062E:J, 4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99614acaf45db0556120c883577494d9f753ea12 Gerrit-Change-Number: 45679 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: util: Add new memory part for zork boards
by Amanda Hwang (Code Review) 28 Sep '20

28 Sep '20

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45647 ) Change subject: util: Add new memory part for zork boards ...................................................................... util: Add new memory part for zork boards Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=b:165611994 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- A src/mainboard/google/zork/spd/ddr4-spd-9.hex M src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt A src/soc/intel/tigerlake/spd/ddr4-spd-9.hex M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt 5 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45647/1 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-9.hex b/src/mainboard/google/zork/spd/ddr4-spd-9.hex new file mode 100644 index 0000000..a67d756 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-9.hex @@ -0,0 +1,32 @@ +23 11 0C 03 86 29 91 08 00 00 00 00 01 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt index 13de1cd..bb4080d 100644 --- a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt +++ b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt @@ -12,3 +12,4 @@ K4AAG165WA-BCWE,ddr4-spd-7.hex H5AN8G6NCJR-XNC,ddr4-spd-1.hex K4AAG165WA-BCTD,ddr4-spd-8.hex +H5ANAG6NDMR-XNC,ddr4-spd-9.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex new file mode 100644 index 0000000..a67d756 --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex @@ -0,0 +1,32 @@ +23 11 0C 03 86 29 91 08 00 00 00 00 01 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt index 13de1cd..bb4080d 100644 --- a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt @@ -12,3 +12,4 @@ K4AAG165WA-BCWE,ddr4-spd-7.hex H5AN8G6NCJR-XNC,ddr4-spd-1.hex K4AAG165WA-BCTD,ddr4-spd-8.hex +H5ANAG6NDMR-XNC,ddr4-spd-9.hex diff --git a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt index 2f4bc8e..fdfe938 100644 --- a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt +++ b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt @@ -179,6 +179,18 @@ "TRFC2MinPs": 260000, "TRFC4MinPs": 160000 } + }, + { + // Datasheet Revision: Rev. 1.0, Feb. 2020 + "name": "H5ANAG6NDMR-XNC", + "attribs": { + "speedMTps": 3200, + "CL_nRCD_nRP": 22, + "capacityPerDieGb": 16, + "diesPerPackage": 2, + "packageBusWidth": 16, + "ranksPerPackage": 1 + } } ] } -- To view, visit https://review.coreboot.org/c/coreboot/+/45647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Gerrit-Change-Number: 45647 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: disable eMMC per FW_CONFIG for Morphius
by Kevin Chiu (Code Review) 28 Sep '20

28 Sep '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45755 ) Change subject: mb/google/zork: disable eMMC per FW_CONFIG for Morphius ...................................................................... mb/google/zork: disable eMMC per FW_CONFIG for Morphius Morphius has SSD/eMMC SKU, we should turn off eMMC if storage is NVMe SSD. BUG=b:169211959 BRANCH=zork TEST=1. emerge-zork coreboot 2. Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Change-Id: I67d5d77ce3d827ae89b82529de59925f67eaf894 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/morphius/Makefile.inc A src/mainboard/google/zork/variants/morphius/variant.c 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45755/1 diff --git a/src/mainboard/google/zork/variants/morphius/Makefile.inc b/src/mainboard/google/zork/variants/morphius/Makefile.inc index 57e7136..51d19fe 100644 --- a/src/mainboard/google/zork/variants/morphius/Makefile.inc +++ b/src/mainboard/google/zork/variants/morphius/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += ./spd ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/morphius/variant.c b/src/mainboard/google/zork/variants/morphius/variant.c new file mode 100644 index 0000000..65ac2ab --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> +#include <console/console.h> + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + /* + * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. + */ + if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) { + printk(BIOS_INFO, "variant_devtree_update: turn off emmc\n"); + cfg->emmc_config.timing = SD_EMMC_DISABLE; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67d5d77ce3d827ae89b82529de59925f67eaf894 Gerrit-Change-Number: 45755 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020