coreboot-gerrit September 2020

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Change in coreboot[master]: mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader
by Felix Singer (Code Review) 28 Sep '20

28 Sep '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45776 ) Change subject: mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0 Gerrit-Change-Number: 45776 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 27 Sep 2020 17:47:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader
by Michael Niewöhner (Code Review) 28 Sep '20

28 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45776 ) Change subject: mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0 Gerrit-Change-Number: 45776 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Sun, 27 Sep 2020 15:57:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron: Add the Kontron mAL10 COMe module support
by Angel Pons (Code Review) 28 Sep '20

28 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add the Kontron mAL10 COMe module support ...................................................................... Patch Set 48: (38 comments) https://review.coreboot.org/c/coreboot/+/39133/48//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39133/48//COMMIT_MSG@7 PS48, Line 7: the drop `the` here https://review.coreboot.org/c/coreboot/+/39133/48//COMMIT_MSG@13 PS48, Line 13: Console (Kontron CPLD/EC) UART console on Kontron kempld https://review.coreboot.org/c/coreboot/+/39133/48//COMMIT_MSG@16 PS48, Line 16: network nit: controller https://review.coreboot.org/c/coreboot/+/39133/48//COMMIT_MSG@19 PS48, Line 19: ports Why only write `ports` here? https://review.coreboot.org/c/coreboot/+/39133/48//COMMIT_MSG@32 PS48, Line 32: As the payload was used: Tested payloads https://review.coreboot.org/c/coreboot/+/39133/48//COMMIT_MSG@34 PS48, Line 34: without video Using non-zero PrimaryDisplay on FSP-M might serve as a work-around for this problem https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/Kconfig: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 6: HAVE_ACPI_RESUME Does this even work with the chosen MRC options? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 28: This option sets the type of carrier board to be used with https://doc.coreboot.org/coding_style.html#kconfig-configuration-files https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 29: come COMe https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 29: kontron mal10 Capitalize accordingly? This help text is meant for human consumption https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 51: config MAINBOARD_SMBIOS_MANUFACTURER : string : default "Kontron" Redundant? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 55: config MAINBOARD_SMBIOS_PRODUCT_NAME : string : default "COMe-mAL10" Redundant? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 59: config INTEL_GMA_VBT_FILE : string : default "src/mainboard/$(MAINBOARDDIR)/data.vbt" Please mention this is necessary to override default variants behavior: # Override the default variant behavior, since the data.vbt is the same https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/acpi/cpld.asl: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 3: Device (CPLD) Why is this not under kontron/kempld? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 13: 0x0A80 This magic number matches that of bootblock.c, why not #define it? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 14: 0x0A80 Increment this and the length so that you only need a single IO entry. https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 15: 0x00 0 https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 16: 0x01 2 https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/bootblock.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 13: 0x3F8/0x2F8 I would drop these numbers. Instead, use `serial` (ports) https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 9: /* GPIO_0 - GPIO (DW0: 0x44000300, DW1: 0x0003d000) */ Unless you have access to schematics/boardviews, please drop these comments. https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 9: # Configure CLKREQ of PCIe root ports : register "pcie_rp_clkreq_pin[0]" = "1" : register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[2]" = "0" : register "pcie_rp_clkreq_pin[3]" = "0" : register "pcie_rp_clkreq_pin[4]" = "0" : register "pcie_rp_clkreq_pin[5]" = "0" Carriers should also control which PCIe root ports are enabled. Then, these clock request entries can be located in the corresponding PCIe root port devices. https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/ramstage.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 8: /* Configure GPIO */ : size_t num = 0; : const struct pad_config *gpio_table = get_gpio_table(&num); : gpio_configure_pads(gpio_table, num); Isn't there another place to do this? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 14: * CPU Power Management Configuration from AMI UEFI BIOS v112: : * [AMI BIOS] -> [Advanced] -> [Cpu Configuration] : * : * | EIST | [Enabled] | : * | Turbo Mode | [Enabled] | : * | Boot performance mode | [Max Performance] | : * | C-States | [Enabled] | : * | Enhanced C-states | [Enabled] | : * | Max Package C State | C0 | : * | Max Core C State | [Core C6] | : * | C-State Auto Demoti | [C1] | : * | C-State Un-demotion | [C1] | : * Is this info here for any particular reason? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 31: PkgCStateLimit Why? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 32: MaxCoreCState No enum for this either? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 41: LPSS_S0ixEnable Is this meant to be enabled? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/romstage.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 10: Profile Is there an enum for this? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 13: DualRankSupportEnable Why disable support for dual rank? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 19: RmtCheckRun Why skip margin check? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 25: MrcFastBoot Why no fast boot? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/variants/mal10/devicetree.cb: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 5: # Enable VT-d These comments say nothing useful. Experience says they eventually turn into lies (someone flips the value, and keeps the comment untouched). https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 96: 1 Problems with HS400? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 101: # Set LPC Serial IRQ mode Not much is gained from this comment either. https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 103: register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" : register "uart[1]" = "{ KEMPLD_UART_2F8, 3 }" nit: place these within the corresponding devices? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 115: register "sensor_mode.local_sensor_enable" = "1" : register "sensor_mode.rtd3" = "RTD_VOLTAGE_MODE" : register "sensor_mode.rtd2" = "RTD_VOLTAGE_MODE" : register "sensor_mode.rtd1" = "RTD_THERMISTOR_MODE" I think something like this should work: register "sensor_mode" = "{ \ .local_sensor_enable = 1, \ .rtd3 = RTD_VOLTAGE_MODE, \ .rtd2 = RTD_VOLTAGE_MODE, \ .rtd1 = RTD_THERMISTOR_MODE, \ }" Backslashes might not be needed. https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 127: 0x5F I've never seen a weather forecast specify temperatures in hex. I wonder why. https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/variants/mal10/gpio.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 7: /* SPI */ These "pad group" comments are fine. https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 9: /* GPIO_97 - FST_SPI_CS0_N (DW0: 0x44000502, DW1: 0x00003c00) */ Same as other gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 48 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 27 Sep 2020 15:57:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/Kconfig: Drop ROM sizes below 256KiB
by Nico Huber (Code Review) 28 Sep '20

28 Sep '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45753 ) Change subject: mb/Kconfig: Drop ROM sizes below 256KiB ...................................................................... mb/Kconfig: Drop ROM sizes below 256KiB Not even our emulation targets can build with these anymore. Change-Id: If108a17f824a31c375a43cb4903ee07c65217f6e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/Kconfig M src/mainboard/emulation/qemu-riscv/Kconfig 2 files changed, 0 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45753/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 77fcba1..af685db 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -13,10 +13,6 @@ config MAINBOARD_VENDOR string "Mainboard vendor name" -config BOARD_ROMSIZE_KB_64 - bool -config BOARD_ROMSIZE_KB_128 - bool config BOARD_ROMSIZE_KB_256 bool config BOARD_ROMSIZE_KB_512 @@ -47,8 +43,6 @@ # TODO: No help text possible for choice fields? choice prompt "ROM chip size" - default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 - default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 @@ -68,16 +62,6 @@ The build system will take care of creating a coreboot.rom file of the matching size. -config COREBOOT_ROMSIZE_KB_64 - bool "64 KB" - help - Choose this option if you have a 64 KB ROM chip. - -config COREBOOT_ROMSIZE_KB_128 - bool "128 KB" - help - Choose this option if you have a 128 KB ROM chip. - config COREBOOT_ROMSIZE_KB_256 bool "256 KB" help @@ -148,8 +132,6 @@ # Map the config names to an integer (KB). config COREBOOT_ROMSIZE_KB int - default 64 if COREBOOT_ROMSIZE_KB_64 - default 128 if COREBOOT_ROMSIZE_KB_128 default 256 if COREBOOT_ROMSIZE_KB_256 default 512 if COREBOOT_ROMSIZE_KB_512 default 1024 if COREBOOT_ROMSIZE_KB_1024 @@ -167,8 +149,6 @@ # Map the config names to a hex value (bytes). config ROM_SIZE hex - default 0x00010000 if COREBOOT_ROMSIZE_KB_64 - default 0x00020000 if COREBOOT_ROMSIZE_KB_128 default 0x00040000 if COREBOOT_ROMSIZE_KB_256 default 0x00080000 if COREBOOT_ROMSIZE_KB_512 default 0x00100000 if COREBOOT_ROMSIZE_KB_1024 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 5b556fc..ee0f337 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -57,8 +57,6 @@ # ugly, but CBFS is placed in DRAM... config OPENSBI_TEXT_START hex - default 0x80010000 if COREBOOT_ROMSIZE_KB_64 - default 0x80020000 if COREBOOT_ROMSIZE_KB_128 default 0x80040000 if COREBOOT_ROMSIZE_KB_256 default 0x80080000 if COREBOOT_ROMSIZE_KB_512 default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 -- To view, visit https://review.coreboot.org/c/coreboot/+/45753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If108a17f824a31c375a43cb4903ee07c65217f6e Gerrit-Change-Number: 45753 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron: Add the Kontron mAL10 COMe module support
by HAOUAS Elyes (Code Review) 28 Sep '20

28 Sep '20

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add the Kontron mAL10 COMe module support ...................................................................... Patch Set 48: (2 comments) https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/ramstage.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 9: size_t <stddef.h> ? https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/romstage.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 3: include <string.h> not used -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 48 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 27 Sep 2020 14:14:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron: Add the Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 27 Sep '20

27 Sep '20

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Angel Pons, Andrey Petrov, Patrick Rudolph, Aaron Durbin, Lance Zhao, Nico Huber, Martin Roth, Werner Zeh, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39133 to look at the new patch set (#48). Change subject: mb/kontron: Add the Kontron mAL10 COMe module support ...................................................................... mb/kontron: Add the Kontron mAL10 COMe module support This patch adds support for the Kontron mAL10 COMe module with the Apollo Lake SoC together with Kontron T10-TNI carrierboard. Working: - Console (Kontron CPLD/EC) - I2C (Kontron CPLD/EC) - USB2/3 - Ethernet network - eMMC - SATA - PCIe ports - IGD/DP - SMBus - HWM Not tested: - IGD/LVDS - SDIO TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) - Documentation As the payload was used: - SeaBIOS - Tianocore, UEFIPayload - without video, EFI-shell in console only Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A src/mainboard/kontron/mal10/Kconfig A src/mainboard/kontron/mal10/Kconfig.name A src/mainboard/kontron/mal10/Makefile.inc A src/mainboard/kontron/mal10/acpi/cpld.asl A src/mainboard/kontron/mal10/acpi/dptf.asl A src/mainboard/kontron/mal10/board_info.txt A src/mainboard/kontron/mal10/bootblock.c A src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc A src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt A src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c A src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h A src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb A src/mainboard/kontron/mal10/cmos.default A src/mainboard/kontron/mal10/cmos.layout A src/mainboard/kontron/mal10/data.vbt A src/mainboard/kontron/mal10/dsdt.asl A src/mainboard/kontron/mal10/mal10.fmd A src/mainboard/kontron/mal10/ramstage.c A src/mainboard/kontron/mal10/romstage.c A src/mainboard/kontron/mal10/variants/mal10/Makefile.inc A src/mainboard/kontron/mal10/variants/mal10/board_info.txt A src/mainboard/kontron/mal10/variants/mal10/devicetree.cb A src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads A src/mainboard/kontron/mal10/variants/mal10/gpio.c A src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h 25 files changed, 1,474 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39133/48 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 48 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/crossgcc: correct the spelling of 'verifying'
by Idwer Vollering (Code Review) 27 Sep '20

27 Sep '20

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45733 ) Change subject: util/crossgcc: correct the spelling of 'verifying' ...................................................................... util/crossgcc: correct the spelling of 'verifying' Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Change-Id: I46af7a225238046f393bbc4b3a214bebc527e079 --- M util/crossgcc/buildgcc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45733/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0f9cac5..d5cca6c 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -1217,7 +1217,7 @@ # Download, unpack, patch and build all packages -printf "Downloading and verifing tarballs ...\n" +printf "Downloading and verifying tarballs ...\n" mkdir -p tarballs for P in $PACKAGES; do download "$P" || exit "$?" -- To view, visit https://review.coreboot.org/c/coreboot/+/45733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46af7a225238046f393bbc4b3a214bebc527e079 Gerrit-Change-Number: 45733 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: Fix file permissions
by Kyösti Mälkki (Code Review) 27 Sep '20

27 Sep '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45737 ) Change subject: libpayload: Fix file permissions ...................................................................... libpayload: Fix file permissions Change-Id: Ibdc211d7f4ec0fbbefafb5eae4c1615c64c99280 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M payloads/libpayload/drivers/usb/usbmsc.c 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/45737/1 diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c old mode 100755 new mode 100644 -- To view, visit https://review.coreboot.org/c/coreboot/+/45737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdc211d7f4ec0fbbefafb5eae4c1615c64c99280 Gerrit-Change-Number: 45737 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{skl,cnl,icl,jsl,elh,tgl}: make XTAL S0ix qualification opt...
by Michael Niewöhner (Code Review) 27 Sep '20

27 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45723 ) Change subject: soc/intel/{skl,cnl,icl,jsl,elh,tgl}: make XTAL S0ix qualification optional ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/45723/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45723/3//COMMIT_MSG@8 PS3, Line 8: add reference to https://patchwork.kernel.org/patch/10810113/ -- To view, visit https://review.coreboot.org/c/coreboot/+/45723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17bac9b06e5291b1548704744e872b22b2435c9c Gerrit-Change-Number: 45723 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 27 Sep 2020 12:15:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skl,cnl,icl,jsl,elh,tgl}: make XTAL S0ix qualification opt...
by Michael Niewöhner (Code Review) 27 Sep '20

27 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45723 ) Change subject: soc/intel/{skl,cnl,icl,jsl,elh,tgl}: make XTAL S0ix qualification optional ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/45723/2/src/soc/intel/cannonlake/c… File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/c/coreboot/+/45723/2/src/soc/intel/cannonlake/c… PS2, Line 61: uint8_t s0ix_allow_xtal_on; > First, let's stop using the term "qualification", since it seems to cause great confusion and we're […] https://patchwork.kernel.org/patch/10810113/ confirms that btw. (assuming the description is correct) -- To view, visit https://review.coreboot.org/c/coreboot/+/45723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17bac9b06e5291b1548704744e872b22b2435c9c Gerrit-Change-Number: 45723 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 27 Sep 2020 11:34:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit September 2020