coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries
by Subrata Banik (Code Review) 30 Sep '20

30 Sep '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Sep 2020 15:33:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 30 Sep '20

30 Sep '20

Hello Elyes HAOUAS, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45536 to look at the new patch set (#6). Change subject: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries ...................................................................... soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries Make use of the previously added common function for generating CPPC entries, when Intel SpeedShift is enabled. Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/tigerlake/acpi.c 5 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45536/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/qemu-x86/car: Move long mode entry right before c entry
by Patrick Rudolph (Code Review) 29 Sep '20

29 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37370 ) Change subject: cpu/qemu-x86/car: Move long mode entry right before c entry ...................................................................... cpu/qemu-x86/car: Move long mode entry right before c entry Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/bootblock_crt0.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S 2 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37370/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3256731..e167a12 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -30,12 +30,6 @@ #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> - /* BIST result in eax */ - mov %eax, %ebx - /* entry64.inc preserves ebx. */ -#include <cpu/x86/64bit/entry64.inc> - mov %ebx, %eax - #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) /* Wait for a JTAG debugger to break in and set EBX non-zero */ diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 1fa0018..f7280bf 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -39,6 +39,9 @@ /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp + /* entry64.inc preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) movd %mm1, %rdi -- To view, visit https://review.coreboot.org/c/coreboot/+/37370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f Gerrit-Change-Number: 37370 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/ubsan.c: Drop GCC 5.x compatibility
by HAOUAS Elyes (Code Review) 29 Sep '20

29 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45821 ) Change subject: lib/ubsan.c: Drop GCC 5.x compatibility ...................................................................... lib/ubsan.c: Drop GCC 5.x compatibility Currently, coorboot uses GCC-8. Change-Id: I7387bdb4526cbe2832db9671f0a0df788a65b8c3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/ubsan.c 1 file changed, 3 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/45821/1 diff --git a/src/lib/ubsan.c b/src/lib/ubsan.c index 6873f7e..8c1a5e2 100644 --- a/src/lib/ubsan.c +++ b/src/lib/ubsan.c @@ -245,13 +245,8 @@ ABORT_VARIANT_VP_VP(vla_bound_not_positive); struct ubsan_float_cast_overflow_data { -/* -* TODO: Remove this GCC 5.x compatibility after switching to GCC 6.x. The -* GCC developers accidentally forgot the source location. Their -* libubsan probes to see if it looks like a path, but we don't need -* to maintain compatibility with multiple gcc releases. See below. -*/ -#if !(defined(__GNUC__) && __GNUC__ < 6) + +#if !defined(__GNUC__) struct ubsan_source_location location; #endif struct ubsan_type_descriptor *from_type; @@ -264,7 +259,7 @@ (struct ubsan_float_cast_overflow_data *)data_raw; ubsan_value_handle_t from = (ubsan_value_handle_t)from_raw; (void) from; -#if !(defined(__GNUC__) && __GNUC__ < 6) +#if !defined(__GNUC__) ubsan_abort(&data->location, "float cast overflow"); #else ubsan_abort(((void) data, &unknown_location), "float cast overflow"); -- To view, visit https://review.coreboot.org/c/coreboot/+/45821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7387bdb4526cbe2832db9671f0a0df788a65b8c3 Gerrit-Change-Number: 45821 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Michael Niewöhner (Code Review) 29 Sep '20

29 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 66: (1 comment) https://review.coreboot.org/c/coreboot/+/37441/64/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md: https://review.coreboot.org/c/coreboot/+/37441/64/Documentation/mainboard/s… PS64, Line 31: 0x235=03 and 0x13E=84 > It is the TPM on SPI Enable Flag, and Setting the SPI Frequency to 40Mhz. […] Then let's add that as comment -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 66 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 29 Sep 2020 08:15:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Update SLP_Sx assertion widths and PwrCycDur
by Jamie Ryu (Code Review) 29 Sep '20

29 Sep '20

Hello build bot (Jenkins), Jamie Ryu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44561 to look at the new patch set (#2). Change subject: mb/intel/tglrvp: Update SLP_Sx assertion widths and PwrCycDur ...................................................................... mb/intel/tglrvp: Update SLP_Sx assertion widths and PwrCycDur This patch updates the SLP_Sx assertion widths and power cycle duration for TGLRVP. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 TEST=Verified that the power cycle duration is 1~2s with global reset on TGLRVP. Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: Ic4bb5aac1e3832e9c4521f9a7970216394e59f29 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44561/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4bb5aac1e3832e9c4521f9a7970216394e59f29 Gerrit-Change-Number: 44561 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur
by Jamie Ryu (Code Review) 29 Sep '20

29 Sep '20

Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44559 ) Change subject: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur ...................................................................... Patch Set 3: (4 comments) https://review.coreboot.org/c/coreboot/+/44559/2/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/44559/2/src/mainboard/google/volte… PS2, Line 152: 3 > MinAssertDur50ms Tim, with current common code implementation, I think this definition cannot be used directly here to set the correct value. To add more information about the list of values to set, I updated more comments for each parameter. Please let me know if this looks okay. Thank you. https://review.coreboot.org/c/coreboot/+/44559/2/src/mainboard/google/volte… PS2, Line 153: 1 > MinAssertDur1s Same as above. https://review.coreboot.org/c/coreboot/+/44559/2/src/mainboard/google/volte… PS2, Line 154: 3 > MinAssertDur1s Same as above. https://review.coreboot.org/c/coreboot/+/44559/2/src/mainboard/google/volte… PS2, Line 155: 3 > MinAssertDur98ms Same as above. -- To view, visit https://review.coreboot.org/c/coreboot/+/44559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f Gerrit-Change-Number: 44559 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 29 Sep 2020 07:23:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur
by Jamie Ryu (Code Review) 29 Sep '20

29 Sep '20

Hello V Sowmya, build bot (Jenkins), Wonkyu Kim, Jamie Ryu, Rizwan Qureshi, Sridhar Siricilla, Raj Astekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44559 to look at the new patch set (#3). Change subject: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur ...................................................................... mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur This patch updates the SLP_Sx assertion widths and power cycle duration for volteer. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159108661 TEST=Verified that the power cycle duration is 1~2s with a global reset on volteer. Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/44559/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/44559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f Gerrit-Change-Number: 44559 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Add IGD Device ID
by Krishna P Bhat D (Code Review) 29 Sep '20

29 Sep '20

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45481 ) Change subject: soc/intel/jasperlake: Add IGD Device ID ...................................................................... soc/intel/jasperlake: Add IGD Device ID Add IGD Device ID for Jasperlake. Reference is taken from Jasperlake EDS volume 1(Document Number: 613601). TEST=Build and boot Jasperlake platform. Change-Id: I00ee7950ffa378b428a76bf367a9a05ab287e7ed Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/jasperlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/45481/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 944c20e..11f81dd 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3637,6 +3637,7 @@ #define PCI_DEVICE_ID_INTEL_JSL_GT1 0x4E51 #define PCI_DEVICE_ID_INTEL_JSL_GT2 0x4E71 #define PCI_DEVICE_ID_INTEL_JSL_GT3 0x4E61 +#define PCI_DEVICE_ID_INTEL_JSL_GT4 0x4E55 #define PCI_DEVICE_ID_INTEL_ADL_GT0 0x46ff #define PCI_DEVICE_ID_INTEL_ADL_GT1 0x4600 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 4561a38..23cf847 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -283,6 +283,7 @@ PCI_DEVICE_ID_INTEL_JSL_GT1, PCI_DEVICE_ID_INTEL_JSL_GT2, PCI_DEVICE_ID_INTEL_JSL_GT3, + PCI_DEVICE_ID_INTEL_JSL_GT4, PCI_DEVICE_ID_INTEL_ADL_GT0, PCI_DEVICE_ID_INTEL_ADL_GT1, PCI_DEVICE_ID_INTEL_ADL_GT1_1, diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index d7eb490..fa5ca69 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -45,6 +45,7 @@ { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" }, { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" }, { PCI_DEVICE_ID_INTEL_JSL_GT3, "Jasperlake GT3" }, + { PCI_DEVICE_ID_INTEL_JSL_GT4, "Jasperlake GT4" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/45481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ee7950ffa378b428a76bf367a9a05ab287e7ed Gerrit-Change-Number: 45481 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader
by Patrick Georgi (Code Review) 29 Sep '20

29 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45776 ) Change subject: mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader ...................................................................... mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader PcieRpSlotImplemented should only be set to 1 for PCIe ports implementing a PCIe slot. Drop it for the on-board card reader. Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45776 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 55c5c6e..e079dff 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -138,7 +138,6 @@ register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" - register "PcieRpSlotImplemented[5]" = "1" end device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/45776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0 Gerrit-Change-Number: 45776 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit September 2020