coreboot-gerrit September 2020

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Change in coreboot[master]: nb/intel/ironlake: Move DEFAULT_MCHBAR to Kconfig
by HAOUAS Elyes (Code Review) 30 Sep '20

30 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45617 ) Change subject: nb/intel/ironlake: Move DEFAULT_MCHBAR to Kconfig ...................................................................... nb/intel/ironlake: Move DEFAULT_MCHBAR to Kconfig Change-Id: Ie829a49fb425f9448a2b8ae677a3fcb6fdd14e63 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/ironlake/Kconfig M src/northbridge/intel/ironlake/acpi/hostbridge.asl M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/ironlake.h 5 files changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45617/1 diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index fbad4be..4c77849 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -11,6 +11,10 @@ if NORTHBRIDGE_INTEL_IRONLAKE +config DEFAULT_MCHBAR + hex + default 0xfed10000 + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl index d6a2cf8..bdfd281 100644 --- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl +++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl @@ -48,7 +48,7 @@ Name (CTCD, 1) /* CTDP Down Select */ Name (CTCU, 2) /* CTDP Up Select */ - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) + OperationRegion (MCHB, SystemMemory, CONFIG_DEFAULT_MCHBAR, 0x8000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x5930), diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 3cf597d..4a09ee1 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -12,7 +12,7 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index fa89bd9..7b4c11f 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -19,7 +19,7 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 7ed6afd..20de8f5 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -26,10 +26,8 @@ /* Northbridge BARs */ #ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ #else -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ @@ -100,9 +98,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -- To view, visit https://review.coreboot.org/c/coreboot/+/45617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie829a49fb425f9448a2b8ae677a3fcb6fdd14e63 Gerrit-Change-Number: 45617 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: nb/intel/haswell: Move DEFAULT_MCHBAR to Kconfig
by HAOUAS Elyes (Code Review) 30 Sep '20

30 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45616 ) Change subject: nb/intel/haswell: Move DEFAULT_MCHBAR to Kconfig ...................................................................... nb/intel/haswell: Move DEFAULT_MCHBAR to Kconfig Change-Id: Id6daa380958ff9de3969abc4f0f53440067b464a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/memmap.h M src/northbridge/intel/haswell/romstage.c 7 files changed, 12 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45616/1 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 84be33d..5152645 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -9,6 +9,10 @@ if NORTHBRIDGE_INTEL_HASWELL +config DEFAULT_MCHBAR + hex + default 0xfed10000 + config HASWELL_VBOOT_IN_BOOTBLOCK depends on VBOOT bool "Start verstage in bootblock" diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 4a9debf..243cb25 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -13,7 +13,7 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1d4eba6..e42c356 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -88,7 +88,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) + OperationRegion (MCHB, SystemMemory, CONFIG_DEFAULT_MCHBAR + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 9db6a9d..b9c2c03 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -16,8 +16,8 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + CONFIG_DEFAULT_MCHBAR) >> 32); pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 4bcaaa7..a1125ab 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -28,9 +28,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h index ac3b1db..2c1aa6a 100644 --- a/src/northbridge/intel/haswell/memmap.h +++ b/src/northbridge/intel/haswell/memmap.h @@ -7,7 +7,6 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 5b025eb..f922e68 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -47,7 +47,7 @@ struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .mchbar = (uintptr_t)CONFIG_DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, -- To view, visit https://review.coreboot.org/c/coreboot/+/45616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6daa380958ff9de3969abc4f0f53440067b464a Gerrit-Change-Number: 45616 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: nb/intel/gm45: Move DEFAULT_MCHBAR to Kconfig
by HAOUAS Elyes (Code Review) 30 Sep '20

30 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45615 ) Change subject: nb/intel/gm45: Move DEFAULT_MCHBAR to Kconfig ...................................................................... nb/intel/gm45: Move DEFAULT_MCHBAR to Kconfig Change-Id: I5544d398c43ab9f0f85db69b2a9d9075d5598ec2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/pcie.c 5 files changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45615/1 diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index f5d6712..788e15a 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -14,6 +14,10 @@ select INTEL_GMA_SSC_ALTERNATE_REF select PARALLEL_MP +config DEFAULT_MCHBAR + hex + default 0xfed14000 + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index af58e0e..2051afa 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -14,7 +14,7 @@ // now. Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 1be3518..25daf38 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -9,7 +9,7 @@ const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ - pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1); /* Setup DMIBAR. */ pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index dc993cf..fe5a265 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -171,10 +171,8 @@ (could be reduced to 10 bytes) */ #ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed14000) #define DEFAULT_DMIBAR ((u8 *)0xfed18000) #else -#define DEFAULT_MCHBAR 0xfed14000 #define DEFAULT_DMIBAR 0xfed18000 #endif #define DEFAULT_EPBAR 0xfed19000 @@ -237,9 +235,9 @@ * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR8(x) *((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + x)) #define HPLLVCO_MCHBAR 0x0c0f diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 5a4999e..ffb52c8 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -268,7 +268,7 @@ /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = (DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0); - DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR; + DMIBAR32(DMILE2A) = (uintptr_t)CONFIG_DEFAULT_MCHBAR; } void gm45_late_init(const stepping_t stepping) -- To view, visit https://review.coreboot.org/c/coreboot/+/45615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5544d398c43ab9f0f85db69b2a9d9075d5598ec2 Gerrit-Change-Number: 45615 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: soc/intel/cnl: enable common CPU code
by Michael Niewöhner (Code Review) 30 Sep '20

30 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/cnl: enable common CPU code ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Sep 2020 16:34:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/sandybridge: Move DEFAULT_MCHBAR to Kconfig
by HAOUAS Elyes (Code Review) 30 Sep '20

30 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45614 ) Change subject: nb/sandybridge: Move DEFAULT_MCHBAR to Kconfig ...................................................................... nb/sandybridge: Move DEFAULT_MCHBAR to Kconfig Change-Id: I7722daafd18f30aa5b5d2fe6b21abecd498f4089 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/dell/optiplex_9010/early_init.c M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/x220/early_init.c M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/early_init.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/early_init.c M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/memmap.h M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h 19 files changed, 25 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45614/1 diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 81eb6f4..b5c23bc 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -85,7 +85,7 @@ struct pei_data pd = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/dell/optiplex_9010/early_init.c b/src/mainboard/dell/optiplex_9010/early_init.c index e96ee34..4947ff0 100644 --- a/src/mainboard/dell/optiplex_9010/early_init.c +++ b/src/mainboard/dell/optiplex_9010/early_init.c @@ -32,8 +32,8 @@ * FIXME: the board gets stuck in reset loop in * mainboard_romstage_entry. Avoid that by clearing SSKPD */ - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + CONFIG_DEFAULT_MCHBAR) >> 32); MCHBAR16(SSKPD_HI) = 0; sch5545_early_init(0x2e); diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 2ffa3aa..ecfdfab 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -79,7 +79,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index f3da77c..f8e8553 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -86,7 +86,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index f0ffc9f..68e7905 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -54,7 +54,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index f2f21bc..8fd923f 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -91,7 +91,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 391d1f2..c83a110 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -14,7 +14,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index a2aaf33b..a44ee24 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -51,7 +51,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index d1aa9d5..85c87c1 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -56,7 +56,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index bb120bf..f08ea8c 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -12,7 +12,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 5b55873..fc0eaec 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -10,7 +10,7 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index 7076eb7..f43b21a 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -40,7 +40,7 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index ad4ddb9..3c1887a 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -117,7 +117,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 7d4a9a4..03ddf21 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -101,7 +101,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3d..8ab557d 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -9,6 +9,10 @@ if NORTHBRIDGE_INTEL_SANDYBRIDGE +config DEFAULT_MCHBAR + hex + default 0xfed10000 + config SANDYBRIDGE_VBOOT_IN_ROMSTAGE bool default n diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 45b5b8f..92165b0 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -52,8 +52,8 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + CONFIG_DEFAULT_MCHBAR) >> 32); pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); diff --git a/src/northbridge/intel/sandybridge/memmap.h b/src/northbridge/intel/sandybridge/memmap.h index 9825125..bd40252 100644 --- a/src/northbridge/intel/sandybridge/memmap.h +++ b/src/northbridge/intel/sandybridge/memmap.h @@ -4,7 +4,6 @@ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ /* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 697862f..b9defda 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -229,7 +229,7 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->mchbar = (uintptr_t)CONFIG_DEFAULT_MCHBAR; pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; pei_data->epbar = DEFAULT_EPBAR; pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8f9d118..fdb1795 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -49,9 +49,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -- To view, visit https://review.coreboot.org/c/coreboot/+/45614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7722daafd18f30aa5b5d2fe6b21abecd498f4089 Gerrit-Change-Number: 45614 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 30 Sep '20

30 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/45536/5/src/soc/intel/icelake/Kcon… File src/soc/intel/icelake/Kconfig: https://review.coreboot.org/c/coreboot/+/45536/5/src/soc/intel/icelake/Kcon… PS5, Line 37: select CPU_INTEL_COMMON > kindly submit a separate CL for ICL first, please add me there 😊 done, see CB:45826 -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Sep 2020 16:34:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: northbridge/intel/Kconfig: Introduce DEFAULT_EPBAR_ADDRESS symbol
by HAOUAS Elyes (Code Review) 30 Sep '20

30 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45676 ) Change subject: northbridge/intel/Kconfig: Introduce DEFAULT_EPBAR_ADDRESS symbol ...................................................................... northbridge/intel/Kconfig: Introduce DEFAULT_EPBAR_ADDRESS symbol This symbol value will be used to define DEFAULT_EPBAR Change-Id: I03a734e22f70f5a93e8ba5ac21b394ffaebaf54e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/Kconfig.bars 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/45676/1 diff --git a/src/northbridge/intel/Kconfig.bars b/src/northbridge/intel/Kconfig.bars index 8541b2c..f5bd502 100644 --- a/src/northbridge/intel/Kconfig.bars +++ b/src/northbridge/intel/Kconfig.bars @@ -5,3 +5,6 @@ config DEFAULT_DMIBAR_ADDRESS hex + +config DEFAULT_EPBAR_ADDRESS + hex -- To view, visit https://review.coreboot.org/c/coreboot/+/45676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03a734e22f70f5a93e8ba5ac21b394ffaebaf54e Gerrit-Change-Number: 45676 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: northbridge/intel/Kconfig: Introduce DEFAULT_DMIBAR_ADDRESS symbol
by HAOUAS Elyes (Code Review) 30 Sep '20

30 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45675 ) Change subject: northbridge/intel/Kconfig: Introduce DEFAULT_DMIBAR_ADDRESS symbol ...................................................................... northbridge/intel/Kconfig: Introduce DEFAULT_DMIBAR_ADDRESS symbol This symbol value will be used to define DEFAULT_DMIBAR Change-Id: I7fabefd13e28bd5a54e5583f356770a0289222b2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/Kconfig.bars 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45675/1 diff --git a/src/northbridge/intel/Kconfig.bars b/src/northbridge/intel/Kconfig.bars index bd0960f..8541b2c 100644 --- a/src/northbridge/intel/Kconfig.bars +++ b/src/northbridge/intel/Kconfig.bars @@ -2,3 +2,6 @@ config DEFAULT_MCHBAR_ADDRESS hex + +config DEFAULT_DMIBAR_ADDRESS + hex -- To view, visit https://review.coreboot.org/c/coreboot/+/45675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fabefd13e28bd5a54e5583f356770a0289222b2 Gerrit-Change-Number: 45675 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 30 Sep '20

30 Sep '20

Hello Elyes HAOUAS, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45536 to look at the new patch set (#7). Change subject: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries ...................................................................... soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries Make use of the previously added common function for generating CPPC entries, when Intel SpeedShift is enabled. Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/tigerlake/acpi.c 5 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45536/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 30 Sep '20

30 Sep '20

Hello Elyes HAOUAS, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45535 to look at the new patch set (#6). Change subject: soc/intel/common/block/acpi: add code for CPPC entries generation ...................................................................... soc/intel/common/block/acpi: add code for CPPC entries generation This adds the code for CPPC entries generation, needed for Intel SpeedShift, to common acpi code. The function will be called from the SoCs' acpi code in the follow-up change. Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45535/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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