Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40062 )
Change subject: sb/intel/lynxpoint: Expand RCBA register list ......................................................................
sb/intel/lynxpoint: Expand RCBA register list
Some registers do not seem to exist, and many were missing.
Change-Id: I6757f4a748cde9f3bed3bacf32112f3259de1d87 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/pch.h 1 file changed, 91 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40062/1
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 0a62803..6d6590a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -445,45 +445,11 @@
/* Southbridge IO BARs */
+#define PMBASE 0x40 #define GPIOBASE 0x48
-#define PMBASE 0x40 +#define CIR0050 0x0050 /* 32bit */
-#define VCH 0x0000 /* 32bit */ -#define VCAP1 0x0004 /* 32bit */ -#define VCAP2 0x0008 /* 32bit */ -#define PVC 0x000c /* 16bit */ -#define PVS 0x000e /* 16bit */ - -#define V0CAP 0x0010 /* 32bit */ -#define V0CTL 0x0014 /* 32bit */ -#define V0STS 0x001a /* 16bit */ - -#define V1CAP 0x001c /* 32bit */ -#define V1CTL 0x0020 /* 32bit */ -#define V1STS 0x0026 /* 16bit */ - -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - -#define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */
/* Root Port configuratinon space hide */ @@ -495,6 +461,9 @@ /* Root Port function number mask */ #define RPFN_FNMASK(port) (7 << ((port) * 4))
+#define CIR0900 0x0900 /* 32bit */ +#define CIR1100 0x1100 /* 32bit */ + #define TRSR 0x1e00 /* 8bit */ #define TRCR 0x1e10 /* 64bit */ #define TWDR 0x1e18 /* 64bit */ @@ -504,6 +473,41 @@ #define IOTR2 0x1e90 /* 64bit */ #define IOTR3 0x1e98 /* 64bit */
+#define V0CTL 0x2014 /* 32bit */ +#define V0STS 0x201a /* 16bit */ + +#define V1CTL 0x2020 /* 32bit */ +#define V1STS 0x2026 /* 16bit */ + +#define VPCTL 0x2030 /* 32bit */ +#define VPSTS 0x2038 /* 16bit */ + +#define VMCTL 0x2040 /* 32bit */ +#define VMSTS 0x2048 /* 16bit */ + +#define CIR2088 0x2088 +#define REC 0x20ac +#define LCAP 0x21a4 +#define LCTL 0x21a8 +#define DMIC 0x2234 +#define CIR2238 0x2238 +#define CIR228C 0x228c +#define DMC 0x2304 +#define CIR2314 0x2314 +#define CIR2320 0x2320 + +/* IO Buffer Programming */ +#define IOBPIRI 0x2330 +#define IOBPD 0x2334 +#define IOBPS 0x2338 +#define IOBPS_READY 0x0001 +#define IOBPS_TX_MASK 0x0006 +#define IOBPS_MASK 0xff00 +#define IOBPS_READ 0x0600 +#define IOBPS_WRITE 0x0700 +#define IOBPU 0x233a +#define IOBPU_MAGIC 0xf000 + #define TCTL 0x3000 /* 8bit */
#define NOINT 0 @@ -526,18 +530,6 @@ #define PIRQG 6 #define PIRQH 7
-/* IO Buffer Programming */ -#define IOBPIRI 0x2330 -#define IOBPD 0x2334 -#define IOBPS 0x2338 -#define IOBPS_READY 0x0001 -#define IOBPS_TX_MASK 0x0006 -#define IOBPS_MASK 0xff00 -#define IOBPS_READ 0x0600 -#define IOBPS_WRITE 0x0700 -#define IOBPU 0x233a -#define IOBPU_MAGIC 0xf000 - #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ #define D31IP_SIP2 20 /* SATA Pin 2 */ @@ -581,26 +573,66 @@ #define D20IR 0x3160 /* 16bit */ #define D21IR 0x3164 /* 16bit */ #define D19IR 0x3168 /* 16bit */ -#define ACPIIRQEN 0x31e0 /* 32bit */ -#define OIC 0x31fe /* 16bit */ -#define PMSYNC_CONFIG 0x33c4 /* 32bit */ -#define PMSYNC_CONFIG2 0x33cc /* 32bit */ -#define SOFT_RESET_CTRL 0x38f4 -#define SOFT_RESET_DATA 0x38f8
-#define DIR_ROUTE(a,b,c,d) \ - (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) +#define ACPIIRQEN 0x31e0 /* 32bit */ + +#define OIC 0x31fe /* 16bit */ + +#define PRSTS 0x3310 +#define CIR3314 0x3314 +#define PM_CFG 0x3318 +#define CIR3324 0x3324 +#define DEEP_S3_POL 0x3328 +#define DEEP_S4_POL 0x332c +#define DEEP_S5_POL 0x3330 +#define PM_CFG2 0x333c +#define CIR3340 0x3340 +#define CIR3344 0x3344 +#define CIR3348 0x3348 +#define CIR3350 0x3350 +#define CIR3360 0x3360 +#define CIR3368 0x3368 +#define CIR3378 0x3378 +#define CIR337C 0x337c +#define CIR3388 0x3388 +#define CIR3390 0x3390 +#define CIR33A0 0x33a0 +#define CIR33B0 0x33b0 +#define CIR33C0 0x33c0 +#define PMSYNC_CONFIG 0x33c4 /* 32bit */ +#define PMSYNC 0x33c8 +#define PMSYNC_CONFIG2 0x33cc /* 32bit */ +#define CIR33D0 0x33d0 +#define CIR33D4 0x33d4
#define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ #define GCS 0x3410 /* 32bit */ #define BUC 0x3414 /* 32bit */ -#define PCH_DISABLE_GBE (1 << 5) +#define PCH_DISABLE_GBE (1 << 5) +#define RC 0x3400 /* 32bit */ +#define HPTC 0x3404 /* 32bit */ +#define GCS 0x3410 /* 32bit */ +#define BUC 0x3414 /* 32bit */ #define FD 0x3418 /* 32bit */ +#define CG 0x341c /* 32bit */ +#define FDSW 0x3420 #define DISPBDF 0x3424 /* 16bit */ #define FD2 0x3428 /* 32bit */ -#define CG 0x341c /* 32bit */ +#define GSX_CTRL 0x3454 + +#define CIR3A28 0x3a28 +#define CIR3A2C 0x3a2c +#define CIR3A6C 0x3a6c +#define CIR3A80 0x3a80 +#define CIR3A84 0x3a84 +#define CIR3A88 0x3a88 + +#define SOFT_RESET_CTRL 0x38f4 +#define SOFT_RESET_DATA 0x38f8 + +#define DIR_ROUTE(a, b, c, d) \ + (((d) << DIR_IDR) | ((c) << DIR_ICR) | ((b) << DIR_IBR) | ((a) << DIR_IAR))
/* Function Disable 1 RCBA 0x3418 */ #define PCH_DISABLE_ALWAYS (1 << 0)
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40062
to look at the new patch set (#2).
Change subject: sb/intel/lynxpoint: Expand RCBA register list ......................................................................
sb/intel/lynxpoint: Expand RCBA register list
Some registers do not seem to exist, and many were missing.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I6757f4a748cde9f3bed3bacf32112f3259de1d87 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/pch.h 1 file changed, 91 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40062/2
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Matt DeVillier, Patrick Rudolph, HAOUAS Elyes, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40062
to look at the new patch set (#3).
Change subject: sb/intel/lynxpoint: Expand RCBA register list ......................................................................
sb/intel/lynxpoint: Expand RCBA register list
Some registers do not seem to exist, and many were missing. Note that many of the register definitions are currently unused. They will be put to good use in subsequent changes.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I6757f4a748cde9f3bed3bacf32112f3259de1d87 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/pch.h 1 file changed, 91 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40062/3
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40062 )
Change subject: sb/intel/lynxpoint: Expand RCBA register list ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40062/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40062/3//COMMIT_MSG@1 PS3, Line 1: Parent: 8ff2ecd3 (soc/intel/braswell: add ACPI backlight support) maybe mention the source for the changes, and that the new values will be used in subsequent commits?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40062 )
Change subject: sb/intel/lynxpoint: Expand RCBA register list ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40062/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40062/3//COMMIT_MSG@1 PS3, Line 1: Parent: 8ff2ecd3 (soc/intel/braswell: add ACPI backlight support)
maybe mention the source for the changes, and that the new values will be used in subsequent commits […]
Last part I just did. As to the source... Different places 😉
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40062 )
Change subject: sb/intel/lynxpoint: Expand RCBA register list ......................................................................
Patch Set 6:
I feel like it makes the most sense to eval this patch in conjunction with whatever other patches you have that will make use of it. Hard to eval on its own with no sources to verify against and no usages to check
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40062 )
Change subject: sb/intel/lynxpoint: Expand RCBA register list ......................................................................
Patch Set 6:
Patch Set 6:
I feel like it makes the most sense to eval this patch in conjunction with whatever other patches you have that will make use of it. Hard to eval on its own with no sources to verify against and no usages to check
Totally understandable. I am only rebasing it because it's a dependency for an unfinished change. I will mark this as WIP and hope it makes less noise.
Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/40062 )
Change subject: sb/intel/lynxpoint: Expand RCBA register list ......................................................................
Removed Code-Review+2 by Angel Pons th3fanbus@gmail.com
Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/40062 )
Change subject: sb/intel/lynxpoint: Expand RCBA register list ......................................................................
Removed Code-Review-2 by Angel Pons th3fanbus@gmail.com
-
Angel Pons (Code Review) -
Matt DeVillier (Code Review)