coreboot-gerrit April 2020

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Change in coreboot[master]: intel/common/fast_spi: Add Protected Range support
by Felix Singer (Code Review) 06 Apr '20

06 Apr '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39718 ) Change subject: intel/common/fast_spi: Add Protected Range support ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/39718/2/src/soc/intel/common/block… File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/39718/2/src/soc/intel/common/block… PS2, Line 224: int fast_spi_pr_set_and_lock(const unsigned pr, const uint32_t value) > Please fix Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia70afb8286bce882cd98a028cfd6c79bc9d624a1 Gerrit-Change-Number: 39718 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Apr 2020 13:20:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/fast_spi: Add Protected Range support
by Felix Singer (Code Review) 06 Apr '20

06 Apr '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39718 ) Change subject: intel/common/fast_spi: Add Protected Range support ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/39718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia70afb8286bce882cd98a028cfd6c79bc9d624a1 Gerrit-Change-Number: 39718 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Apr 2020 13:12:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/bd82x6x: Drop PCI resource reg override
by Felix Singer (Code Review) 06 Apr '20

06 Apr '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40230 ) Change subject: sb/intel/bd82x6x: Drop PCI resource reg override ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/40230/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40230/2//COMMIT_MSG@7 PS2, Line 7: Assignment of PCI resource registers is up to the allocator. > This could serve as a commit message body, but the summary should […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/40230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I184a263c81aa8a434fcd153406b73058914cb2f9 Gerrit-Change-Number: 40230 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 06 Apr 2020 13:02:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Remove unused Kconfig
by Ronak Kanabar (Code Review) 06 Apr '20

06 Apr '20

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40039 ) Change subject: soc/intel/common: Remove unused Kconfig ...................................................................... soc/intel/common: Remove unused Kconfig Change-Id: Ie337fd727d72118c43aa869da1446ea4fceadc5b Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/common/block/graphics/Kconfig 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/40039/1 diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index 36cac22..4ab9200 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -2,11 +2,3 @@ bool help Intel Processor common Graphics support - -config SKIP_GRAPHICS_ENABLING - bool - depends on SOC_INTEL_COMMON_BLOCK_GRAPHICS - default n - help - Skip GT specific programming in coreboot to support - early parts without GT enable. -- To view, visit https://review.coreboot.org/c/coreboot/+/40039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie337fd727d72118c43aa869da1446ea4fceadc5b Gerrit-Change-Number: 40039 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/razer/blade_stealth_kbl: Use ACPI brightness controls
by Frans Hendriks (Code Review) 06 Apr '20

06 Apr '20

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40146 ) Change subject: mb/razer/blade_stealth_kbl: Use ACPI brightness controls ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/40146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8979f74b583e9fca4a1b57fe9166e433cd1d596b Gerrit-Change-Number: 40146 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Apr 2020 12:27:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/bd82x6x: Drop PCI resource reg override
by Felix Singer (Code Review) 06 Apr '20

06 Apr '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40230 ) Change subject: sb/intel/bd82x6x: Drop PCI resource reg override ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/40230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I184a263c81aa8a434fcd153406b73058914cb2f9 Gerrit-Change-Number: 40230 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 06 Apr 2020 12:15:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add function to dump ME firmware status information
by Sridhar Siricilla (Code Review) 06 Apr '20

06 Apr '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39127 ) Change subject: soc/intel/tigerlake: Add function to dump ME firmware status information ...................................................................... Patch Set 10: > Patch Set 10: > > > Patch Set 10: > > > > > Patch Set 10: > > > > > > Hey guys. Can we implement this in src/soc/intel/common/block/cse/cse.c instead so we have a common code base. Other we would duplicate the code base > > > > HFSTS register is not same the across SoCs. Because of this reason we cannot avoid SoC specific macros if move the function to common code. Hence, recommendation is to make the function SoC specific > > It can be done, if you can create a directory inside common cse as MEx (x= CSE version) to address your header files related deltas. > Then from SoC code, you can just select which is your support ME version. In this logic, your common code can get dedicated header or registers delta from respective headers with very optimal changes. As you know, so far no SOC specific macros/ME Version specific code in CSE's common code and the amount of duplicated code is very less for now. So, going forward, if we see redundant code come with different ME versions, then we can introduce your idea to push the code to common. I would say let the code stay in SoC specific for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/39127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I831a51f9f482425bd3b97ef1d2404b1d06844d07 Gerrit-Change-Number: 39127 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Apr 2020 12:08:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Remove DDI A lane programming
by Ronak Kanabar (Code Review) 06 Apr '20

06 Apr '20

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40038 ) Change subject: soc/intel/jasperlake: Remove DDI A lane programming ...................................................................... soc/intel/jasperlake: Remove DDI A lane programming For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by default. And kernel driver no longer relies on coreboot to provide information via DDI_BUF_CTL_A(for DDI port A) register programming. Hence removing this code. BRANCH=None TEST=checked jslrvp compilation and boot. Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057 --- M src/soc/intel/jasperlake/graphics.c 1 file changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/40038/1 diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index 4f5d573..0ee340c 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> #include <types.h> @@ -31,24 +30,6 @@ void graphics_soc_init(struct device *dev) { - uint32_t ddi_buf_ctl; - - /* Skip IGD GT programming */ - if (CONFIG(SKIP_GRAPHICS_ENABLING)) - return; - - /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver do not execute. - */ - ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { - ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED | - DDI_BUF_IS_IDLE); - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); - } - /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/40038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057 Gerrit-Change-Number: 40038 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x/sata: Set values as described in BIOS spec
by Patrick Rudolph (Code Review) 06 Apr '20

06 Apr '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40231 ) Change subject: sb/intel/bd82x6x/sata: Set values as described in BIOS spec ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27360d6ea5d1f00b1ed350f47ff40a22f19dfb05 Gerrit-Change-Number: 40231 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 06 Apr 2020 11:36:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add function to dump ME firmware status information
by Philipp Deppenwiese (Code Review) 06 Apr '20

06 Apr '20

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39127 ) Change subject: soc/intel/tigerlake: Add function to dump ME firmware status information ...................................................................... Patch Set 10: Sounds like a good plan! -- To view, visit https://review.coreboot.org/c/coreboot/+/39127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I831a51f9f482425bd3b97ef1d2404b1d06844d07 Gerrit-Change-Number: 39127 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Apr 2020 11:29:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2020