Change in coreboot[master]: soc/intel/jasperlake: Remove DDI A lane programming

[Ronak Kanabar (Code Review)]

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

soc/intel/jasperlake: Remove DDI A lane programming

For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by
default. And kernel driver no longer relies on coreboot to provide
information via DDI_BUF_CTL_A(for DDI port A) register programming.
Hence removing this code.

BRANCH=None
TEST=checked jslrvp compilation and boot.
Signed-off-by: Ronak Kanabar

Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057
---
M src/soc/intel/jasperlake/graphics.c
1 file changed, 0 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/40038/1

diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c
index 4f5d573..0ee340c 100644
--- a/src/soc/intel/jasperlake/graphics.c
+++ b/src/soc/intel/jasperlake/graphics.c
@@ -19,7 +19,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
-#include <drivers/intel/gma/i915_reg.h>
 #include <drivers/intel/gma/opregion.h>
 #include <intelblocks/graphics.h>
 #include <types.h>
@@ -31,24 +30,6 @@

void graphics_soc_init(struct device *dev)
 {
-	uint32_t ddi_buf_ctl;
-
-	/* Skip IGD GT programming */
-	if (CONFIG(SKIP_GRAPHICS_ENABLING))
-		return;
-
-	/*
-	 * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
-	 * This will allow the kernel to use 4-lane eDP links properly
-	 * if the VBIOS or GOP driver do not execute.
-	 */
-	ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
-	if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
-		ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED |
-				DDI_BUF_IS_IDLE);
-		graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
-	}
-
    /*
     * GFX PEIM module inside FSP binary is taking care of graphics
     * initialization based on RUN_FSP_GOP Kconfig

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@16 
PS1, Line 16: Signed-off-by: Ronak Kanabar 
next line?
Signed-off-by: Ronak Kanabar 
Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057

https://review.coreboot.org/c/coreboot/+/40038/1/src/soc/intel/jasperlake/gr... 
File src/soc/intel/jasperlake/graphics.c:

https://review.coreboot.org/c/coreboot/+/40038/1/src/soc/intel/jasperlake/gr... 
PS1, Line 37: SKIP_GRAPHICS_ENABLING
Can we remove this Kconfig as well? Planning in a separate CL?

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40038/1/src/soc/intel/jasperlake/gr... 
File src/soc/intel/jasperlake/graphics.c:

https://review.coreboot.org/c/coreboot/+/40038/1/src/soc/intel/jasperlake/gr... 
PS1, Line 37: SKIP_GRAPHICS_ENABLING
> Can we remove this Kconfig as well? Planning in a separate CL?

Sorry I saw: https://review.coreboot.org/c/coreboot/+/40039/3

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@14 
PS1, Line 14: BRANCH=None
BUG=?

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

Patch Set 1:

(5 comments)

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@9 
PS1, Line 9: The
the

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@9 
PS1, Line 9: For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by
Please add a space before the (.

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@10 
PS1, Line 10: default. And kernel driver no longer relies on coreboot to provide
… lanes default to 4.

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@11 
PS1, Line 11: information via DDI_BUF_CTL_A(for DDI port A) register programming.
Space before (.

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@18 
PS1, Line 18: Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057
Please move this directly above the Signed-off-by line.

[Ronak Kanabar (Code Review)]

Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40038

to look at the new patch set (#2).

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

soc/intel/jasperlake: Remove DDI A lane programming

For newer Intel graphics (>=11), the DDI port max lanes default to 4.
And kernel driver no longer relies on coreboot to provide information
via DDI_BUF_CTL_A (for DDI port A) register programming. Hence removing
this code.

BUG=b:150788968
BRANCH=None
TEST=checked jslrvp compilation and boot.
Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/jasperlake/graphics.c
1 file changed, 0 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/40038/2

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

Patch Set 2:

(7 comments)

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@9 
PS1, Line 9: For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by
> Please add a space before the (.

Done

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@9 
PS1, Line 9: The
> the

Done

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@10 
PS1, Line 10: default. And kernel driver no longer relies on coreboot to provide
> … lanes default to 4.

Done

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@11 
PS1, Line 11: information via DDI_BUF_CTL_A(for DDI port A) register programming.
> Space before (.

Done

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@14 
PS1, Line 14: BRANCH=None
> BUG=?

Done

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@16 
PS1, Line 16: Signed-off-by: Ronak Kanabar
> next line? […]

Done

https://review.coreboot.org/c/coreboot/+/40038/1//COMMIT_MSG@18 
PS1, Line 18: Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057
> Please move this directly above the Signed-off-by line.

Done

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

Patch Set 3: Code-Review+2

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

Patch Set 3: Code-Review+2

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

Patch Set 3: Code-Review+2

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

soc/intel/jasperlake: Remove DDI A lane programming

For newer Intel graphics (>=11), the DDI port max lanes default to 4.
And kernel driver no longer relies on coreboot to provide information
via DDI_BUF_CTL_A (for DDI port A) register programming. Hence removing
this code.

BUG=b:150788968
BRANCH=None
TEST=checked jslrvp compilation and boot.
Change-Id: I4c171ec6a57d6fc53bee88420bfb3c0fbc5dc057
Signed-off-by: Ronak Kanabar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40038
Reviewed-by: Nico Huber 
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Aamir Bohra 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/jasperlake/graphics.c
1 file changed, 0 insertions(+), 19 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Aamir Bohra: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c
index 4f5d573..0ee340c 100644
--- a/src/soc/intel/jasperlake/graphics.c
+++ b/src/soc/intel/jasperlake/graphics.c
@@ -19,7 +19,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
-#include <drivers/intel/gma/i915_reg.h>
 #include <drivers/intel/gma/opregion.h>
 #include <intelblocks/graphics.h>
 #include <types.h>
@@ -31,24 +30,6 @@

void graphics_soc_init(struct device *dev)
 {
-	uint32_t ddi_buf_ctl;
-
-	/* Skip IGD GT programming */
-	if (CONFIG(SKIP_GRAPHICS_ENABLING))
-		return;
-
-	/*
-	 * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
-	 * This will allow the kernel to use 4-lane eDP links properly
-	 * if the VBIOS or GOP driver do not execute.
-	 */
-	ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
-	if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
-		ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED |
-				DDI_BUF_IS_IDLE);
-		graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
-	}
-
    /*
     * GFX PEIM module inside FSP binary is taking care of graphics
     * initialization based on RUN_FSP_GOP Kconfig

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40038 )

Change subject: soc/intel/jasperlake: Remove DDI A lane programming
......................................................................

Patch Set 4:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2113
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2112
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2111

Please note: This test is under development and might not be accurate at all!