coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: libpayload: add read64() and write64()
by Thomas Heijligen (Code Review) 04 Mar '20

04 Mar '20

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34206 ) Change subject: libpayload: add read64() and write64() ...................................................................... libpayload: add read64() and write64() Change-Id: I6febf13ed54a7707f5a99d3d2715c36e18517c12 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M payloads/libpayload/include/x86/arch/io.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34206/1 diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h index c417ce0..46836d9 100644 --- a/payloads/libpayload/include/x86/arch/io.h +++ b/payloads/libpayload/include/x86/arch/io.h @@ -64,6 +64,11 @@ return *((volatile uint32_t *)(addr)); } +static inline __attribute__((always_inline)) uint64_t read64(const volatile void *addr) +{ + return *((volatile uint64_t *)(addr)); +} + static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value) { *((volatile uint8_t *)(addr)) = value; @@ -79,6 +84,11 @@ *((volatile uint32_t *)(addr)) = value; } +static inline __attribute__((always_inline)) void write64(volatile void *addr, uint64_t value) +{ + *((volatile uint64_t *)(addr)) = value; +} + static inline unsigned int inl(int port) { unsigned long val; -- To view, visit https://review.coreboot.org/c/coreboot/+/34206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6febf13ed54a7707f5a99d3d2715c36e18517c12 Gerrit-Change-Number: 34206 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake
by Srinidhi N Kaushik (Code Review) 04 Mar '20

04 Mar '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39169 ) Change subject: soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake ...................................................................... soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake update SerialIoUartAutoFlow settings for Tiger Lake platform. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39169/1 diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index d22cde0..b24156c 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -120,6 +121,8 @@ /* PCH UART selection for FSP Debug */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + ASSERT(CONFIG_UART_FOR_CONSOLE < ARRAY_SIZE(params->SerialIoUartAutoFlow)); + params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; /* SATA */ dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/39169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 Gerrit-Change-Number: 39169 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

6 11

Change in ...coreboot[master]: soc/intel/denverton_ns: Allow using FSP repo
by Felix Singer (Code Review) 04 Mar '20

04 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931 Change subject: soc/intel/denverton_ns: Allow using FSP repo ...................................................................... soc/intel/denverton_ns: Allow using FSP repo Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8156d18..6f5ed2a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,8 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 1096549..dfb5c37 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -78,6 +78,16 @@ help The memory location of the Intel FSP-S binary for this platform. +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" + # CAR memory layout on DENVERTON_NS hardware: ## CAR base address - 0xfef00000 ## CAR size 1MB - 0x100 (0xfff00) -- To view, visit https://review.coreboot.org/c/coreboot/+/30931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Gerrit-Change-Number: 30931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

8 23

Change in coreboot[master]: src/ec,mainboard: Move weak smbios_system_sku() override inwards
by Edward O'Callaghan (Code Review) 04 Mar '20

04 Mar '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39146 ) Change subject: src/ec,mainboard: Move weak smbios_system_sku() override inwards ...................................................................... src/ec,mainboard: Move weak smbios_system_sku() override inwards Internalise smbios_system_sku() strong symbol inwards in the ec_skuid.c implementation and simply wrap a call to: google_chromeec_smbios_system_sku(). BUG=b:XXX BRANCH=none TEST=none Change-Id: I05ebfc8126c0fb176ca52c307c658f50611ab6ab Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/ec/google/chromeec/ec_skuid.c M src/mainboard/google/dedede/board_info.c M src/mainboard/google/hatch/mainboard.c M src/mainboard/google/octopus/Makefile.inc D src/mainboard/google/octopus/mainboard_misc.c M src/mainboard/google/volteer/mainboard.c 6 files changed, 5 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/39146/1 diff --git a/src/ec/google/chromeec/ec_skuid.c b/src/ec/google/chromeec/ec_skuid.c index f8fc203..aed41b3 100644 --- a/src/ec/google/chromeec/ec_skuid.c +++ b/src/ec/google/chromeec/ec_skuid.c @@ -34,3 +34,8 @@ snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); return sku_str; } + +const char *smbios_system_sku(void) +{ + return google_chromeec_smbios_system_sku(); +} diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index 7b10b23..1d222b2 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -12,11 +12,6 @@ #include <smbios.h> #include <string.h> -const char *smbios_system_sku(void) -{ - return google_chromeec_smbios_system_sku(); -} - const char *smbios_mainboard_manufacturer(void) { static char oem_name[32]; diff --git a/src/mainboard/google/hatch/mainboard.c b/src/mainboard/google/hatch/mainboard.c index 888acf7..e0e7a32 100644 --- a/src/mainboard/google/hatch/mainboard.c +++ b/src/mainboard/google/hatch/mainboard.c @@ -21,11 +21,6 @@ #include <string.h> #include <stdint.h> -const char *smbios_system_sku(void) -{ - return google_chromeec_smbios_system_sku(); -} - const char *smbios_mainboard_manufacturer(void) { static char oem_name[32]; diff --git a/src/mainboard/google/octopus/Makefile.inc b/src/mainboard/google/octopus/Makefile.inc index d36d5f7..aa05524 100644 --- a/src/mainboard/google/octopus/Makefile.inc +++ b/src/mainboard/google/octopus/Makefile.inc @@ -5,12 +5,10 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c -ramstage-y += mainboard_misc.c ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c smm-y += smihandler.c -smm-y += mainboard_misc.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/octopus/mainboard_misc.c b/src/mainboard/google/octopus/mainboard_misc.c deleted file mode 100644 index 8b281da..0000000 --- a/src/mainboard/google/octopus/mainboard_misc.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> -#include <boardid.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include <ec/ec.h> -#include <smbios.h> -#include <string.h> - -const char *smbios_system_sku(void) -{ - return google_chromeec_smbios_system_sku(); -} diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index dcefb5d..6ed928a 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -17,11 +17,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> -const char *smbios_system_sku(void) -{ - return google_chromeec_smbios_system_sku(); -} - static void mainboard_init(struct device *dev) { mainboard_ec_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/39146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05ebfc8126c0fb176ca52c307c658f50611ab6ab Gerrit-Change-Number: 39146 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mainboard/google/dedede: Migrate onto SKU ID helpers
by Edward O'Callaghan (Code Review) 04 Mar '20

04 Mar '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39036 ) Change subject: mainboard/google/dedede: Migrate onto SKU ID helpers ...................................................................... mainboard/google/dedede: Migrate onto SKU ID helpers Leverage the common sku id space helper encoders. dedede uses the non-legacy SKU ID space. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/board_info.c 2 files changed, 7 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/39036/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 5254d16..6a511ba 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -7,6 +7,7 @@ select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_JASPERLAKE + select EC_GOOGLE_CHROMEEC_SKU_ID_MAX if BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index ee89beb..f9ed44d 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -12,37 +12,9 @@ #include <smbios.h> #include <string.h> -#define SKU_UNKNOWN 0xffffffff -#define SKU_MAX 0x7fffffff - -static uint32_t board_info_get_sku(void) -{ - static uint32_t sku_id = SKU_UNKNOWN; - - if (sku_id != SKU_UNKNOWN) - return sku_id; - - if (google_chromeec_cbi_get_sku_id(&sku_id)) - sku_id = SKU_UNKNOWN; - - return sku_id; -} - const char *smbios_system_sku(void) { - /* sku{0..2147483647} */ - static char sku_str[14]; - uint32_t sku_id = board_info_get_sku(); - - if (sku_id == SKU_UNKNOWN || sku_id > SKU_MAX) { - printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", - __func__, sku_id); - return ""; - } - - snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); - - return sku_str; + return google_chromeec_smbios_system_sku(); } const char *smbios_mainboard_manufacturer(void) @@ -66,7 +38,11 @@ int board_info_get_fw_config(uint32_t *fw_config) { - uint32_t sku_id = board_info_get_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); + + /* FIXME: Move get_fw_config() in with rest of sku id helpers */ +#define SKU_UNKNOWN 0xffffffff +#define SKU_MAX 0x7fffffff /* * FW_CONFIG can potentially have all the bits set. So check the -- To view, visit https://review.coreboot.org/c/coreboot/+/39036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b Gerrit-Change-Number: 39036 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mainboard/google/octopus: Migrate onto SKU ID helpers
by Edward O'Callaghan (Code Review) 04 Mar '20

04 Mar '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39035 ) Change subject: mainboard/google/octopus: Migrate onto SKU ID helpers ...................................................................... mainboard/google/octopus: Migrate onto SKU ID helpers Leverage the common sku id space helper encoders and set the sku id max to 0xff for legacy to ensure we behave the same. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/mainboard_misc.c M src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/octopus/variants/bloog/variant.c M src/mainboard/google/octopus/variants/bobba/gpio.c M src/mainboard/google/octopus/variants/bobba/variant.c M src/mainboard/google/octopus/variants/casta/variant.c M src/mainboard/google/octopus/variants/dood/gpio.c M src/mainboard/google/octopus/variants/dood/variant.c M src/mainboard/google/octopus/variants/foob/gpio.c M src/mainboard/google/octopus/variants/foob/variant.c M src/mainboard/google/octopus/variants/garg/gpio.c M src/mainboard/google/octopus/variants/garg/variant.c M src/mainboard/google/octopus/variants/meep/gpio.c M src/mainboard/google/octopus/variants/meep/variant.c 15 files changed, 27 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/39035/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index a4e4982..7c9694c 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -116,6 +116,10 @@ int default 63 # GPE0_DW1_31 (GPIO_63) +config EC_GOOGLE_CHROMEEC_SKU_ID_MAX + hex + default 0xff # LEGACY SKU_ID space. + config DRAM_PART_NUM_NOT_ALWAYS_IN_CBI bool default y if BOARD_GOOGLE_BOBBA diff --git a/src/mainboard/google/octopus/mainboard_misc.c b/src/mainboard/google/octopus/mainboard_misc.c index 3672f66..8b281da 100644 --- a/src/mainboard/google/octopus/mainboard_misc.c +++ b/src/mainboard/google/octopus/mainboard_misc.c @@ -21,34 +21,7 @@ #include <smbios.h> #include <string.h> -#define SKU_UNKNOWN 0xFFFFFFFF -#define SKU_MAX 255 - -uint32_t get_board_sku(void) -{ - static uint32_t sku_id = SKU_UNKNOWN; - - if (sku_id != SKU_UNKNOWN) - return sku_id; - - if (google_chromeec_cbi_get_sku_id(&sku_id)) - sku_id = SKU_UNKNOWN; - - return sku_id; -} - const char *smbios_system_sku(void) { - static char sku_str[7]; /* sku{0..255} */ - uint32_t sku_id = get_board_sku(); - - if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { - printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", - __func__, sku_id); - return ""; - } - - snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); - - return sku_str; + return google_chromeec_smbios_system_sku(); } diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index 2132db5..bf08a85 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -35,8 +35,6 @@ const struct lpddr4_cfg *variant_lpddr4_config(void); /* Return memory SKU for the board. */ size_t variant_memory_sku(void); -/* Return board SKU */ -uint32_t get_board_sku(void); /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 699385e..1e5c3ca 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -42,7 +42,7 @@ const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_33_BLOOG: @@ -65,7 +65,7 @@ { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_33_BLOOG: diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index 7c522c7..dd10840 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -18,6 +18,7 @@ #include <boardid.h> #include <gpio.h> #include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> enum { SKU_37_DROID = 37, /* LTE */ @@ -60,7 +61,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_37_DROID: diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 1f6e80d..936eac8 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -58,7 +58,7 @@ const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 || sku_id == 41 || sku_id == 42 || sku_id == 43 || sku_id == 44) @@ -74,7 +74,7 @@ if (slp_typ != ACPI_S5) return; - switch (get_board_sku()) { + switch (google_chromeec_get_board_sku()) { case SKU_37_DROID: case SKU_38_DROID: case SKU_39_DROID: diff --git a/src/mainboard/google/octopus/variants/casta/variant.c b/src/mainboard/google/octopus/variants/casta/variant.c index 12c8dd7..ef50eaf 100644 --- a/src/mainboard/google/octopus/variants/casta/variant.c +++ b/src/mainboard/google/octopus/variants/casta/variant.c @@ -21,7 +21,7 @@ const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); if (sku_id == 2) filename = "wifi_sar-bluebird.hex"; @@ -31,7 +31,7 @@ bool variant_ext_usb_status(unsigned int port_type, unsigned int port_id) { - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); if (sku_id == 2 && port_id == RIGHT_USB_C_PORT_ID) return false; diff --git a/src/mainboard/google/octopus/variants/dood/gpio.c b/src/mainboard/google/octopus/variants/dood/gpio.c index 5b567b3..07eeb32 100644 --- a/src/mainboard/google/octopus/variants/dood/gpio.c +++ b/src/mainboard/google/octopus/variants/dood/gpio.c @@ -18,6 +18,7 @@ #include <boardid.h> #include <gpio.h> #include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> enum { SKU_1_LTE = 1, /* Wifi + LTE */ @@ -58,7 +59,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_1_LTE: diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index 7116061..f4b4eaa 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -61,7 +61,7 @@ if (slp_typ != ACPI_S5) return; - switch (get_board_sku()) { + switch (google_chromeec_get_board_sku()) { case SKU_1_LTE: power_off_lte_module(slp_typ); return; diff --git a/src/mainboard/google/octopus/variants/foob/gpio.c b/src/mainboard/google/octopus/variants/foob/gpio.c index dec2ff5..55f8196 100644 --- a/src/mainboard/google/octopus/variants/foob/gpio.c +++ b/src/mainboard/google/octopus/variants/foob/gpio.c @@ -20,8 +20,6 @@ #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> -#define SKU_UNKNOWN 0xFFFFFFFF - static const struct pad_config default_override_table[] = { PAD_NC(GPIO_52, UP_20K), PAD_NC(GPIO_53, UP_20K), @@ -70,9 +68,9 @@ const struct pad_config *variant_override_gpio_table(size_t *num) { const struct pad_config *c; - uint32_t sku_id = SKU_UNKNOWN; + uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); if (no_touchscreen_sku(sku_id)) { c = non_touchscreen_override_table; *num = ARRAY_SIZE(non_touchscreen_override_table); diff --git a/src/mainboard/google/octopus/variants/foob/variant.c b/src/mainboard/google/octopus/variants/foob/variant.c index dcc11dd..47639f6 100644 --- a/src/mainboard/google/octopus/variants/foob/variant.c +++ b/src/mainboard/google/octopus/variants/foob/variant.c @@ -30,7 +30,7 @@ return; /* SKU ID 1 does not have a touchscreen device, hence disable it. */ - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); if (no_touchscreen_sku(sku_id)) touchscreen_i2c_host->enabled = 0; } diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index eeeb466..987c69e 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -19,6 +19,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <variant/sku.h> +#include <ec/google/chromeec/ec.h> static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), @@ -72,7 +73,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_9_HDMI: diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index f5f350a..2afceb9 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -54,7 +54,7 @@ { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_9_HDMI: @@ -72,7 +72,7 @@ if (slp_typ != ACPI_S5) return; - switch (get_board_sku()) { + switch (google_chromeec_get_board_sku()) { case SKU_17_LTE: case SKU_18_LTE_TS: power_off_lte_module(slp_typ); diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 44d9fff..ed4eb05 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -18,6 +18,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <variant/sku.h> +#include <ec/google/chromeec/ec.h> static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), @@ -44,7 +45,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num) { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_33_DORP: diff --git a/src/mainboard/google/octopus/variants/meep/variant.c b/src/mainboard/google/octopus/variants/meep/variant.c index 20aaa0a..7cd1e47 100644 --- a/src/mainboard/google/octopus/variants/meep/variant.c +++ b/src/mainboard/google/octopus/variants/meep/variant.c @@ -22,7 +22,7 @@ const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_1_MEEP: @@ -45,7 +45,7 @@ { uint32_t sku_id; - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_33_DORP: -- To view, visit https://review.coreboot.org/c/coreboot/+/39035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440 Gerrit-Change-Number: 39035 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: mainboard/google/dedede: Migrate onto get fw_config helper
by Edward O'Callaghan (Code Review) 04 Mar '20

04 Mar '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39039 ) Change subject: mainboard/google/dedede: Migrate onto get fw_config helper ...................................................................... mainboard/google/dedede: Migrate onto get fw_config helper Fix the FIXME. BUG=b:149348474 BRANCH=none TEST=only tested on hatch Change-Id: Ic84ffb6188d1f98b076142829fe49afd38c528bc Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_boardid.c M src/mainboard/google/dedede/board_info.c 4 files changed, 13 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/39039/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 4bf41ac..c97b3ab 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -889,6 +889,17 @@ int google_chromeec_cbi_get_fw_config(uint32_t *fw_config) { + uint32_t sku_id = google_chromeec_get_board_sku(); + + /* + * FW_CONFIG can potentially have all the bits set. So check the + * sku_id to ensure that the CBI is provisioned before reading the + * FW_CONFIG. + */ + if ((sku_id == SKU_UNKNOWN) || + (sku_id > CONFIG_EC_GOOGLE_CHROMEEC_SKU_ID_MAX)) + return -1; + return cbi_get_uint32(fw_config, CBI_TAG_FW_CONFIG); } diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f5c2e1a..16ecf88 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -88,6 +88,8 @@ int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); +#define SKU_UNKNOWN 0xFFFFFFFF + uint32_t google_chromeec_get_board_sku(void); const char *google_chromeec_smbios_system_sku(void); diff --git a/src/ec/google/chromeec/ec_boardid.c b/src/ec/google/chromeec/ec_boardid.c index 41d9959..bc33007 100644 --- a/src/ec/google/chromeec/ec_boardid.c +++ b/src/ec/google/chromeec/ec_boardid.c @@ -30,8 +30,6 @@ return id; } -#define SKU_UNKNOWN 0xFFFFFFFF - uint32_t google_chromeec_get_board_sku(void) { static uint32_t sku_id = SKU_UNKNOWN; diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index f9ed44d..7b10b23 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -38,19 +38,5 @@ int board_info_get_fw_config(uint32_t *fw_config) { - uint32_t sku_id = google_chromeec_get_board_sku(); - - /* FIXME: Move get_fw_config() in with rest of sku id helpers */ -#define SKU_UNKNOWN 0xffffffff -#define SKU_MAX 0x7fffffff - - /* - * FW_CONFIG can potentially have all the bits set. So check the - * sku_id to ensure that the CBI is provisioned before reading the - * FW_CONFIG. - */ - if (sku_id == SKU_UNKNOWN || sku_id > SKU_MAX) - return -1; - return google_chromeec_cbi_get_fw_config(fw_config); } -- To view, visit https://review.coreboot.org/c/coreboot/+/39039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic84ffb6188d1f98b076142829fe49afd38c528bc Gerrit-Change-Number: 39039 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: lz4: Fix out-of-bounds reads
by Alexandre Rebert (Code Review) 04 Mar '20

04 Mar '20

Alexandre Rebert has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39174 ) Change subject: lz4: Fix out-of-bounds reads ...................................................................... lz4: Fix out-of-bounds reads Fix two out-of-bounds reads in lz4 decompression: 1) LZ4_decompress_generic could read one byte past the input buffer when decoding variable length literals due to a missing bounds check. This issue was resolved in libpayload, commonlib and cbfstool 2) ulz4fn could read up to 4 bytes past the input buffer when reading a lz4_block_header due to a missing bounds check. This issue was resolved in libpayload and commonlib. Change-Id: I5afdf7e1d43ecdb06c7b288be46813c1017569fc Signed-off-by: Alex Rebert <alexandre.rebert(a)gmail.com> Found-by: Mayhem --- M payloads/libpayload/liblz4/lz4.c.inc M payloads/libpayload/liblz4/lz4_wrapper.c M src/commonlib/bsd/lz4.c.inc M src/commonlib/bsd/lz4_wrapper.c M util/cbfstool/lz4/lib/lz4.c 5 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39174/1 diff --git a/payloads/libpayload/liblz4/lz4.c.inc b/payloads/libpayload/liblz4/lz4.c.inc index baa9110..68fac47 100644 --- a/payloads/libpayload/liblz4/lz4.c.inc +++ b/payloads/libpayload/liblz4/lz4.c.inc @@ -150,6 +150,7 @@ if ((length=(token>>ML_BITS)) == RUN_MASK) { unsigned s; + if ((endOnInput) && unlikely(ip>=iend-RUN_MASK)) goto _output_error; /* overflow detection */ do { s = *ip++; diff --git a/payloads/libpayload/liblz4/lz4_wrapper.c b/payloads/libpayload/liblz4/lz4_wrapper.c index d125ce33..3d17fe6 100644 --- a/payloads/libpayload/liblz4/lz4_wrapper.c +++ b/payloads/libpayload/liblz4/lz4_wrapper.c @@ -141,6 +141,9 @@ } while (1) { + if ((size_t)(in - src) + sizeof(struct lz4_block_header) > srcn) + break; /* input overrun */ + struct lz4_block_header b = { .raw = le32toh(*(uint32_t *)in) }; in += sizeof(struct lz4_block_header); diff --git a/src/commonlib/bsd/lz4.c.inc b/src/commonlib/bsd/lz4.c.inc index b3be4e5..8c75e2f 100644 --- a/src/commonlib/bsd/lz4.c.inc +++ b/src/commonlib/bsd/lz4.c.inc @@ -150,6 +150,7 @@ if ((length=(token>>ML_BITS)) == RUN_MASK) { unsigned s; + if ((endOnInput) && unlikely(ip>=iend-RUN_MASK)) goto _output_error; /* overflow detection */ do { s = *ip++; diff --git a/src/commonlib/bsd/lz4_wrapper.c b/src/commonlib/bsd/lz4_wrapper.c index 2367afc..3822e8c 100644 --- a/src/commonlib/bsd/lz4_wrapper.c +++ b/src/commonlib/bsd/lz4_wrapper.c @@ -129,6 +129,9 @@ } while (1) { + if ((size_t)(in - src) + sizeof(struct lz4_block_header) > srcn) + break; /* input overrun */ + struct lz4_block_header b = { { .raw = le32toh(*(const uint32_t *)in) } }; diff --git a/util/cbfstool/lz4/lib/lz4.c b/util/cbfstool/lz4/lib/lz4.c index 9c9a9a0..e393690 100644 --- a/util/cbfstool/lz4/lib/lz4.c +++ b/util/cbfstool/lz4/lib/lz4.c @@ -1206,6 +1206,7 @@ if ((length=(token>>ML_BITS)) == RUN_MASK) { unsigned s; + if ((endOnInput) && unlikely(ip>=iend-RUN_MASK)) goto _output_error; /* overflow detection */ do { s = *ip++; -- To view, visit https://review.coreboot.org/c/coreboot/+/39174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5afdf7e1d43ecdb06c7b288be46813c1017569fc Gerrit-Change-Number: 39174 Gerrit-PatchSet: 1 Gerrit-Owner: Alexandre Rebert <alexandre.rebert(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: i82371eb: Drop ops entry for i82371sb
by Keith Hui (Code Review) 03 Mar '20

03 Mar '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38598 ) Change subject: i82371eb: Drop ops entry for i82371sb ...................................................................... i82371eb: Drop ops entry for i82371sb All boards with this chipset use i82371eb (that shares PCI ID with i82371ab). Change-Id: Iab1e83b8f5fff44a33619c7925e5448169a2a87c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/isa.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38598/1 diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 00fbb77..1442470 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -158,9 +158,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, }; - -static const struct pci_driver isa_SB_driver __pci_driver = { - .ops = &isa_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82371SB_ISA, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab1e83b8f5fff44a33619c7925e5448169a2a87c Gerrit-Change-Number: 38598 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: README: Spell Web site with one space
by Paul Menzel (Code Review) 03 Mar '20

03 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384 Change subject: README: Spell Web site with one space ...................................................................... README: Spell Web site with one space Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/libpayload/README 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1 diff --git a/payloads/libpayload/README b/payloads/libpayload/README index fdf9b18..7348934 100644 --- a/payloads/libpayload/README +++ b/payloads/libpayload/README @@ -49,10 +49,10 @@ Please see the sample/ directory for details. -Website and Mailing List +Web site and Mailing List ------------------------ -The main website is https://www.coreboot.org/Libpayload. +The main web site is https://www.coreboot.org/Libpayload. For additional information, patches, and discussions, please join the coreboot mailing list at https://www.coreboot.org/Mailinglist, where most -- To view, visit https://review.coreboot.org/c/coreboot/+/31384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Gerrit-Change-Number: 31384 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

2 3

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020