coreboot-gerrit February 2020

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Change in coreboot[master]: mb/lenovo/t530/devicetree: Select docking_supported
by Peter Lemenkov (Code Review) 04 Mar '20

04 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38710 ) Change subject: mb/lenovo/t530/devicetree: Select docking_supported ...................................................................... mb/lenovo/t530/devicetree: Select docking_supported Looks like it should select it like any other Lenovo xx20/xx30 boards around. UNTESTED. Change-Id: Iaa4983c0a6365d77ac647f68d112a405d782d501 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t530/variants/t530/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/38710/1 diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 19fc18e..d6d9e2c 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -70,6 +70,8 @@ register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x04000201" + register "docking_supported" = "1" + register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" -- To view, visit https://review.coreboot.org/c/coreboot/+/38710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4983c0a6365d77ac647f68d112a405d782d501 Gerrit-Change-Number: 38710 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Explicitly silence sub-makes
by Nico Huber (Code Review) 04 Mar '20

04 Mar '20

Hello Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38931 to review the following change. Change subject: Makefile: Explicitly silence sub-makes ...................................................................... Makefile: Explicitly silence sub-makes GNU Make 4.3 doesn't propagate a global .SILENT to sub-processes anymore. Let's make it explicit to maintain the behaviour we are used to. From the changelog: [SV 54740] Ensure .SILENT settings do not leak into sub-makes Change-Id: I3de51c245d3344b062dc0fe9c62b8d5c0ac5e67d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/38931/1 diff --git a/Makefile b/Makefile index 41a9b3a..3f60493 100644 --- a/Makefile +++ b/Makefile @@ -82,6 +82,7 @@ ifneq ($(V),1) ifneq ($(Q),) .SILENT: +MAKEFLAGS += -s endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3de51c245d3344b062dc0fe9c62b8d5c0ac5e67d Gerrit-Change-Number: 38931 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/[tw]530/devicetree: Fix comment about chip codename
by Peter Lemenkov (Code Review) 04 Mar '20

04 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38708 ) Change subject: mb/lenovo/[tw]530/devicetree: Fix comment about chip codename ...................................................................... mb/lenovo/[tw]530/devicetree: Fix comment about chip codename Change-Id: I3323e713970041b0665ca17bbcad985cba600687 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t530/variants/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/w530/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/38708/1 diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 6f6dd1c..19fc18e 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -43,7 +43,7 @@ device pci 01.0 on end # PCIe bridge for discrete graphics device pci 02.0 on end # Internal graphics VGA controller - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + chip southbridge/intel/bd82x6x # Intel Series 6 Panther Point PCH # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index da5a094..c2e32e3 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -48,7 +48,7 @@ subsystemid 0x17aa 0x21f5 end - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + chip southbridge/intel/bd82x6x # Intel Series 6 Panther Point PCH # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) -- To view, visit https://review.coreboot.org/c/coreboot/+/38708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3323e713970041b0665ca17bbcad985cba600687 Gerrit-Change-Number: 38708 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/lenovo/t530/*/*/devicetree: whitespace and comments
by Peter Lemenkov (Code Review) 04 Mar '20

04 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37601 ) Change subject: mb/lenovo/t530/*/*/devicetree: whitespace and comments ...................................................................... mb/lenovo/t530/*/*/devicetree: whitespace and comments Only whitespace, minor comments. This helps making diff between devicetrees shorter. Change-Id: Ia1a84728abbece96a3d05b3b1616ac58535845bc Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t530/variants/t530/devicetree.cb M src/mainboard/lenovo/t530/variants/w530/devicetree.cb 2 files changed, 66 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37601/1 diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 47e40c3..c2a9259 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -39,9 +39,9 @@ device domain 0 on subsystemid 0x17aa 0x21f6 inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -86,9 +86,9 @@ device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on + device pci 1c.2 on # PCIe Port #3 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #3 (expresscard) + end device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 @@ -96,10 +96,9 @@ device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device pci 1f.0 on # PCI-LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -162,9 +161,9 @@ register "has_thinker1" = "1" end - end # LPC bridge + end device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on + device pci 1f.3 on # SMBus # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -176,7 +175,7 @@ device i2c 5e on end device i2c 5f on end end - end # SMBus + end device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 on end # Thermal end diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 135627f..f814c3f 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -14,31 +14,40 @@ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - device cpu_cluster 0x0 on - chip cpu/intel/model_206ax # FIXME: check all registers - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + device cpu_cluster 0 on + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip device lapic 0x0 on end device lapic 0xacac off end + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) end end register "pci_mmio_size" = "2048" - device domain 0x0 on + device domain 0 on subsystemid 0x17aa 0x21f6 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x21f5 + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) @@ -48,20 +57,30 @@ register "gpi1_routing" = "2" register "gpi13_routing" = "2" - register "c2_latency" = "0x0065" - register "docking_supported" = "1" - register "gen1_dec" = "0x007c1601" - register "gen2_dec" = "0x000c15e1" - register "gen4_dec" = "0x000c06a1" - register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" - register "sata_interface_speed_support" = "0x3" + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) register "sata_port_map" = "0x3f" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported + + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "xhci_overcurrent_mapping" = "0x4000201" + + register "docking_supported" = "1" + register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x04000201" - register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 @@ -71,7 +90,7 @@ subsystemid 0x17aa 0x21f3 end device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x83" @@ -90,11 +109,11 @@ device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # PCI-LPC bridge chip ec/lenovo/pmh7 + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" - device pnp ff.1 on end # dummy end chip drivers/pc80/tpm @@ -102,14 +121,23 @@ end chip ec/lenovo/h8 - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end register "config0" = "0xa7" register "config1" = "0x01" register "config2" = "0xa0" register "config3" = "0xe2" + register "has_keyboard_backlight" = "1" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "0" register "event2_enable" = "0xff" register "event3_enable" = "0xff" register "event4_enable" = "0xd0" @@ -124,18 +152,9 @@ register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" - register "has_keyboard_backlight" = "1" - register "has_power_management_beeps" = "0" register "has_bdc_detection" = "1" register "bdc_gpio_num" = "54" register "bdc_gpio_lvl" = "0" - - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end end chip drivers/lenovo/hybrid_graphics device pnp ff.f on end # dummy @@ -154,7 +173,8 @@ end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBus - chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end device i2c 56 on end @@ -168,10 +188,5 @@ device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21f5 - end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a84728abbece96a3d05b3b1616ac58535845bc Gerrit-Change-Number: 37601 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/testing/Makefile.inc: Remove viatool
by Angel Pons (Code Review) 04 Mar '20

04 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38853 ) Change subject: util/testing/Makefile.inc: Remove viatool ...................................................................... util/testing/Makefile.inc: Remove viatool It somehow creeps into `make clean`, but is not used at all. Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/testing/Makefile.inc 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38853/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 8e3882f..bf096d3 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -66,8 +66,7 @@ inteltool \ intelvbttool \ nvramtool \ -superiotool \ -viatool +superiotool TEST_PAYLOADLIST_INTERNAL= \ coreinfo \ -- To view, visit https://review.coreboot.org/c/coreboot/+/38853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec Gerrit-Change-Number: 38853 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: capitalize 'PCIe'
by HAOUAS Elyes (Code Review) 04 Mar '20

04 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39101 ) Change subject: src: capitalize 'PCIe' ...................................................................... src: capitalize 'PCIe' Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family14/fixme.c M src/mainboard/asrock/e350m1/acpi/routing.asl M src/mainboard/asus/f2a85-m/acpi/routing.asl M src/mainboard/gizmosphere/gizmo/acpi/routing.asl M src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl M src/mainboard/lenovo/g505s/acpi/routing.asl M src/mainboard/msi/ms7721/acpi/routing.asl M src/mainboard/pcengines/apu1/acpi/routing.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/baytrail/pcie.c M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/denverton_ns/smm.c M src/soc/intel/icelake/chip.h M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/chip.h M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/nvs.h 28 files changed, 30 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39101/1 diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index be7c635..658434d 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -100,7 +100,7 @@ PciValue |= 0x80000000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize GMM Base Address for Pcie Mode + /* Initialize GMM Base Address for PCIe Mode * Modify B0D1F0x18 */ PciAddress.Address.Bus = 0; @@ -112,7 +112,7 @@ PciValue |= 0x96000000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize FB Base Address for Pcie Mode + /* Initialize FB Base Address for PCIe Mode * Modify B0D1F0x10 */ PciAddress.Address.Register = 0x10; diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index 537bcac..0675012 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -199,7 +199,7 @@ /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index c0aef87..38ba142 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -78,7 +78,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl index 447d992..af05ec6 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl @@ -200,7 +200,7 @@ /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl index 22c4550..a1ce860 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl @@ -90,7 +90,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl index 22c4550..a1ce860 100644 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ b/src/mainboard/lenovo/g505s/acpi/routing.asl @@ -90,7 +90,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/msi/ms7721/acpi/routing.asl b/src/mainboard/msi/ms7721/acpi/routing.asl index 0af6b42..5443dd5 100644 --- a/src/mainboard/msi/ms7721/acpi/routing.asl +++ b/src/mainboard/msi/ms7721/acpi/routing.asl @@ -71,7 +71,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl index 9a63d72..79ebef3 100644 --- a/src/mainboard/pcengines/apu1/acpi/routing.asl +++ b/src/mainboard/pcengines/apu1/acpi/routing.asl @@ -162,7 +162,7 @@ /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index f33fcf6..4764931 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -99,7 +99,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 4a89eb9..8532728 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -83,7 +83,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 6dc0346..6b6c28d 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -163,7 +163,7 @@ dev->path.pci.devfn &= ~0x7; dev->path.pci.devfn |= func; - /* is pcie device there */ + /* is PCIe device there */ if (pci_read_config32(dev, 0) == 0xFFFFFFFF) continue; diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 9bd9afc..70b83be 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -101,7 +101,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 33800ef..f4cd8f2 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -86,7 +86,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 9ceeca5..1508b06 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -91,7 +91,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 456fda6..ea64341 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -75,7 +75,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd2; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fd37d26..a7ad07e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -180,7 +180,7 @@ /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index d05e76b..75f179e 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -53,7 +53,7 @@ { printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events Disable pcie wake. */ + /* Configure events Disable PCIe wake. */ enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); disable_gpe(PME_B0_EN); diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 0687513..e82bec0 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -134,7 +134,7 @@ /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index b2467f9..372f527 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -106,7 +106,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b189a16..2c3d3a5 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -226,7 +226,7 @@ u8 PchDciEn; /* - * Pcie Root Port configuration: + * PCIe Root Port configuration: * each element of array corresponds to * respective PCIe root port. */ diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index d5f62f6..24e4cf1 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -88,7 +88,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 75a399f..8176b07 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -114,7 +114,7 @@ /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index f7652ee..3983962 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -166,7 +166,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index a6b0bdb..0ec0c05 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -138,7 +138,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 5c2b130..7c672b3 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -351,8 +351,8 @@ * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 * - * This check is done here instead of pcie driver - * because the pcie driver enable() handler is not + * This check is done here instead of PCIe driver + * because the PCIe driver enable() handler is not * called unless the device is enabled. */ if ((PCI_FUNC(dev->path.pci.devfn) == 0 || diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index a956398..a0422f2 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -137,7 +137,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index ba9f850..fc8e219 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -161,7 +161,7 @@ PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 3aca7bb..34c2537 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -114,7 +114,7 @@ u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Gerrit-Change-Number: 39101 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: nb/amd/agesa/family14/acpi: Fix comment
by HAOUAS Elyes (Code Review) 04 Mar '20

04 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38054 ) Change subject: nb/amd/agesa/family14/acpi: Fix comment ...................................................................... nb/amd/agesa/family14/acpi: Fix comment "amdfam10" is no more. Change-Id: Ibf4892bb4076eb88b864fc0e894b986bf6f6e5bf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38054/1 diff --git a/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl b/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl index fb33772..c1e4413 100644 --- a/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl +++ b/src/northbridge/amd/agesa/family14/acpi/thermal_mixin.asl @@ -25,7 +25,7 @@ * Scope (\_SB.PCI0) { * Device (K10M) { * Name (_ADR, 0x00180003) - * #include <northbridge/amd/amdfam10/thermal_mixin.asl> + * #include <northbridge/amd/agesa/family14/acpi/thermal_mixin.asl> * } * } * -- To view, visit https://review.coreboot.org/c/coreboot/+/38054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf4892bb4076eb88b864fc0e894b986bf6f6e5bf Gerrit-Change-Number: 38054 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: include/cpu/amd: Drop unused file
by HAOUAS Elyes (Code Review) 04 Mar '20

04 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38055 ) Change subject: include/cpu/amd: Drop unused file ...................................................................... include/cpu/amd: Drop unused file Change-Id: Iff14250e52854d598967cfd3cbc98061be06e581 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/include/cpu/amd/amdfam10_sysconf.h 1 file changed, 0 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38055/1 diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h deleted file mode 100644 index fc7b6bf..0000000 --- a/src/include/cpu/amd/amdfam10_sysconf.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_SYSCONF_H -#define AMDFAM10_SYSCONF_H - -#include "northbridge/amd/amdfam10/nums.h" - -#include <cpu/x86/msr.h> - -struct p_state_t { - unsigned int corefreq; - unsigned int power; - unsigned int transition_lat; - unsigned int busmaster_lat; - unsigned int control; - unsigned int status; -}; - -struct amdfam10_sysconf_t { - //ht - unsigned int hc_possible_num; - unsigned int pci1234[HC_POSSIBLE_NUM]; - unsigned int hcdn[HC_POSSIBLE_NUM]; - unsigned int hcid[HC_POSSIBLE_NUM]; //record ht chain type - unsigned int sbdn; - unsigned int sblk; - - unsigned int nodes; - unsigned int ht_c_num; // we only can have 32 ht chain at most - // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable - unsigned int ht_c_conf_bus[HC_NUMS]; - unsigned int io_addr_num; - unsigned int conf_io_addr[HC_NUMS]; - unsigned int conf_io_addrx[HC_NUMS]; - unsigned int mmio_addr_num; - unsigned int conf_mmio_addr[HC_NUMS*2]; // mem and pref mem - unsigned int conf_mmio_addrx[HC_NUMS*2]; - unsigned int segbit; - unsigned int hcdn_reg[HC_NUMS]; // it will be used by get_pci1234 - - // quad cores all cores in one node should be the same, and p0,..p5 - msr_t msr_pstate[NODE_NUMS * 5]; - unsigned int needs_update_pstate_msrs; - - unsigned int bsp_apicid; - int enabled_apic_ext_id; - unsigned int lift_bsp_apicid; - int apicid_offset; - - void *mb; // pointer for mb related struct - -}; - -extern struct amdfam10_sysconf_t sysconf; - -void get_bus_conf(void); -void get_pci1234(void); -void get_default_pci1234(int mb_hc_possible); - -extern u8 pirq_router_bus; - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff14250e52854d598967cfd3cbc98061be06e581 Gerrit-Change-Number: 38055 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/hatch/Kconfig: Add support for boot with tianocore payload
by Meera Ravindranath (Code Review) 04 Mar '20

04 Mar '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36067 ) Change subject: mainboard/hatch/Kconfig: Add support for boot with tianocore payload ...................................................................... mainboard/hatch/Kconfig: Add support for boot with tianocore payload Add new config and set the required GBB flags to support boot with tianocore payload. BUG=none TEST=Allows boot to tianocore on pressing Ctrl+L in depthcharge. Change-Id: I42fcf23523889d47f0490fbd662ca6b7587ab548 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/36067/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 004cc28..246e258 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -33,10 +33,18 @@ select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if BOARD_USES_TIANOCORE + select GBB_FLAG_ENABLE_ALTERNATE_OS if BOARD_USES_TIANOCORE select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH +config BOARD_USES_TIANOCORE + bool + default n + select USE_LEGACY_8254_TIMER + select USE_ACPI_PM_TIMER + config CHROMEOS_WIFI_SAR bool "Enable SAR options for Chrome OS build" depends on CHROMEOS -- To view, visit https://review.coreboot.org/c/coreboot/+/36067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42fcf23523889d47f0490fbd662ca6b7587ab548 Gerrit-Change-Number: 36067 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Remove misleading BUG: messages
by Wim Vervoorn (Code Review) 04 Mar '20

04 Mar '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38750 ) Change subject: soc/intel/skylake: Remove misleading BUG: messages ...................................................................... soc/intel/skylake: Remove misleading BUG: messages The skylake pch_log_rp_wake_source function causes a "BUG: pch_log_rp_wake_source requests hidden...." message for each root port not listed in the device tree. This is caused by the fact that the function tries to read all root ports possible on the Skylake PCH. This is required because of a flaw in the PCH. The issue is solved by using the 'pcidev_path_on_root' function instead of the one that is standard for the Skylake SoC. This routine doesn display the "BUG" messages. BUG=N/A TEST=build Change-Id: I6bc04e48e97b0a29aef8aa050d3aad116cff1a14 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/soc/intel/skylake/elog.c 1 file changed, 59 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/38750/1 diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 411b3e9..a3c8fc4 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -120,6 +120,41 @@ } #define RP_PME_STS_BIT (1 << 16) + +#if !defined(__SIMPLE_DEVICE__) +//#include <device/device.h> +#define RP_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#else +#define RP_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +#define RP_DEV_PCIE1 RP_DEV(PCIE, 0) +#define RP_DEV_PCIE2 RP_DEV(PCIE, 1) +#define RP_DEV_PCIE3 RP_DEV(PCIE, 2) +#define RP_DEV_PCIE4 RP_DEV(PCIE, 3) +#define RP_DEV_PCIE5 RP_DEV(PCIE, 4) +#define RP_DEV_PCIE6 RP_DEV(PCIE, 5) +#define RP_DEV_PCIE7 RP_DEV(PCIE, 6) +#define RP_DEV_PCIE8 RP_DEV(PCIE, 7) + +#define RP_DEV_PCIE9 RP_DEV(PCIE_1, 0) +#define RP_DEV_PCIE10 RP_DEV(PCIE_1, 1) +#define RP_DEV_PCIE11 RP_DEV(PCIE_1, 2) +#define RP_DEV_PCIE12 RP_DEV(PCIE_1, 3) +#define RP_DEV_PCIE13 RP_DEV(PCIE_1, 4) +#define RP_DEV_PCIE14 RP_DEV(PCIE_1, 5) +#define RP_DEV_PCIE15 RP_DEV(PCIE_1, 6) +#define RP_DEV_PCIE16 RP_DEV(PCIE_1, 7) + +#define RP_DEV_PCIE17 RP_DEV(PCIE_2, 0) +#define RP_DEV_PCIE18 RP_DEV(PCIE_2, 1) +#define RP_DEV_PCIE19 RP_DEV(PCIE_2, 2) +#define RP_DEV_PCIE20 RP_DEV(PCIE_2, 3) +#define RP_DEV_PCIE21 RP_DEV(PCIE_2, 4) +#define RP_DEV_PCIE22 RP_DEV(PCIE_2, 5) +#define RP_DEV_PCIE23 RP_DEV(PCIE_2, 6) +#define RP_DEV_PCIE24 RP_DEV(PCIE_2, 7) + static void pch_log_rp_wake_source(void) { size_t i, maxports; @@ -131,30 +166,30 @@ uint32_t val; struct pme_status_info pme_status_info[] = { - { PCH_DEV_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 }, - { PCH_DEV_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 }, - { PCH_DEV_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 }, - { PCH_DEV_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 }, - { PCH_DEV_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 }, - { PCH_DEV_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 }, - { PCH_DEV_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 }, - { PCH_DEV_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 }, - { PCH_DEV_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 }, - { PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 }, - { PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 }, - { PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 }, - { PCH_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 }, - { PCH_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 }, - { PCH_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 }, - { PCH_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 }, - { PCH_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 }, - { PCH_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 }, - { PCH_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 }, - { PCH_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 }, - { PCH_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 }, - { PCH_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 }, - { PCH_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 }, - { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, + { RP_DEV_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { RP_DEV_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { RP_DEV_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { RP_DEV_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { RP_DEV_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { RP_DEV_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { RP_DEV_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { RP_DEV_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { RP_DEV_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { RP_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { RP_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { RP_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 }, + { RP_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 }, + { RP_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 }, + { RP_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 }, + { RP_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 }, + { RP_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 }, + { RP_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 }, + { RP_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 }, + { RP_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 }, + { RP_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 }, + { RP_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 }, + { RP_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 }, + { RP_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, }; maxports = MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); -- To view, visit https://review.coreboot.org/c/coreboot/+/38750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bc04e48e97b0a29aef8aa050d3aad116cff1a14 Gerrit-Change-Number: 38750 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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