coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: util/chromeos: Add unzip as a dependency
by Mete Balci (Code Review) 03 Mar '20

03 Mar '20

Mete Balci has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31821 Change subject: util/chromeos: Add unzip as a dependency ...................................................................... util/chromeos: Add unzip as a dependency unzip might not be installed by default, so it is added as a dependency in crosfirmware script. Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Signed-off-by: Mete Balci <metebalci(a)gmail.com> --- M util/chromeos/crosfirmware.sh 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31821/1 diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 9d2ca84..0564106 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -37,6 +37,7 @@ exit_if_uninstalled "debugfs" "e2fsprogs" exit_if_uninstalled "parted" "parted" exit_if_uninstalled "curl" "curl" + exit_if_uninstalled "unzip" "unzip" } get_inventory() -- To view, visit https://review.coreboot.org/c/coreboot/+/31821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Gerrit-Change-Number: 31821 Gerrit-PatchSet: 1 Gerrit-Owner: Mete Balci <metebalci(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: clang-format: set to 80 chars per line
by Philipp Deppenwiese (Code Review) 03 Mar '20

03 Mar '20

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31947 Change subject: clang-format: set to 80 chars per line ...................................................................... clang-format: set to 80 chars per line Change-Id: If785ff5eb5cbadab92b0c2fed67a202b6d0ed5d4 Signed-off-by: zaolin <zaolin.daisuki(a)gmail.com> --- M .clang-format 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/31947/1 diff --git a/.clang-format b/.clang-format index d853f50..c292e2f 100644 --- a/.clang-format +++ b/.clang-format @@ -7,7 +7,7 @@ IndentCaseLabels: false SortIncludes: false ContinuationIndentWidth: 8 -ColumnLimit: 0 +ColumnLimit: 80 AlwaysBreakBeforeMultilineStrings: true AllowShortLoopsOnASingleLine: false AllowShortFunctionsOnASingleLine: false -- To view, visit https://review.coreboot.org/c/coreboot/+/31947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If785ff5eb5cbadab92b0c2fed67a202b6d0ed5d4 Gerrit-Change-Number: 31947 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: configure ethernet fsp param
by Wonkyu Kim (Code Review) 03 Mar '20

03 Mar '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39153 ) Change subject: soc/intel/tigerlake: configure ethernet fsp param ...................................................................... soc/intel/tigerlake: configure ethernet fsp param Configure ethernet based on board config BUG=none BRANCH=none TEST= build TGLRVP and check ethernet is disabled based on devicetree Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8 --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/39153/1 diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index d22cde0..b8a7d91 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,13 @@ sizeof(params->SataPortsDevSlp)); } + /* Lan */ + dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + if (!dev) + params->PchLanEnable = 0; + else + params->PchLanEnable = dev->enabled; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; -- To view, visit https://review.coreboot.org/c/coreboot/+/39153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8 Gerrit-Change-Number: 39153 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: add --output flag
by Marcello Sylvester Bauer (Code Review) 03 Mar '20

03 Mar '20

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38828 ) Change subject: util/ifdtool: add --output flag ...................................................................... util/ifdtool: add --output flag Add a optional commandline flag to define the filename of the resulting output file. If this flag is not defined, if will behave like before by creating a new file with a ".new" suffix. With this additional flag it is not necessary to move the output file at build-time, and the stdout print "Writing new image to <filename>" makes more sense for the build context. Change-Id: I824e94e93749f55c3576e4ee2f7804d855fefed2 Signed-off-by: Marcello Sylvester Bauer <sylv(a)sylv.io> --- M util/ifdtool/ifdtool.c 1 file changed, 30 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/38828/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 2bf2f4d..3cc5e15 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -854,17 +854,11 @@ static void write_image(const char *filename, char *image, int size) { - char new_filename[FILENAME_MAX]; // allow long file names int new_fd; - - // - 5: leave room for ".new\0" - strncpy(new_filename, filename, FILENAME_MAX - 5); - strncat(new_filename, ".new", FILENAME_MAX - strlen(filename)); - - printf("Writing new image to %s\n", new_filename); + printf("Writing new image to %s\n", filename); // Now write out new image - new_fd = open(new_filename, + new_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC | O_BINARY, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); if (new_fd < 0) { @@ -1429,6 +1423,7 @@ " -x | --extract: extract intel fd modules\n" " -i | --inject <region>:<module> inject file <module> into region <region>\n" " -n | --newlayout <filename> update regions using a flashrom layout file\n" + " -O | --output <filename> output filename\n" " -s | --spifreq <17|20|30|33|48|50> set the SPI frequency\n" " -D | --density <512|1|2|4|8|16|32|64> set chip density (512 in KByte, others in MByte)\n" " -C | --chip <0|1|2> select spi chip on which to operate\n" @@ -1460,6 +1455,7 @@ int mode_altmedisable = 0, altmedisable = 0; char *region_type_string = NULL, *region_fname = NULL; const char *layout_fname = NULL; + char *new_filename = NULL; int region_type = -1, inputfreq = 0; unsigned int new_density = 0; enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; @@ -1470,6 +1466,7 @@ {"extract", 0, NULL, 'x'}, {"inject", 1, NULL, 'i'}, {"newlayout", 1, NULL, 'n'}, + {"output", 1, NULL, 'O'}, {"spifreq", 1, NULL, 's'}, {"density", 1, NULL, 'D'}, {"chip", 1, NULL, 'C'}, @@ -1484,7 +1481,7 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "df:D:C:M:xi:n:s:p:eluvth?", + while ((opt = getopt_long(argc, argv, "df:D:C:M:xi:n:O:s:p:eluvth?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -1543,6 +1540,14 @@ exit(EXIT_FAILURE); } break; + case 'O': + new_filename = strdup(optarg); + if (!new_filename) { + fprintf(stderr, "No output filename specified\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + break; case 'D': mode_density = 1; new_density = strtoul(optarg, NULL, 0); @@ -1731,6 +1736,14 @@ close(bios_fd); + // generate new filename + if (new_filename == NULL) { + new_filename = (char *) malloc((strlen(filename)) * sizeof(char)); + // - 5: leave room for ".new\0" + strcpy(new_filename, filename); + strcat(new_filename, ".new"); + } + check_ifd_version(image, size); if (mode_dump) @@ -1746,32 +1759,32 @@ validate_layout(image, size); if (mode_inject) - inject_region(filename, image, size, region_type, + inject_region(new_filename, image, size, region_type, region_fname); if (mode_newlayout) - new_layout(filename, image, size, layout_fname); + new_layout(new_filename, image, size, layout_fname); if (mode_spifreq) - set_spi_frequency(filename, image, size, spifreq); + set_spi_frequency(new_filename, image, size, spifreq); if (mode_density) - set_chipdensity(filename, image, size, new_density); + set_chipdensity(new_filename, image, size, new_density); if (mode_em100) - set_em100_mode(filename, image, size); + set_em100_mode(new_filename, image, size); if (mode_locked) - lock_descriptor(filename, image, size); + lock_descriptor(new_filename, image, size); if (mode_unlocked) - unlock_descriptor(filename, image, size); + unlock_descriptor(new_filename, image, size); if (mode_altmedisable) { fpsba_t *fpsba = find_fpsba(image, size); fmsba_t *fmsba = find_fmsba(image, size); fpsba_set_altmedisable(fpsba, fmsba, altmedisable); - write_image(filename, image, size); + write_image(new_filename, image, size); } free(image); -- To view, visit https://review.coreboot.org/c/coreboot/+/38828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I824e94e93749f55c3576e4ee2f7804d855fefed2 Gerrit-Change-Number: 38828 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/tigerlake: Add memory configuration support for Jasper Lake
by Meera Ravindranath (Code Review) 03 Mar '20

03 Mar '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39135 ) Change subject: src/soc/tigerlake: Add memory configuration support for Jasper Lake ...................................................................... src/soc/tigerlake: Add memory configuration support for Jasper Lake BUG=none BRANCH=none TEST=Build and verify boot of WaddleDoo. Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/jsl_memcfg_init.h A src/soc/intel/tigerlake/jsl_memcfg_init.c 3 files changed, 305 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/39135/1 diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 56119f5..c85f9dc 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += espi.c romstage-y += gpio.c romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c +romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += jsl_memcfg_init.c romstage-y += reset.c ramstage-y += acpi.c diff --git a/src/soc/intel/tigerlake/include/soc/jsl_memcfg_init.h b/src/soc/intel/tigerlake/include/soc/jsl_memcfg_init.h new file mode 100644 index 0000000..e04ef85 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/jsl_memcfg_init.h @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright Intel Corporation 2020. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_ +#define _SOC_JASPERLAKE_MEMCFG_INIT_H_ + +#include <stddef.h> +#include <stdint.h> +#include <fsp/soc_binding.h> + +/* Number of dq bits controlled per dqs */ +#define DQ_BITS_PER_DQS 8 + +/* Number of memory DIMM slots available on Cannonlake board */ +#define NUM_DIMM_SLOT 4 + +/* + * Number of memory packages, where a "package" represents a 64-bit solution. + */ +#define DDR_NUM_PACKAGES 2 + +/* 64-bit Channel identification */ +enum { + DDR_CH0, + DDR_CH1, + DDR_NUM_CHANNELS +}; + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum mem_info_read_type { + NOT_EXISTING, /* No memory in this slot */ + READ_SMBUS, /* Read on-module spd by SMBUS. */ + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + +struct spd_info { + enum mem_info_read_type read_type; + union spd_data_by { + /* To read on-module spd when read_type is READ_SMBUS. */ + uint8_t spd_smbus_address; + + /* To identify spd file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory dq mapping information */ +struct jsl_mb_cfg { + /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + struct spd_info spd[NUM_DIMM_SLOT]; + + /* + * For each channel, there are 6 sets of DQ byte mappings, + * where each set has a package 0 and a package 1 value (package 0 + * represents the first 64-bit lpddr4 chip combination, and package 1 + * represents the second 64-bit lpddr4 chip combination). + * The first three sets are for CLK, CMD, and CTL. + * The fsp package actually expects 6 sets, even though the last 3 sets + * are not used in CNL. + * We let the meminit_lpddr4() routine take care of clearing the + * unused fields for the caller. + * Note that dq_map is only used by LPDDR; it does not need to be + * initialized for designs using DDR4. + */ + uint8_t dq_map[DDR_NUM_CHANNELS][6][DDR_NUM_PACKAGES]; + + /* + * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + * dqs_map is only used by LPDDR; same comments apply as for dq_map + * above. + */ + uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS]; + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + uint16_t rcomp_resistor[3]; + + /* + * Rcomp target values. These will typically be the following + * values for Cannon Lake : { 80, 40, 40, 40, 30 } + */ + uint16_t rcomp_targets[5]; + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + uint8_t dq_pins_interleaved; + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + uint8_t vref_ca_config; + + /* Early Command Training Enabled */ + uint8_t ect; + + /* Board type */ + uint8_t UserBd; +}; + +/* + * Initialize default memory configurations for CannonLake. + */ +void jasperlake_memcfg_init(FSP_M_CONFIG *mem_cfg, + const struct jsl_mb_cfg *jsl_cfg); + +#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */ diff --git a/src/soc/intel/tigerlake/jsl_memcfg_init.c b/src/soc/intel/tigerlake/jsl_memcfg_init.c new file mode 100644 index 0000000..c8e2c03 --- /dev/null +++ b/src/soc/intel/tigerlake/jsl_memcfg_init.c @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <assert.h> +#include <console/console.h> +#include <fsp/util.h> +#include <soc/jsl_memcfg_init.h> +#include <spd_bin.h> +#include <string.h> + +static void meminit_memcfg(FSP_M_CONFIG *mem_cfg, + const struct jsl_mb_cfg *board_cfg) +{ + /* + * DqByteMapChx expects 12 bytes of data, but the last 6 bytes + * are unused, so client passes in the relevant values and + * we null out the rest of the data. + */ + memset(&mem_cfg->DqByteMapCh0, 0, sizeof(mem_cfg->DqByteMapCh0)); + memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0], + sizeof(board_cfg->dq_map[DDR_CH0])); + + memset(&mem_cfg->DqByteMapCh1, 0, sizeof(mem_cfg->DqByteMapCh1)); + memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1], + sizeof(board_cfg->dq_map[DDR_CH1])); + + memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], + sizeof(board_cfg->dqs_map[DDR_CH0])); + memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], + sizeof(board_cfg->dqs_map[DDR_CH1])); + + memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, + sizeof(mem_cfg->RcompResistor)); + + /* Early cannonlake requires rcomp targets to be 0 */ + memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, + sizeof(mem_cfg->RcompTarget)); + + mem_cfg->UserBd = board_cfg->UserBd; + +} + +/* + * Initialize default memory settings using spd data contained in a buffer. + */ +static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, uint8_t mem_slot, + size_t spd_data_len, uintptr_t spd_data_ptr) +{ + static size_t last_set_spd_data_len = 0; + + assert(spd_data_ptr != 0 && spd_data_len != 0); + + if (last_set_spd_data_len != 0 && + last_set_spd_data_len != spd_data_len) + die("spd data length disparity among slots"); + + mem_cfg->MemorySpdDataLen = spd_data_len; + last_set_spd_data_len = spd_data_len; + + switch (mem_slot) { + case 0: + mem_cfg->MemorySpdPtr00 = spd_data_ptr; + break; + case 1: + mem_cfg->MemorySpdPtr01 = spd_data_ptr; + break; + case 2: + mem_cfg->MemorySpdPtr10 = spd_data_ptr; + break; + case 3: + mem_cfg->MemorySpdPtr11 = spd_data_ptr; + break; + default: + die("nonexistent memory slot"); + } + printk(BIOS_INFO, "memory slot: %d configuration done.\n", mem_slot); +} + +/* + * Initialize default memory settings using the spd file specified by + * spd_index. The spd_index is an index into the SPD_SOURCES array defined + * in spd/Makefile.inc. + */ +static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, + int spd_index, uint8_t mem_slot) +{ + static size_t spd_data_len; + static uintptr_t spd_data_ptr; + static int last_spd_index; + + assert(mem_slot < NUM_DIMM_SLOT); + + if ((spd_data_ptr == 0) || (last_spd_index != spd_index)) { + struct region_device spd_rdev; + + printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); + last_spd_index = spd_index; + print_spd_info((unsigned char *)spd_data_ptr); + } + + meminit_spd_data(mem_cfg, mem_slot, spd_data_len, spd_data_ptr); +} + +/* Initialize onboard memory configurations for CannonLake */ +void jasperlake_memcfg_init(FSP_M_CONFIG *mem_cfg, + const struct jsl_mb_cfg *jsl_cfg) +{ + const struct spd_info *spdi; + + /* Early Command Training Enabled */ + mem_cfg->ECT = jsl_cfg->ect; + mem_cfg->DqPinsInterleaved = jsl_cfg->dq_pins_interleaved; + mem_cfg->CaVrefConfig = jsl_cfg->vref_ca_config; + + for (int i = 0; i < NUM_DIMM_SLOT; i++) { + spdi = &(jsl_cfg->spd[i]); + switch (spdi->read_type) { + case NOT_EXISTING: + break; + + case READ_SMBUS: + mem_cfg->SpdAddressTable[i] = + spdi->spd_spec.spd_smbus_address; + break; + + case READ_SPD_CBFS: + mem_cfg->SpdAddressTable[i] = 0; + meminit_cbfs_spd_index(mem_cfg, + spdi->spd_spec.spd_index, i); + break; + + case READ_SPD_MEMPTR: + meminit_spd_data(mem_cfg, i, + spdi->spd_spec.spd_data_ptr_info.spd_data_len, + spdi->spd_spec.spd_data_ptr_info.spd_data_ptr); + break; + + default: + die("no valid way to read mem info"); + } + + meminit_memcfg(mem_cfg, jsl_cfg); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85 Gerrit-Change-Number: 39135 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Kconfig: Have GDB_STUB depend on DRIVERS_UART
by Arthur Heymans (Code Review) 03 Mar '20

03 Mar '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36604 ) Change subject: Kconfig: Have GDB_STUB depend on DRIVERS_UART ...................................................................... Kconfig: Have GDB_STUB depend on DRIVERS_UART There is no reason to hide the GDB_STUB option when SERIAL_CONSOLE is set. Change-Id: Icbf9a1ac0e617939cafa3d66774bbd467dc01cbc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/36604/1 diff --git a/src/Kconfig b/src/Kconfig index 793927a..ad6c18a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -746,7 +746,7 @@ config GDB_STUB bool "GDB debugging support" default n - depends on CONSOLE_SERIAL + depends on DRIVERS_UART help If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details. -- To view, visit https://review.coreboot.org/c/coreboot/+/36604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbf9a1ac0e617939cafa3d66774bbd467dc01cbc Gerrit-Change-Number: 36604 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: i82371eb: Roll 82093aa init into isa_init()
by Keith Hui (Code Review) 03 Mar '20

03 Mar '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38599 ) Change subject: i82371eb: Roll 82093aa init into isa_init() ...................................................................... i82371eb: Roll 82093aa init into isa_init() This allows reuse of dev and reg32 already available, and converting the block from #if to simple if. Change-Id: I7a56f5a170986bbdf3c0c87eb5ead838ad55c659 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/isa.c 1 file changed, 22 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38599/1 diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 1442470..310a9fe 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -30,37 +30,6 @@ #include "i82371eb.h" #include "chip.h" -#if CONFIG(IOAPIC) -static void enable_intel_82093aa_ioapic(void) -{ - u16 reg16; - u32 reg32; - u8 ioapic_id = 2; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - struct device *dev; - - dev = dev_find_device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_ISA, 0); - - /* Enable IOAPIC. */ - reg16 = pci_read_config16(dev, XBCS); - reg16 |= (1 << 8); /* APIC Chip Select */ - pci_write_config16(dev, XBCS, reg16); - - /* Set the IOAPIC ID. */ - *ioapic_index = 0; - *ioapic_data = ioapic_id << 24; - - /* Read back and verify the IOAPIC ID. */ - *ioapic_index = 0; - reg32 = (*ioapic_data >> 24) & 0x0f; - printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32); - if (reg32 != ioapic_id) - die("IOAPIC error!\n"); -} -#endif - static void isa_init(struct device *dev) { u32 reg32; @@ -91,7 +60,6 @@ /* Initialize ISA DMA. */ isa_dma_init(); -#if CONFIG(IOAPIC) /* * Unlike most other southbridges the 82371EB doesn't have a built-in * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs @@ -100,8 +68,28 @@ * Thus, we can/must only enable the IOAPIC if it actually exists, * i.e. the respective mainboard does "select IOAPIC". */ - enable_intel_82093aa_ioapic(); -#endif + if (CONFIG(IOAPIC)) { + u16 reg16; + u8 ioapic_id = 2; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + + /* Enable IOAPIC. */ + reg16 = pci_read_config16(dev, XBCS); + reg16 |= (1 << 8); /* APIC Chip Select */ + pci_write_config16(dev, XBCS, reg16); + + /* Set the IOAPIC ID. */ + *ioapic_index = 0; + *ioapic_data = ioapic_id << 24; + + /* Read back and verify the IOAPIC ID. */ + *ioapic_index = 0; + reg32 = (*ioapic_data >> 24) & 0x0f; + printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32); + if (reg32 != ioapic_id) + die("IOAPIC error!\n"); + } } static void sb_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/38599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a56f5a170986bbdf3c0c87eb5ead838ad55c659 Gerrit-Change-Number: 38599 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: sb/intel/i82371eb: Add support for reconfiguring GPO22/23
by Keith Hui (Code Review) 03 Mar '20

03 Mar '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38352 ) Change subject: sb/intel/i82371eb: Add support for reconfiguring GPO22/23 ...................................................................... sb/intel/i82371eb: Add support for reconfiguring GPO22/23 XOE# and XDIR# can be used as GPOs 23/22 if X-Bus functionality is not required. Turns out asus/p2b-ls is using them to control termination for the onboard SCSI buses. Add support to allow this reconfiguration. Change-Id: I2dab6fafbd67a98ed1cac1ffcf9352be4a87c3e9 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b-ls/devicetree.cb M src/southbridge/intel/i82371eb/chip.h M src/southbridge/intel/i82371eb/isa.c 3 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38352/1 diff --git a/src/mainboard/asus/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b-ls/devicetree.cb index a9901b4..5e55278 100644 --- a/src/mainboard/asus/p2b-ls/devicetree.cb +++ b/src/mainboard/asus/p2b-ls/devicetree.cb @@ -8,6 +8,10 @@ device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge + register "gpo" = "0x7fbfb9ff" + register "gpo22_enable" = "1" + register "lid_polarity" = "1" + register "thrm_polarity" = "1" device pci 4.0 on # ISA bridge chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) device pnp 3f0.0 on # Floppy diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h index 28975a2..5b23ab1 100644 --- a/src/southbridge/intel/i82371eb/chip.h +++ b/src/southbridge/intel/i82371eb/chip.h @@ -28,6 +28,10 @@ int ide1_drive1_udma33_enable:1; int ide_legacy_enable:1; int usb_enable:1; + int gpo22_enable:1; /* GPO22/GPO23 (1) vs. XDIR#/XOE# (0) */ + int gpo22:1; + int gpo23:1; + int pad:5; /* acpi */ u32 gpo; /* gpio output default */ u8 lid_polarity; diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index bb88f7d..fd63440 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -28,6 +28,7 @@ #include <arch/acpigen.h> #endif #include "i82371eb.h" +#include "chip.h" #if CONFIG(IOAPIC) static void enable_intel_82093aa_ioapic(void) @@ -63,6 +64,7 @@ static void isa_init(struct device *dev) { u32 reg32; + struct southbridge_intel_i82371eb_config *sb = dev->chip_info; /* Initialize the real time clock (RTC). */ cmos_init(0); @@ -77,9 +79,13 @@ /* * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) * bus, which is a subset of ISA. We select the full ISA bus here. + * Some boards use GPO22/23. That will be taken care of as well. */ reg32 = pci_read_config32(dev, GENCFG); - reg32 |= ISA; /* Select ISA, not EIO. */ + + reg32 |= ISA | /* Select ISA, not EIO. */ + (sb->gpo22_enable << 28); /* Select GPO22/23 if configured. */ + pci_write_config16(dev, GENCFG, reg32); /* Initialize ISA DMA. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dab6fafbd67a98ed1cac1ffcf9352be4a87c3e9 Gerrit-Change-Number: 38352 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

6 20

Change in coreboot[master]: cpu/intel/slot_1: Cache romstage XIP execution
by Arthur Heymans (Code Review) 03 Mar '20

03 Mar '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37164 ) Change subject: cpu/intel/slot_1: Cache romstage XIP execution ...................................................................... cpu/intel/slot_1: Cache romstage XIP execution Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/slot_1/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37164/1 diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 7919974..a8d90e8 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -27,6 +27,7 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE + select SETUP_XIP_CACHE config DCACHE_RAM_BASE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/37164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f Gerrit-Change-Number: 37164 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/dedede: Add Jasper Lake memory initialization support
by Meera Ravindranath (Code Review) 03 Mar '20

03 Mar '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39136 ) Change subject: mb/google/dedede: Add Jasper Lake memory initialization support ...................................................................... mb/google/dedede: Add Jasper Lake memory initialization support Update memory parameters based on memory type supported by dedede 1. Update dq/dqs mappings 2. Update spd data for Micron Memory 3. Add SPD data binary files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= Build dedede, flash and boot to kernel Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/romstage.c A src/mainboard/google/dedede/spd/Makefile.inc A src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex A src/mainboard/google/dedede/spd/empty.spd.hex M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/dedede/variants/waddledoo/Makefile.inc A src/mainboard/google/dedede/variants/waddledoo/memory.c 9 files changed, 230 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/39136/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 3eddabc..43c104b 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -13,6 +13,7 @@ select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE + select GENERIC_SPD_BIN if BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -68,4 +69,8 @@ default "dedede" if BOARD_GOOGLE_DEDEDE default "waddledoo" if BOARD_GOOGLE_WADDLEDOO +config DIMM_SPD_SIZE + int + default 512 + endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index 2be3feb..9af93dd 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -13,6 +13,8 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c subdirs-y += variants/baseboard +subdirs-y += spd + CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index bba6e1a..ce014bb 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -1,15 +1,24 @@ /* * This file is part of the coreboot project. * - * Copyright 2020 The coreboot project Authors. + * Copyright (C) 2020 Intel Corporation. * - * SPDX-License-Identifier: GPL-2.0-or-later - */ + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ -#include <fsp/api.h> +#include <baseboard/variants.h> +#include <soc/jsl_memcfg_init.h> #include <soc/romstage.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { - /* ToDo : Fill FSP-M memory params */ + jasperlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); } + diff --git a/src/mainboard/google/dedede/spd/Makefile.inc b/src/mainboard/google/dedede/spd/Makefile.inc new file mode 100644 index 0000000..97a4dfd --- /dev/null +++ b/src/mainboard/google/dedede/spd/Makefile.inc @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifneq ($(SPD_SOURCES),) +SPD_BIN = $(obj)/spd.bin + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd +endif diff --git a/src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex b/src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex new file mode 100644 index 0000000..71e5456 --- /dev/null +++ b/src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dedede/spd/empty.spd.hex b/src/mainboard/google/dedede/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/google/dedede/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 32b2c8b..4987bb2 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -27,5 +27,5 @@ * @return 0 on success or negative integer for errors. */ int board_info_get_fw_config(uint32_t *fw_config); - +const struct jsl_mb_cfg *variant_memcfg_config(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc new file mode 100644 index 0000000..4f3b453 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2020 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = empty # 0b000 +SPD_SOURCES += empty # 1b001 +SPD_SOURCES += Micron_MT53E512M32D2NP_2GB + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c + +smm-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory.c b/src/mainboard/google/dedede/variants/waddledoo/memory.c new file mode 100644 index 0000000..b00ab86 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/memory.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <gpio.h> +#include <soc/jsl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct jsl_mb_cfg baseboard_memcfg_cfg = { + /* Access memory info through SMBUS. */ + + .spd[0] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0x2} + }, + .spd[2] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0x2} + }, + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x00, 0x0}, + {0x00, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {1, 3, 0, 2, 7, 5, 4, 6}, + .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 5, 7, 6}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = {80, 40, 40, 40, 30}, + + /* Baseboard is an interleaved design */ + .dq_pins_interleaved = 0, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Disable Early Command Training */ + .ect = 1, + + /* User Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct jsl_mb_cfg *variant_memcfg_config(void) +{ + return &baseboard_memcfg_cfg; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e Gerrit-Change-Number: 39136 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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