coreboot-gerrit February 2020

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Change in coreboot[master]: sb/intel/i82371eb: Enable upper NVRAM bank
by Keith Hui (Code Review) 03 Mar '20

03 Mar '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38368 ) Change subject: sb/intel/i82371eb: Enable upper NVRAM bank ...................................................................... sb/intel/i82371eb: Enable upper NVRAM bank Change-Id: I9ad127ca4394e27fc055ddf03012a195cb03bd94 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/bootblock.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/38368/1 diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 711b317..2688e37 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -61,4 +61,9 @@ reg16 |= LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB; reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ pci_write_config16(dev, XBCS, reg16); + + /* Enable (RTC and) upper NVRAM bank. */ + pci_write_config8(dev, RTCCFG, + RTC_POS_DECODE | UPPER_RAM_EN | RTC_ENABLE); + } -- To view, visit https://review.coreboot.org/c/coreboot/+/38368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad127ca4394e27fc055ddf03012a195cb03bd94 Gerrit-Change-Number: 38368 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/tigerlake: Correct FSP log interface
by Wonkyu Kim (Code Review) 03 Mar '20

03 Mar '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39167 ) Change subject: soc/tigerlake: Correct FSP log interface ...................................................................... soc/tigerlake: Correct FSP log interface BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39167/1 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index ed6aa5a..043a257 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -61,7 +61,8 @@ /* UART Debug Log */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : \ + DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; m_cfg->PcdIsaSerialUartBase = 0x0; m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/39167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 Gerrit-Change-Number: 39167 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

7 13

Change in coreboot[master]: vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT option
by Joel Kitching (Code Review) 03 Mar '20

03 Mar '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38780 ) Change subject: vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT option ...................................................................... vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT option With CL:1940398, this option is no longer needed. Recovery requests are not cleared until kernel verification stage is reached. If the FSP triggers any reboots, recovery requests will be preserved. In particular: - Manual requests will be preserved via recovery switch state, whose behaviour is modified in CB:XXXXXX. - Other recovery requests will remain in nvdata across reboot. BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I52d17a3c6730be5c04c3c0ae020368d11db6ca3c Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/Kconfig M src/security/vboot/bootmode.c M src/security/vboot/misc.h M src/security/vboot/vbnv.c M src/security/vboot/vbnv.h M src/security/vboot/vboot_logic.c M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 12 files changed, 2 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/38780/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ea70e65..54e88dd 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -156,14 +156,6 @@ reused by the succeeding stage. This is useful if a RAM space is too small to fit both the verstage and the succeeding stage. -config VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT - bool - default n - help - This option ensures that the recovery request is not lost because of - reboots caused after vboot verification is run. e.g. reboots caused by - FSP components on Intel platforms. - config VBOOT_MUST_REQUEST_DISPLAY bool default y if VGA_ROM_RUN diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 61b3d76..5f15790 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -50,62 +50,21 @@ return sd->recovery_reason; } -void vboot_save_recovery_reason_vbnv(void) -{ - if (!CONFIG(VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT)) - return; - - int reason = vboot_get_recovery_reason_shared_data(); - if (!reason) - return; - - set_recovery_mode_into_vbnv(reason); -} - -static void vboot_clear_recovery_reason_vbnv(void *unused) -{ - if (!CONFIG(VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT)) - return; - - set_recovery_mode_into_vbnv(0); -} - -/* - * Recovery reason stored in VBNV needs to be cleared before the state of VBNV - * is backed-up anywhere or jumping to the payload (whichever occurs - * first). Currently, vbnv_cmos.c backs up VBNV on POST_DEVICE. Thus, we need to - * make sure that the stored recovery reason is cleared off before that - * happens. - * IMPORTANT: Any reboot occurring after BS_DEV_INIT state will cause loss of - * recovery reason on reboot. Until now, we have seen reboots occurring on x86 - * only in FSP stages which run before BS_DEV_INIT. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, - vboot_clear_recovery_reason_vbnv, NULL); - /* * vb2_check_recovery_request looks up different components to identify if there * is a recovery request and returns appropriate reason code: * 1. Checks if recovery mode is initiated by EC. If yes, returns * VB2_RECOVERY_RO_MANUAL. - * 2. Checks if recovery request is present in VBNV and returns the code read - * from it. - * 3. Checks if vboot verification is done. If yes, return the reason code from + * 2. Checks if vboot verification is done. If yes, return the reason code from * shared data. - * 4. If nothing applies, return 0 indicating no recovery request. + * 3. If nothing applies, return 0 indicating no recovery request. */ int vboot_check_recovery_request(void) { - int reason = 0; - /* EC-initiated recovery. */ if (get_recovery_mode_switch()) return VB2_RECOVERY_RO_MANUAL; - /* Recovery request in VBNV. */ - if ((reason = get_recovery_mode_from_vbnv()) != 0) - return reason; - /* Identify if vboot verification is already complete. */ if (vboot_logic_executed()) return vboot_get_recovery_reason_shared_data(); diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 2d5b084..c629ca5 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -52,11 +52,6 @@ int vboot_locate_firmware(struct vb2_context *ctx, struct region_device *fw); /* - * Source: security/vboot/bootmode.c - */ -void vboot_save_recovery_reason_vbnv(void); - -/* * The stage loading code is compiled and entered from multiple stages. The * helper functions below attempt to provide more clarity on when certain * code should be called. They are implemented inline for better compile-time diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index be598ac..a5a7806 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -101,26 +101,6 @@ vbnv_initialized = 0; } -/* Save a recovery reason into VBNV. */ -void set_recovery_mode_into_vbnv(int recovery_reason) -{ - uint8_t vbnv_copy[VBOOT_VBNV_BLOCK_SIZE]; - - read_vbnv(vbnv_copy); - - vbnv_copy[RECOVERY_OFFSET] = recovery_reason; - vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); - - save_vbnv(vbnv_copy); -} - -/* Read the recovery reason from VBNV. */ -int get_recovery_mode_from_vbnv(void) -{ - vbnv_setup(); - return vbnv[RECOVERY_OFFSET]; -} - /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void) { diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index a2f0b4c..7d288d5 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -23,8 +23,6 @@ void save_vbnv(const uint8_t *vbnv_copy); int verify_vbnv(uint8_t *vbnv_copy); void regen_vbnv_crc(uint8_t *vbnv_copy); -int get_recovery_mode_from_vbnv(void); -void set_recovery_mode_into_vbnv(int recovery_reason); /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void); diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index eabf8f7..465c85b 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -429,8 +429,5 @@ vboot_is_firmware_slot_a(ctx) ? 'A' : 'B'); verstage_main_exit: - /* Save recovery reason in case of unexpected reboots on x86. */ - vboot_save_recovery_reason_vbnv(); - timestamp_add_now(TS_END_VBOOT); } diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index c3fcad9..7d69a92 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -93,7 +93,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0d69da2..6c90294 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -113,7 +113,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d098785..b68e93d 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -260,7 +260,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 15e895f..210fd0d 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -165,7 +165,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 6277cea..7382df0 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -93,7 +93,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cef1fd0..56a0d74 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -189,7 +189,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -- To view, visit https://review.coreboot.org/c/coreboot/+/38780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52d17a3c6730be5c04c3c0ae020368d11db6ca3c Gerrit-Change-Number: 38780 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: Signed-off-by: mirek190 <mirek190@gmail.com>
by Miroslaw Kocur (Code Review) 02 Mar '20

02 Mar '20

Miroslaw Kocur has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38909 ) Change subject: Signed-off-by: mirek190 <mirek190(a)gmail.com> ...................................................................... Signed-off-by: mirek190 <mirek190(a)gmail.com> Attempt to add a nwe device - etab_pro tablet based on GLK. Change-Id: I63b9129a419facbcd2ca4819ba5946c40d7d5498 --- A configs/config.glk_etab_pro M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/chromeos.fmd M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/octopus/variants/baseboard/gpio.c M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 10 files changed, 601 insertions(+), 364 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/38909/1 diff --git a/configs/config.glk_etab_pro b/configs/config.glk_etab_pro new file mode 100644 index 0000000..558e788 --- /dev/null +++ b/configs/config.glk_etab_pro @@ -0,0 +1,10 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_OCTOPUS=y +CONFIG_NEED_LBP2=y +CONFIG_LBP2_FMAP_NAME="SIGN_CSE" +CONFIG_LBP2_FROM_IFWI=y +CONFIG_NEED_IFWI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_FMDFILE="src/mainboard/google/octopus/chromeos.fmd" +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/intel/GLK/etabpro/flashregion_1_bios.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/intel/GLK/etabpro/flashregion_0_flashdescriptor.bin" diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 3139716..f613b43 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -2,7 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS def_bool n select SOC_INTEL_GLK - select BOARD_ROMSIZE_KB_16384 + select BOARD_ROMSIZE_KB_8192 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 @@ -17,7 +17,6 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE - select MAINBOARD_HAS_CHROMEOS select SOC_ESPI select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 @@ -26,25 +25,11 @@ if BOARD_GOOGLE_BASEBOARD_OCTOPUS -config CHROMEOS_WIFI_SAR - bool - default y if CHROMEOS - select DSAR_ENABLE - select SAR_ENABLE - select USE_SAR - select GEO_SAR_ENABLE config BASEBOARD_OCTOPUS_LAPTOP def_bool n select SYSTEM_TYPE_LAPTOP -config CHROMEOS - bool - default y - select EC_GOOGLE_CHROMEEC_SWITCHES - select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - select VBOOT_LID_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index 332465a..0eccc4d 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -1,56 +1,23 @@ -FLASH 16M { - WP_RO@0x0 0x400000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x1ff000 - RO_VPD(PRESERVE)@0x200000 0x4000 - RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0x1f8000 - GBB@0x1f9000 0x3000 - } - } - MISC_RW@0x400000 0x30000 { - RW_PRESERVE(PRESERVE) { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 +FLASH 8M { + SI_DESC 0x1000 + SI_BIOS { + IFWI 0x2ff000 + OBBP { + FMAP 0x1000 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 } + CONSOLE 0x20000 + COREBOOT(CBFS) + SIGN_CSE 0x2000 + BIOS_UNUSABLE 0x4000 } - RW_ELOG(PRESERVE)@0x21000 0x3000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 - FPF_STATUS@0x2f000 0x1000 } - RW_SECTION_A@0x430000 0x480000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x46ffc0 - RW_FWID_A@0x47ffc0 0x40 + SI_DEVICEEXT 0x101000 { + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 } - RW_SECTION_B@0x8b0000 0x480000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x46ffc0 - RW_FWID_B@0x47ffc0 0x40 - } - SMMSTORE(PRESERVE)@0xd30000 0x40000 - RW_LEGACY(CBFS)@0xd70000 0x1c0000 - BIOS_UNUSABLE@0xf30000 0x4f000 - DEVICE_EXTENSION@0xf7f000 0x80000 - # Currently, it is required that the BIOS region be a multiple of 8KiB. - # This is required so that the recovery mechanism can find SIGN_CSE - # region aligned to 4K at the center of BIOS region. Since the - # descriptor at the beginning uses 4K and BIOS starts at an offset of - # 4K, a hole of 4K is created towards the end of the flash to compensate - # for the size requirement of BIOS region. - # FIT tool thus creates descriptor with following regions: - # Descriptor --> 0 to 4K - # BIOS --> 4K to 0xf7f000 - # Device ext --> 0xf7f000 to 0xfff000 - UNUSED_HOLE@0xfff000 0x1000 } + diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 8f85070..e132f14 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -110,16 +110,16 @@ device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 off end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit + device pci 02.0 off end # - Gen + device pci 03.0 off end # - Iunit chip drivers/intel/wifi register "wake" = "GPE0A_CNVI_PME_STS" device pci 0c.0 on end # - CNVi end - device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC - device pci 0d.2 on end # - Fast SPI - device pci 0d.3 on end # - Shared SRAM + device pci 0d.0 off end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 off end # - Fast SPI + device pci 0d.3 off end # - Shared SRAM device pci 0e.0 on chip drivers/generic/max98357a register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" @@ -128,18 +128,18 @@ end end # - Audio device pci 0f.0 on end # - Heci1 - device pci 0f.1 on end # - Heci2 - device pci 0f.2 on end # - Heci3 + device pci 0f.1 off end # - Heci2 + device pci 0f.2 off end # - Heci3 device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA + device pci 12.0 on end # - SATA device pci 13.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW3_11" device pci 00.0 on end end end # - PCIe-A 0 Onboard M2 Slot(Wifi) - device pci 13.1 off end # - PCIe-A 1 - device pci 13.2 off end # - PCIe-A 2 + device pci 13.1 on end # - PCIe-A 1 + device pci 13.2 on end # - PCIe-A 2 device pci 13.3 off end # - PCIe-A 3 device pci 14.0 off end # - PCIe-B 0 device pci 14.1 off end # - PCIe-B 1 @@ -231,19 +231,19 @@ end end end # - XHCI - device pci 15.1 on end # - XDCI + device pci 15.1 off end # - XDCI device pci 16.0 on end # - I2C 0 - device pci 16.1 off end # - I2C 1 - device pci 16.2 off end # - I2C 2 - device pci 16.3 off end # - I2C 3 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 device pci 17.0 on end # - I2C 4 device pci 17.1 on end # - I2C 5 device pci 17.2 on end # - I2C 6 - device pci 17.3 off end # - I2C 7 + device pci 17.3 on end # - I2C 7 device pci 18.0 on end # - UART 0 - device pci 18.1 off end # - UART 1 + device pci 18.1 on end # - UART 1 device pci 18.2 on end # - UART 2 - device pci 18.3 off end # - UART 3 + device pci 18.3 on end # - UART 3 device pci 19.0 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" @@ -252,11 +252,11 @@ device spi 0 on end end end # - GSPI 0 - device pci 19.1 off end # - SPI 1 + device pci 19.1 on end # - SPI 1 device pci 19.2 on end # - SPI 2 - device pci 1a.0 on end # - PWM + device pci 1a.0 off end # - PWM device pci 1c.0 on end # - eMMC - device pci 1e.0 off end # - SDIO + device pci 1e.0 on end # - SDIO device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 6f68522..ed4892e 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -25,267 +25,225 @@ */ static const struct pad_config gpio_table[] = { /* NORTHWEST COMMUNITY GPIOS */ - PAD_NC(GPIO_0, DN_20K), /* TCK -- debug header NC */ - PAD_NC(GPIO_1, DN_20K), /* TRST_B -- debug header NC */ - PAD_NC(GPIO_2, UP_20K), /* TMS -- debug header NC */ - PAD_NC(GPIO_3, UP_20K), /* TDI -- debug header NC */ - PAD_NC(GPIO_4, UP_20K), /* TDO -- debug header NC */ - PAD_NC(GPIO_5, UP_20K), /* JTAGX -- unused */ - PAD_NC(GPIO_6, UP_20K), /* CX_PREQ_B -- debug header NC */ - PAD_NC(GPIO_7, UP_20K), /* CX_PRDY_B -- debug header NC */ - PAD_NC(GPIO_8, DN_20K), /* TRACE_0_CLK_VNN -- debug header NC */ - PAD_NC(GPIO_9, DN_20K), /* TRACE_0_DATA0_VNN -- debug header NC */ - PAD_NC(GPIO_10, DN_20K), /* TRACE_0_DATA1_VNN -- debug header NC */ - PAD_NC(GPIO_11, DN_20K), /* TRACE_0_DATA2_VNN -- debug header NC */ - PAD_NC(GPIO_12, DN_20K), /* TRACE_0_DATA3_VNN -- debug header NC */ - PAD_NC(GPIO_13, DN_20K), /* TRACE_0_DATA4_VNN -- debug header NC */ - PAD_NC(GPIO_14, DN_20K), /* TRACE_0_DATA5_VNN -- debug header NC */ - PAD_NC(GPIO_15, DN_20K), /* TRACE_0_DATA6_VNN -- debug header NC */ - PAD_NC(GPIO_16, DN_20K), /* TRACE_0_DATA7_VNN -- debug header NC */ - PAD_NC(GPIO_17, UP_20K), /* DBG_PTI_CLK_1 -- debug header NC */ - PAD_NC(GPIO_18, UP_20K), /* DBG_PTI_DATA_8 -- debug header NC */ - PAD_NC(GPIO_19, UP_20K), /* DBG_PTI_DATA_9 -- debug header NC */ - PAD_NC(GPIO_20, UP_20K), /* DBG_PTI_DATA_10 -- debug header NC */ - PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ - PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ - PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ - PAD_NC(GPIO_24, UP_20K), /* TRACE_1_DATA6_VNN -- debug header NC */ - PAD_NC(GPIO_25, UP_20K), /* TRACE_1_DATA7_VNN -- debug header NC */ - PAD_NC(GPIO_26, DN_20K), /* TRACE_2_CLK_VNN -- debug header NC */ - PAD_NC(GPIO_27, DN_20K), /* TRACE_2_DATA0_VNN -- debug header NC */ - PAD_NC(GPIO_28, DN_20K), /* TRACE_2_DATA1_VNN 0-- debug header NC */ - PAD_NC(GPIO_29, DN_20K), /* TRACE_2_DATA2_VNN -- debug header NC */ - PAD_NC(GPIO_30, DN_20K), /* TRACE_2_DATA3_VNN -- debug header NC */ - PAD_NC(GPIO_31, DN_20K), /* TRACE_2_DATA4_VNN -- debug header NC */ - PAD_NC(GPIO_32, DN_20K), /* TRACE_2_DATA5_VNN -- debug header NC */ - PAD_NC(GPIO_33, DN_20K), /* TRACE_2_DATA6_VNN -- debug header NC */ - PAD_NC(GPIO_34, DN_20K), /* TRACE_2_DATA7_VNN -- debug header NC */ - PAD_NC(GPIO_35, UP_20K), /* TRACE_3_CLK_VNN -- debug header NC */ - PAD_NC(GPIO_36, UP_20K), /* TRACE_3_DATA0_VNN -- debug header NC */ - PAD_NC(GPIO_37, UP_20K), /* TRACE_3_DATA1_VNN -- debug header NC */ - PAD_NC(GPIO_38, UP_20K), /* TRACE_3_DATA2_VNN -- debug header NC */ - PAD_NC(GPIO_39, UP_20K), /* TRACE_3_DATA3_VNN -- unused */ - PAD_NC(GPIO_40, UP_20K), /* TRACE_3_DATA4_VNN -- unused */ - PAD_NC(GPIO_41, DN_20K), /* TRACE_3_DATA5_VNN -- unused */ - PAD_NC(GPIO_42, DN_20K), /* GP_INTD_DSI_TE1 -- unused */ - PAD_NC(GPIO_43, DN_20K), /* GP_INTD_DSI_TE2 -- debug header NC */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ - PAD_NC(GPIO_46, DN_20K), /* DSI_I2C_SDA -- unused */ - PAD_NC(GPIO_47, DN_20K), /* DSI_I2C_SCL -- unused */ - - /* PMC stays active in suspend so disable standby for these pins */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PMC_I2C_SDA */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PMC_I2C_SCL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SCL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ - PAD_NC(GPIO_54, UP_20K), /* LPSS_I2C2_SDA -- unused */ - PAD_NC(GPIO_55, UP_20K), /* LPSS_I2C2_SCL -- unused */ - PAD_NC(GPIO_56, UP_20K), /* LPSS_I2C3_SDA -- debug header NC */ - PAD_NC(GPIO_57, UP_20K), /* LPSS_I2C2_SCL -- debug header NC */ - PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA -- unused */ - PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL -- unused */ - PAD_NC(GPIO_60, UP_20K), /* LPSS_UART0_RXD -- debug header NC */ - PAD_NC(GPIO_61, UP_20K), /* LPSS_UART0_TXD -- debug header NC */ - PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ - PAD_NC(GPIO_66, UP_20K), /* UART2-RTS_B -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */ - PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */ - PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */ - PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */ - PAD_NC(GPIO_72, DN_20K), /* PMC_SPI_TXD -- unused */ - PAD_NC(GPIO_73, DN_20K), /* PMC_SPI_CLK -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ - PAD_NC(GPIO_211, UP_20K), /* EMMC_RST_B -- unused */ - PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* P_SENSOR_INT_L */ - + _PAD_CFG_STRUCT(GPIO_0, 0x44000700, 0x00c01000), // JTAG_TCK + _PAD_CFG_STRUCT(GPIO_1, 0x44000700, 0x00c01000), // JTAG_TRST_N + _PAD_CFG_STRUCT(GPIO_2, 0x44000700, 0x00c03000), // JTAG_TMS + _PAD_CFG_STRUCT(GPIO_3, 0x44000700, 0x00c03000), // JTAG_TDI + _PAD_CFG_STRUCT(GPIO_4, 0x44000700, 0x00c03000), // JTAG_TDO + _PAD_CFG_STRUCT(GPIO_5, 0x44000300, 0x00c3c000), // GPIO + _PAD_CFG_STRUCT(GPIO_6, 0x44000402, 0x00c3f300), // JTAG_PREQ_N + _PAD_CFG_STRUCT(GPIO_7, 0x44000402, 0x00c3f300), // JTAG_PRDY_N + _PAD_CFG_STRUCT(GPIO_8, 0x04000300, 0x0003c032), // GPIO + _PAD_CFG_STRUCT(GPIO_9, 0x04000300, 0x0003c033), // GPIO + _PAD_CFG_STRUCT(GPIO_10, 0x04000300, 0x0003c034), // GPIO + _PAD_CFG_STRUCT(GPIO_11, 0x04000300, 0x0003c035), // GPIO + _PAD_CFG_STRUCT(GPIO_12, 0x04000300, 0x0003c036), // GPIO + _PAD_CFG_STRUCT(GPIO_13, 0x44000300, 0x0003c037), // GPIO + _PAD_CFG_STRUCT(GPIO_14, 0x44000300, 0x0003c038), // GPIO + _PAD_CFG_STRUCT(GPIO_15, 0x44000300, 0x0003c039), // GPIO + _PAD_CFG_STRUCT(GPIO_16, 0x44000300, 0x0003c03a), // GPIO + _PAD_CFG_STRUCT(GPIO_17, 0x44000300, 0x0003c03b), // GPIO + _PAD_CFG_STRUCT(GPIO_18, 0x44000300, 0x0003c03c), // GPIO + _PAD_CFG_STRUCT(GPIO_19, 0x42100102, 0x0002733d), // GPIO + _PAD_CFG_STRUCT(GPIO_20, 0x44000300, 0x0003c03e), // GPIO + _PAD_CFG_STRUCT(GPIO_21, 0x44000802, 0x0000303f), // CNV_MFUART2_RXD + _PAD_CFG_STRUCT(GPIO_22, 0x44000800, 0x00027040), // CNV_MFUART2_TXD + _PAD_CFG_STRUCT(GPIO_23, 0x44000802, 0x00003041), // CNV_GNSS_PA_BLANKING + _PAD_CFG_STRUCT(GPIO_24, 0x44000300, 0x0003c042), // GPIO + _PAD_CFG_STRUCT(GPIO_25, 0x44000300, 0x0003c043), // GPIO + _PAD_CFG_STRUCT(GPIO_26, 0x42800102, 0x00027044), // GPIO + _PAD_CFG_STRUCT(GPIO_27, 0x44000201, 0x00003045), // GPIO + _PAD_CFG_STRUCT(GPIO_28, 0x44000201, 0x00003246), // GPIO + _PAD_CFG_STRUCT(GPIO_29, 0x44000102, 0x00023147), // GPIO + _PAD_CFG_STRUCT(GPIO_30, 0x40900102, 0x0003f048), // GPIO + _PAD_CFG_STRUCT(GPIO_31, 0x40800100, 0x0003f049), // GPIO + _PAD_CFG_STRUCT(GPIO_32, 0x44000100, 0x0003d24a), // GPIO + _PAD_CFG_STRUCT(GPIO_33, 0x40900102, 0x0003f04b), // GPIO + _PAD_CFG_STRUCT(GPIO_34, 0x44000201, 0x0003f34c), // GPIO + _PAD_CFG_STRUCT(GPIO_35, 0x44000201, 0x0003f34d), // GPIO + _PAD_CFG_STRUCT(GPIO_36, 0x44000300, 0x0003c34e), // GPIO + _PAD_CFG_STRUCT(GPIO_37, 0x44000300, 0x0003c04f), // GPIO + _PAD_CFG_STRUCT(GPIO_38, 0x42880102, 0x0003f350), // GPIO + _PAD_CFG_STRUCT(GPIO_39, 0x44000201, 0x0003f351), // GPIO + _PAD_CFG_STRUCT(GPIO_40, 0x44000201, 0x0003f352), // GPIO + _PAD_CFG_STRUCT(GPIO_41, 0x44000300, 0x0003c053), // GPIO + _PAD_CFG_STRUCT(GPIO_42, 0x44000700, 0x00001054), // MDSI_A_TE + _PAD_CFG_STRUCT(GPIO_43, 0x44000702, 0x00001055), // MDSI_C_TE + _PAD_CFG_STRUCT(GPIO_44, 0x44000402, 0x00003356), // USB2_OC0_N + _PAD_CFG_STRUCT(GPIO_45, 0x44000402, 0x00003357), // USB2_OC1_N + _PAD_CFG_STRUCT(GPIO_46, 0x44000300, 0x0003c058), // GPIO + _PAD_CFG_STRUCT(GPIO_47, 0x44000300, 0x0003c059), // GPIO + _PAD_CFG_STRUCT(GPIO_48, 0x44000402, 0x0003e75a), // PMC_I2C_SDA + _PAD_CFG_STRUCT(GPIO_49, 0x44000402, 0x0003e75b), // PMC_I2C_SCL + _PAD_CFG_STRUCT(GPIO_50, 0x44000402, 0x0002275c), // SIO_I2C0_SDA + _PAD_CFG_STRUCT(GPIO_51, 0x44000402, 0x0002275d), // SIO_I2C0_SCL + _PAD_CFG_STRUCT(GPIO_52, 0x44000300, 0x0003c05e), // GPIO + _PAD_CFG_STRUCT(GPIO_53, 0x44000300, 0x0003c05f), // GPIO + _PAD_CFG_STRUCT(GPIO_54, 0x44000300, 0x0003c060), // GPIO + _PAD_CFG_STRUCT(GPIO_55, 0x44000300, 0x0003c061), // GPIO + _PAD_CFG_STRUCT(GPIO_56, 0x44000300, 0x0003c062), // GPIO + _PAD_CFG_STRUCT(GPIO_57, 0x44000300, 0x0003c063), // GPIO + _PAD_CFG_STRUCT(GPIO_58, 0x44000402, 0x00022764), // SIO_I2C4_SDA + _PAD_CFG_STRUCT(GPIO_59, 0x44000402, 0x00022765), // SIO_I2C4_SCL + _PAD_CFG_STRUCT(GPIO_60, 0x44000300, 0x0003c066), // GPIO + _PAD_CFG_STRUCT(GPIO_61, 0x44000300, 0x00003067), // GPIO + _PAD_CFG_STRUCT(GPIO_62, 0x46880100, 0x0003c068), // GPIO + _PAD_CFG_STRUCT(GPIO_63, 0x44000300, 0x0003c069), // GPIO + _PAD_CFG_STRUCT(GPIO_64, 0x44000402, 0x0002336a), // SIO_UART2_RXD + _PAD_CFG_STRUCT(GPIO_65, 0x44000400, 0x0002336b), // SIO_UART2_TXD + _PAD_CFG_STRUCT(GPIO_66, 0x44000201, 0x0000336c), // GPIO + _PAD_CFG_STRUCT(GPIO_67, 0x44840102, 0x0002036d), // GPIO + _PAD_CFG_STRUCT(GPIO_68, 0x44000300, 0x0003c06e), // GPIO + _PAD_CFG_STRUCT(GPIO_69, 0x44000300, 0x0003c06f), // GPIO + _PAD_CFG_STRUCT(GPIO_70, 0x44000300, 0x0003c070), // GPIO + _PAD_CFG_STRUCT(GPIO_71, 0x44000300, 0x0003c071), // GPIO + _PAD_CFG_STRUCT(GPIO_72, 0x44000300, 0x0003c072), // GPIO + _PAD_CFG_STRUCT(GPIO_73, 0x44000201, 0x0003f373), // GPIO + _PAD_CFG_STRUCT(GPIO_74, 0x44000400, 0x0003f300), // THERMTRIP_N + _PAD_CFG_STRUCT(GPIO_75, 0x44000702, 0x00003000), // PROCHOT_N +// _PAD_CFG_STRUCT(GPIO_211, 0xffffffff, 0xffffffff), RESERVED + _PAD_CFG_STRUCT(GPIO_212, 0x44000102, 0x0001f375), // GPIO + _PAD_CFG_STRUCT(GPIO_213, 0x44000102, 0x0001d376), // GPIO + _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x0001d377), // GPIO /* NORTH COMMUNITY GPIOS */ - - /* svid - unused */ - PAD_NC(GPIO_76, UP_20K),/* SVID Alert - unused */ - PAD_NC(GPIO_77, UP_20K),/* SVID Data - unused */ - PAD_NC(GPIO_78, UP_20K),/* SVID Clk - unused */ - - /* LPSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_79, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* H1_SLAVE_SPI_CLK_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_80, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* H1_SLAVE_SPI_CS_L_R */ - PAD_NC(GPIO_81, DN_20K), /* GPIO_81_DEBUG -- debug header NC */ - PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ - PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ - PAD_NC(GPIO_84, DN_20K), /* LPSS_SPI_2_CLK - unused */ - PAD_NC(GPIO_85, DN_20K), /* LPSS_SPI_2_FS0 - unused */ - PAD_NC(GPIO_86, DN_20K), /* LPSS_SPI_2_FS1 - unused */ - PAD_NC(GPIO_87, DN_20K), /* LPSS_SPI_2_FS2 - unused */ - PAD_NC(GPIO_88, DN_20K), /* LPSS_SPI_2_RXD - unused */ - PAD_NC(GPIO_89, DN_20K), /* LPSS_SPI_2_TXD - unused */ - - /* Fast SPI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ - PAD_NC(GPIO_94, NATIVE),/* FST_SPI_IO2 - unused */ - PAD_NC(GPIO_95, NATIVE),/* FST_SPI_IO3 - unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ - - /* PMU Signals */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1),/* PMU_PLTRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ - PAD_NC(GPIO_104, UP_20K),/* EMMC_DNX_PWR_EN_B - unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ - PAD_NC(GPIO_108, NONE),/* PMU_SUSCLK -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */ - - /* I2C5 - Audio */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SCL */ - - /* I2C6 - Trackpad */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SCL */ - - /* I2C7 - Touchscreen */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */ - - /* PCIE_WAKE[0:3]_B */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ - PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ - PAD_NC(GPIO_118, UP_20K),/* PCIE_WAKE2_B -- unused */ - PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */ - - /* - * PCIE_CLKREQ[0:3]_B. For unused pins, follow the termination - * guideline for unused PCIE ports as described in PDG i.e. keep - * the pins in native mode and deploy the internal pull up. - */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ - - /* DDI[0:1] SDA and SCL -- unused */ - PAD_NC(GPIO_124, UP_20K),/* HV_DDI0_DDC_SDA -- unused */ - PAD_NC(GPIO_125, UP_20K),/* HV_DDI0_DDC_SCL -- unused */ - PAD_NC(GPIO_126, UP_20K),/* HV_DDI1_DDC_SDA -- unused */ - PAD_NC(GPIO_127, UP_20K),/* HV_DDI1_DDC_SCL -- unused */ - - /* Panel 0 control */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTEN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTCTL */ - - /* Hot plug detect. */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI0_HPD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */ - - /* EC_AP_INT_ODL */ - PAD_CFG_GPI_APIC_LOW(GPIO_134, NONE, DEEP), - - PAD_CFG_GPI_IRQ_WAKE(GPIO_135, NONE, DEEP, LEVEL, INVERT),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ - // Also we may be able to use eSPI WAKE# Virtual Wire instead - PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ - PAD_NC(GPIO_142, UP_20K),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL(unused) */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_143, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* GPIO_143 -- LTE_SAR_ODL */ - - /* GPIO_144 -- PEN_EJECT(wake) */ - PAD_CFG_GPI_SCI_HIGH_DEBEN(GPIO_144, UP_20K, DEEP, EDGE_SINGLE, - DEBOUNCE_256_RTC), - /* GPIO_145 -- PEN_EJECT(notifications) */ - PAD_CFG_GPI_GPIO_DRIVER(GPIO_145, UP_20K, DEEP), - PAD_NC(GPIO_146, UP_20K),/* GPIO_146 -- unused */ - - /* - * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for - * eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO - * and kept unconnected to allow S0ix entry. - */ - - /* AUDIO COMMUNITY GPIOS*/ - PAD_NC(GPIO_156, DN_20K), /* AVS_I2S0_MCLK -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_BCLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_WS_SYNC */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_SDI */ - PAD_NC(GPIO_160, DN_20K), /* AVS_I2S0_SDO -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */ - - /* Disable standby for GPIO_171 and GPIO_173 to support Wake on Voice */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_171, DN_20K, DEEP, NF1), /* AVS_M_CLK_A1 -- DMIC_CLK1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_173, DN_20K, DEEP, NF1), /* AVS_M_DATA_1 -- DMIC_DATA */ - PAD_NC(GPIO_174, DN_20K), /* AVS_M_CLK_AB2 -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ - - /* SCC COMMUNITY GPIOS */ - PAD_NC(GPIO_176, UP_20K), /* SMB_ALERTB -- unused */ - PAD_NC(GPIO_177, UP_20K), /* SMB_CLK -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_WLAN_L */ - - PAD_NC(GPIO_179, NONE), /* SDCARD_CLK -- unused */ - PAD_NC(GPIO_180, NONE), /* SDCARD_CMD -- unused */ - PAD_NC(GPIO_181, UP_20K), /* SDCARD_D0 -- unused */ - PAD_NC(GPIO_182, UP_20K), /* SDCARD_D1 -- unused */ - PAD_NC(GPIO_183, UP_20K), /* SDCARD_D2 -- unused */ - PAD_NC(GPIO_184, UP_20K), /* SDCARD_D3 -- unused */ - PAD_NC(GPIO_185, UP_20K), /* SDCARD_CMD -- unused */ - PAD_NC(GPIO_186, UP_20K), /* SDCARD_CD_N -- unused */ - PAD_NC(GPIO_187, NONE), /* SDCARD_LVL_WP -- unused */ - PAD_NC(GPIO_188, UP_20K), /* SDCARD_PWR_DWN_N -- unused */ - PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */ - PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ - - /* - * Disable standby state for these CNVI pins to allow wake on - * WiFI & Bluetooth. - */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNV_RF_RESET_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D2 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D3 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D4 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D5 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ - PAD_NC(GPIO_210, DN_20K), -}; + _PAD_CFG_STRUCT(GPIO_76, 0x44000400, 0x0003c000), // SVID0_ALERT_N + _PAD_CFG_STRUCT(GPIO_77, 0x44000400, 0x0003c000), // SVID0_DATA + _PAD_CFG_STRUCT(GPIO_78, 0x44000400, 0x0003c000), // SVID0_CLK + _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d232), // SIO_SPI_0_CLK + _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d233), // SIO_SPI_0_FS0 + _PAD_CFG_STRUCT(GPIO_81, 0x44000c02, 0x0003d034), // FST_SPI_CS2_N + _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d235), // SIO_SPI_0_RXD + _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x0003d236), // SIO_SPI_0_TXD + _PAD_CFG_STRUCT(GPIO_84, 0x44000100, 0x00001037), // GPIO + _PAD_CFG_STRUCT(GPIO_85, 0x44000300, 0x00001038), // GPIO + _PAD_CFG_STRUCT(GPIO_86, 0x44000300, 0x00001039), // GPIO + _PAD_CFG_STRUCT(GPIO_87, 0x44000300, 0x0003c03a), // GPIO + _PAD_CFG_STRUCT(GPIO_88, 0x44000300, 0x0003c03b), // GPIO + _PAD_CFG_STRUCT(GPIO_89, 0x44000300, 0x0003c03c), // GPIO + _PAD_CFG_STRUCT(GPIO_90, 0x44000502, 0x00003c3d), // FST_SPI_CS0_N + _PAD_CFG_STRUCT(GPIO_91, 0x44000300, 0x0003fc3e), // GPIO + _PAD_CFG_STRUCT(GPIO_92, 0x44000500, 0x00003c3f), // FST_SPI_MOSI_IO + _PAD_CFG_STRUCT(GPIO_93, 0x44000502, 0x00003c40), // FST_SPI_MISO_IO + _PAD_CFG_STRUCT(GPIO_94, 0x44000502, 0x00003c41), // FST_SPI_IO2 + _PAD_CFG_STRUCT(GPIO_95, 0x44000502, 0x00003c42), // FST_SPI_IO3 + _PAD_CFG_STRUCT(GPIO_96, 0x44000500, 0x00003c43), // FST_SPI_CLK + _PAD_CFG_STRUCT(GPIO_97, 0x44000500, 0x00003c00), // FST_SPI_CLK_FB + _PAD_CFG_STRUCT(GPIO_98, 0x44000400, 0x0003c000), // PMU_PLTRST_N + _PAD_CFG_STRUCT(GPIO_99, 0x44000402, 0x0003f300), // PMU_PWRBTN_N + _PAD_CFG_STRUCT(GPIO_100, 0x44000400, 0x0003c000), // PMU_SLP_S0_N + _PAD_CFG_STRUCT(GPIO_101, 0x44000400, 0x0003c000), // PMU_SLP_S3_N + _PAD_CFG_STRUCT(GPIO_102, 0x44000400, 0x0003c000), // PMU_SLP_S4_N + _PAD_CFG_STRUCT(GPIO_103, 0x44000400, 0x0003c000), // SUSPWRDNACK + _PAD_CFG_STRUCT(GPIO_104, 0x44000700, 0x00003000), // EMMC_PWR_EN_N + _PAD_CFG_STRUCT(GPIO_105, 0x44000300, 0x0003c344), // GPIO + _PAD_CFG_STRUCT(GPIO_106, 0x44000402, 0x0003f300), // PMU_BATLOW_N + _PAD_CFG_STRUCT(GPIO_107, 0x44000400, 0x0003f300), // PMU_RSTBTN_N + _PAD_CFG_STRUCT(GPIO_108, 0x44000400, 0x0003c000), // PMU_SUSCLK + _PAD_CFG_STRUCT(GPIO_109, 0x44000400, 0x0003c000), // SUS_STAT_N + _PAD_CFG_STRUCT(GPIO_110, 0x44000402, 0x0003e745), // SIO_I2C5_SDA + _PAD_CFG_STRUCT(GPIO_111, 0x44000402, 0x0003e746), // SIO_I2C5_SCL + _PAD_CFG_STRUCT(GPIO_112, 0x44000300, 0x0003c047), // GPIO + _PAD_CFG_STRUCT(GPIO_113, 0x44000300, 0x0003c048), // GPIO + _PAD_CFG_STRUCT(GPIO_114, 0x44000402, 0x00022749), // SIO_I2C7_SDA + _PAD_CFG_STRUCT(GPIO_115, 0x44000402, 0x0002274a), // SIO_I2C7_SCL + _PAD_CFG_STRUCT(GPIO_116, 0x44000402, 0x0003f34b), // PCIE_WAKE0_N + _PAD_CFG_STRUCT(GPIO_117, 0x44000402, 0x0003f34c), // PCIE_WAKE1_N + _PAD_CFG_STRUCT(GPIO_118, 0x44000402, 0x0003f34d), // PCIE_WAKE2_N + _PAD_CFG_STRUCT(GPIO_119, 0x44000300, 0x0003c04e), // GPIO + _PAD_CFG_STRUCT(GPIO_120, 0x44000402, 0x0002334f), // PCIE_CLKREQ0_N + _PAD_CFG_STRUCT(GPIO_121, 0x44000402, 0x00023350), // PCIE_CLKREQ1_N + _PAD_CFG_STRUCT(GPIO_122, 0x44000400, 0x00023351), // PCIE_CLKREQ2_N + _PAD_CFG_STRUCT(GPIO_123, 0x44000300, 0x00020352), // GPIO + _PAD_CFG_STRUCT(GPIO_124, 0x44000402, 0x0001c353), // DDI0_DDC_SDA + _PAD_CFG_STRUCT(GPIO_125, 0x44000402, 0x0001c354), // DDI0_DDC_SCL + _PAD_CFG_STRUCT(GPIO_126, 0x44000300, 0x0003c055), // GPIO + _PAD_CFG_STRUCT(GPIO_127, 0x44000300, 0x0003c056), // GPIO + _PAD_CFG_STRUCT(GPIO_128, 0x44000400, 0x00005257), // PNL0_VDDEN + _PAD_CFG_STRUCT(GPIO_129, 0x44000400, 0x00005258), // PNL0_BKLTEN + _PAD_CFG_STRUCT(GPIO_130, 0x44000400, 0x00005259), // PNL0_BKLCTL + _PAD_CFG_STRUCT(GPIO_131, 0x44000402, 0x0002735a), // DDI0_HPD + _PAD_CFG_STRUCT(GPIO_132, 0x44000402, 0x0002735b), // DDI1_HPD + _PAD_CFG_STRUCT(GPIO_133, 0x44000400, 0x0002435c), // DDI2_HPD + _PAD_CFG_STRUCT(GPIO_134, 0x44000201, 0x0003f35d), // GPIO + _PAD_CFG_STRUCT(GPIO_135, 0x44000201, 0x0000325e), // GPIO + _PAD_CFG_STRUCT(GPIO_136, 0x44000300, 0x0003c05f), // GPIO + _PAD_CFG_STRUCT(GPIO_137, 0x44000300, 0x0003c060), // GPIO + _PAD_CFG_STRUCT(GPIO_138, 0x44000102, 0x00000061), // GPIO + _PAD_CFG_STRUCT(GPIO_139, 0x44000300, 0x0003c062), // GPIO + _PAD_CFG_STRUCT(GPIO_140, 0x44000100, 0x00001063), // GPIO + _PAD_CFG_STRUCT(GPIO_141, 0x44001400, 0x00020364), // SATA_DEVSLP1 + _PAD_CFG_STRUCT(GPIO_142, 0x44900102, 0x00023365), // GPIO + _PAD_CFG_STRUCT(GPIO_143, 0x44900102, 0x00020066), // GPIO + _PAD_CFG_STRUCT(GPIO_144, 0x44000201, 0x00001067), // GPIO + _PAD_CFG_STRUCT(GPIO_145, 0x44000201, 0x00001068), // GPIO + _PAD_CFG_STRUCT(GPIO_146, 0x44001400, 0x00001069), // n/a + _PAD_CFG_STRUCT(GPIO_147, 0x44000702, 0x0000336a), // LPC_SERIRQ + _PAD_CFG_STRUCT(GPIO_148, 0x44000700, 0x0002006b), // LPC_CLKOUT0 + _PAD_CFG_STRUCT(GPIO_149, 0x44000700, 0x0002006c), // LPC_CLKOUT1 + _PAD_CFG_STRUCT(GPIO_150, 0x44000702, 0x0002336d), // LPC_AD0 + _PAD_CFG_STRUCT(GPIO_151, 0x44000702, 0x0002336e), // LPC_AD1 + _PAD_CFG_STRUCT(GPIO_152, 0x44000702, 0x0002336f), // LPC_AD2 + _PAD_CFG_STRUCT(GPIO_153, 0x44000702, 0x00023370), // LPC_AD3 + _PAD_CFG_STRUCT(GPIO_154, 0x44000702, 0x00003071), // LPC_CLKRUN_N + _PAD_CFG_STRUCT(GPIO_155, 0x44000700, 0x00023372), // LPC_FRAME_N + /* Group Audio GPIOS */ + _PAD_CFG_STRUCT(GPIO_156, 0x42000100, 0x0003d200), // GPIO + _PAD_CFG_STRUCT(GPIO_157, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_158, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_159, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_160, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_161, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_162, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_163, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_164, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_165, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_166, 0x44000400, 0x00021200), // AVS_HDA_BCLK + _PAD_CFG_STRUCT(GPIO_167, 0x44000400, 0x00021200), // AVS_HDA_WS_SYNC + _PAD_CFG_STRUCT(GPIO_168, 0x44000400, 0x00020000), // AVS_HDA_SDI + _PAD_CFG_STRUCT(GPIO_169, 0x44000400, 0x00021200), // AVS_HDA_SDO + _PAD_CFG_STRUCT(GPIO_170, 0x44000402, 0x00021200), // AVS_HDA_RST_N + _PAD_CFG_STRUCT(GPIO_171, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_172, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_173, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_174, 0x44000201, 0x00003300), // GPIO + _PAD_CFG_STRUCT(GPIO_175, 0x44000100, 0x00001000), // GPIO + /* Group SCC GPIOS */ + _PAD_CFG_STRUCT(GPIO_176, 0x40800102, 0x0003f000), // GPIO + _PAD_CFG_STRUCT(GPIO_177, 0x44000102, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_178, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_187, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_179, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_180, 0x44000400, 0x00001200), // SDCARD_CLK_FB + _PAD_CFG_STRUCT(GPIO_181, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_182, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_183, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_184, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_185, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_186, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_188, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_210, 0x44000200, 0x0001f200), // GPIO + _PAD_CFG_STRUCT(GPIO_189, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_190, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_191, 0x44000400, 0x0003c000), // CNV_BRI_DT + _PAD_CFG_STRUCT(GPIO_192, 0x44000402, 0x0003f300), // CNV_BRI_RST + _PAD_CFG_STRUCT(GPIO_193, 0x44000400, 0x0003c000), // CNV_RGI_DT + _PAD_CFG_STRUCT(GPIO_194, 0x44000400, 0x0003f300), // CNV_RGI_RST + _PAD_CFG_STRUCT(GPIO_195, 0x44000400, 0x0003c000), // CNV_RF_RESET_N + _PAD_CFG_STRUCT(GPIO_196, 0x44000400, 0x0003c000), // XTAL_CLKREQ + _PAD_CFG_STRUCT(GPIO_197, 0x44000b00, 0x00001200), // n/a + _PAD_CFG_STRUCT(GPIO_198, 0x44000400, 0x0001d200), // EMMC_CLK + _PAD_CFG_STRUCT(GPIO_199, 0x44000500, 0x00001200), // EMMC_D0 + _PAD_CFG_STRUCT(GPIO_200, 0x44000402, 0x00023300), // EMMC_D1 + _PAD_CFG_STRUCT(GPIO_201, 0x44000402, 0x00023300), // EMMC_D2 + _PAD_CFG_STRUCT(GPIO_202, 0x44000402, 0x00023300), // EMMC_D3 + _PAD_CFG_STRUCT(GPIO_203, 0x44000402, 0x00023300), // EMMC_D4 + _PAD_CFG_STRUCT(GPIO_204, 0x44000402, 0x00023300), // EMMC_D5 + _PAD_CFG_STRUCT(GPIO_205, 0x44000402, 0x00023300), // EMMC_D6 + _PAD_CFG_STRUCT(GPIO_206, 0x44000402, 0x00023300), // EMMC_D7 + _PAD_CFG_STRUCT(GPIO_207, 0x44000402, 0x00023300), // EMMC_CMD + _PAD_CFG_STRUCT(GPIO_208, 0x44000402, 0x00023300), // EMMC_RCLK + _PAD_CFG_STRUCT(GPIO_209, 0x44000400, 0x0001d200), // EMMC_RST_N} +; const struct pad_config *__weak variant_base_gpio_table(size_t *num) { @@ -307,43 +265,41 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ + _PAD_CFG_STRUCT(GPIO_190, 0x44000300, 0x0003c000), /* PCH_WP_OD */ /* GSPI0_INT */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, - DISPUPD), /* H1_PCH_INT_ODL */ + _PAD_CFG_STRUCT(GPIO_63, 0x44000300, 0x0003c069), /* H1_PCH_INT_ODL */ /* GSPI0_CLK */ - PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ + _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d232), /* H1_SLAVE_SPI_CLK_R */ /* GSPI0_CS# */ - PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */ + _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d233), /* H1_SLAVE_SPI_CS_L_R */ /* GSPI0_MISO */ - PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ + _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d235), /* H1_SLAVE_SPI_MISO */ /* GSPI0_MOSI */ - PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ + _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x0003d236), /* H1_SLAVE_SPI_MOSI_R */ /* Enable power to wifi early in bootblock and de-assert PERST#. */ - PAD_CFG_GPO(GPIO_178, 0, DEEP), /* EN_PP3300_WLAN_L */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ + _PAD_CFG_STRUCT(GPIO_178, 0x44000300, 0x0003c000), /* EN_PP3300_WLAN_L */ + _PAD_CFG_STRUCT(GPIO_164, 0x44000100, 0x00001000), /* WLAN_PE_RST */ /* * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, - ENPU), /* ESPI_IO1 */ + _PAD_CFG_STRUCT(GPIO_151, 0x44000702, 0x0002336e), /* ESPI_IO1 */ /* GPIO_67 and GPIO_117 are in early_gpio_table and gpio_table. For variants * having LTE SKUs, these two GPIOs would be overridden to output high first * in the bootblock then be set to default state in gpio_table for non-LTE * SKUs and keep to output high for LTE SKUs in ramstage. */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ + _PAD_CFG_STRUCT(GPIO_67, 0x44840102, 0x0002036d), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + _PAD_CFG_STRUCT(GPIO_117, 0x44000402, 0x0003f34c),/* PCIE_WAKE1_B -- LTE_WAKE_L */ /* GPIO_161 is in early_gpio_table and gpio_table because LTE SKU needs * to override this pin to output low then high respectively in two * stages. */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ + _PAD_CFG_STRUCT(GPIO_161, 0x44000100, 0x00001000), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ }; const struct pad_config *__weak @@ -360,7 +316,7 @@ /* GPIO settings before entering slp_s5. */ static const struct pad_config sleep_s5_gpio_table[] = { /* BT_DISABLE_L */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 0, DEEP, NONE, Tx0RxDCRx1, SAME), + _PAD_CFG_STRUCT(GPIO_109, 0x44000400, 0x0003c000), }; const struct pad_config *__weak diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab56..07d5129 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1036,6 +1036,7 @@ case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: case PCI_DEVICE_ID_INTEL_APL_LPC: + case PCI_DEVICE_ID_INTEL_GLK: case PCI_DEVICE_ID_INTEL_DNV_LPC: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..cc1d99e 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -45,6 +45,310 @@ * (if it's the first column, GPIO is the default, no matter the name) */ +static const char *const glk_group_northwest_names[] = { + "GPIO_0", "JTAG_TCK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_1", "JTAG_TRST_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_2", "JTAG_TMS", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_3", "JTAG_TDI", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_4", "JTAG_TDO", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_5", "JTAGX", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_6", "JTAG_PREQ_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_7", "JTAG_PRDY_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_8", "n/a", "n/a", "CNV_DEBUG_09", "CNV_DEBUG_00", "n/a", "n/a", + "GPIO_9", "n/a", "n/a", "CNV_DEBUG_10", "CNV_DEBUG_01", "n/a", "n/a", + "GPIO_10", "n/a", "n/a", "CNV_DEBUG_11", "CNV_DEBUG_02", "n/a", "n/a", + "GPIO_11", "n/a", "n/a", "CNV_DEBUG_12", "CNV_DEBUG_03", "n/a", "n/a", + "GPIO_12", "n/a", "n/a", "CNV_DEBUG_13", "CNV_DEBUG_04", "n/a", "n/a", + "GPIO_13", "n/a", "n/a", "CNV_DEBUG_14", "CNV_DEBUG_05", "n/a", "n/a", + "GPIO_14", "n/a", "n/a", "CNV_DEBUG_15", "CNV_DEBUG_06", "n/a", "n/a", + "GPIO_15", "n/a", "n/a", "CNV_DEBUG_16", "CNV_DEBUG_07", "n/a", "n/a", + "GPIO_16", "n/a", "n/a", "CNV_DEBUG_17", "CNV_DEBUG_08", "n/a", "n/a", + "GPIO_17", "n/a", "CNV_MFUART0_RXD", "CNV_DEBUG_00", "n/a", "n/a", "n/a", + "GPIO_18", "n/a", "CNV_MFUART0_TXD", "CNV_DEBUG_01", "n/a", "n/a", "n/a", + "GPIO_19", "n/a", "CNV_MFUART0_RTS_N", "CNV_DEBUG_02", "n/a", "n/a", "n/a", + "GPIO_20", "n/a", "CNV_MFUART0_CTS_N", "CNV_DEBUG_03", "n/a", "n/a", "n/a", + "GPIO_21", "n/a", "CNV_MFUART2_RXD", "CNV_DEBUG_04", "n/a", "n/a", "n/a", + "GPIO_22", "n/a", "CNV_MFUART2_TXD", "CNV_DEBUG_05", "n/a", "n/a", "n/a", + "GPIO_23", "n/a", "CNV_GNSS_PA_BLANKING", "CNV_DEBUG_06", "PMIC_STDBY", "n/a", "n/a", + "GPIO_24", "n/a", "CNV_GNSS_FTA", "CNV_DEBUG_07", "PMIC_PWRGOOD", "n/a", "n/a", + "GPIO_25", "n/a", "CNV_GNSS_SYSCK", "CNV_DEBUG_08", "PMIC_RESET_N", "n/a", "n/a", + "GPIO_26", "n/a", "SIO_UART1_RXD", "ISH_UART1_RXD", "CNV_BT_UART_RXD", "n/a", "n/a", + "GPIO_27", "n/a", "SIO_UART1_TXD", "ISH_UART1_TXD", "CNV_BT_UART_TXD", "n/a", "n/a", + "GPIO_28", "n/a", "SIO_UART1_RTS_N", "ISH_UART1_RTS_N", "CNV_BT_UART_RTS_N", "n/a", "n/a", + "GPIO_29", "n/a", "SIO_UART1_CTS_N", "ISH_UART1_CTS_N", "CNV_BT_UART_CTS_N", "n/a", "n/a", + "GPIO_30", "n/a", "SATA_GP0", "n/a", "n/a", "n/a", "n/a", + "GPIO_31", "n/a", "SATA_GP1", "n/a", "n/a", "n/a", "n/a", + "GPIO_32", "n/a", "SATA_DE_VSLP0", "n/a", "n/a", "n/a", "n/a", + "GPIO_33", "n/a", "SATA_DE_VSLP1", "SUSCLK1", "n/a", "n/a", "n/a", + "GPIO_34", "n/a", "SATA_LEDN", "SUSCLK2", "n/a", "n/a", "n/a", + "GPIO_35", "n/a", "n/a", "n/a", "SPKR", "n/a", "BSSB_CLK", + "GPIO_36", "n/a", "n/a", "CNV_BTEN", "n/a", "n/a", "BSSB_DI", + "GPIO_37", "n/a", "n/a", "CNV_GNEN", "n/a", "n/a", "n/a", + "GPIO_38", "n/a", "n/a", "CNV_WFEN", "n/a", "n/a", "n/a", + "GPIO_39", "n/a", "n/a", "CNV_WCEN", "n/a", "n/a", "n/a", + "GPIO_40", "n/a", "n/a", "CNVBT_HOST_WAKE_N", "n/a", "n/a", "n/a", + "GPIO_41", "n/a", "n/a", "CNV_GNSS_HOST_WAKE_N", "n/a", "n/a", "n/a", + "GPIO_42", "MDSI_A_TE", "PWM0", "n/a", "n/a", "n/a", "n/a", + "GPIO_43", "MDSI_C_TE", "PWM1", "n/a", "n/a", "n/a", "n/a", + "GPIO_44", "USB2_OC0_N", "PWM2", "n/a", "n/a", "n/a", "n/a", + "GPIO_45", "USB2_OC1_N", "PWM3", "n/a", "n/a", "n/a", "n/a", + "GPIO_46", "MIPI_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_47", "MIPI_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_48", "PMC_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_49", "PMC_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_50", "SIO_I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_51", "SIO_I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_52", "SIO_I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_53", "SIO_I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_54", "SIO_I2C2_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_55", "SIO_I2C2_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_56", "SIO_I2C3_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_57", "SIO_I2C3_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_58", "SIO_I2C4_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_59", "SIO_I2C4_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_60", "SIO_UART0_RXD", "ISH_UART0_RXD", "CNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "GPIO_61", "SIO_UART0_TXD", "ISH_UART0_TXD", "CNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "GPIO_62", "SIO_UART0_RTS_N", "ISH_UART0_RTS_N", "CNV_GNSS_UART_RTS_N", "n/a", "n/a", "n/a", + "GPIO_63", "SIO_UART0_CTS_N", "ISH_UART0_CTS_N", "CNV_GNSS_UART_CTS_N", "n/a", "n/a", "n/a", + "GPIO_64", "SIO_UART2_RXD", "ISH_UART2_RXD", "CNV_MFUART1_RXD", "n/a", "n/a", "n/a", + "GPIO_65", "SIO_UART2_TXD", "ISH_UART2_TXD", "CNV_MFUART1_TXD", "n/a", "n/a", "n/a", + "GPIO_66", "SIO_UART2_RTS_N", "ISH_UART2_RTS_N", "CNV_MFUART1_RTS_N", "n/a", "n/a", "n/a", + "GPIO_67", "SIO_UART2_CTS_N", "ISH_UART2_CTS_N", "CNV_MFUART1_CTS_N", "n/a", "n/a", "n/a", + "GPIO_68", "PMC_SPI_FS0", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_69", "PMC_SPI_FS1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_70", "PMC_SPI_FS2", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_71", "PMC_SPI_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_72", "PMC_SPI_TXD", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_73", "PMC_SPI_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_74", "THERMTRIP_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_75", "PROCHOT_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_211","EMMC_RST_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_212", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_213", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_214", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_northwest = { + .display = "------- GPIO Group NorthWest -------", + .pad_count = ARRAY_SIZE(glk_group_northwest_names) / 7, + .func_count = 7, + .pad_names = glk_group_northwest_names, +}; + +static const struct gpio_group *const glk_community_northwest_groups[] = { + &glk_group_northwest, +}; + +static const struct gpio_community glk_community_northwest = { + .name = "----- GPIO Community NorthWest -----", + .pcr_port_id = 0xc4, + .group_count = ARRAY_SIZE(glk_community_northwest_groups), + .groups = glk_community_northwest_groups, +}; + +static const char *const glk_group_north_names[] = { + "GPIO_76", "SVID0_ALERT_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_77", "SVID0_DATA", "n/a", "n/a", "n/a", "n/a", + "GPIO_78", "SVID0_CLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_79", "SIO_SPI_0_CLK", "ISH_SPI_0_CLK", "n/a", "n/a", "n/a", + "GPIO_80", "SIO_SPI_0_FS0", "ISH_SPI_0_FS0", "n/a", "n/a", "n/a", + "GPIO_81", "SIO_SPI_0_FS1", "ISH_SPI_0_FS1", "FST_SPI_CS2_N", "n/a", "n/a", + "GPIO_82", "SIO_SPI_0_RXD", "ISH_SPI_0_RXD", "n/a", "n/a", "n/a", + "GPIO_83", "SIO_SPI_0_TXD", "ISH_SPI_0_TXD", "n/a", "n/a", "n/a", + "GPIO_84", "SIO_SPI_2_CLK", "ISH_SPI_1_CLK", "TOUCH_SPI_CLK", "n/a", "n/a", + "GPIO_85", "SIO_SPI_2_FS0", "ISH_SPI_1_FS0", "TOUCH_SPI_FS0", "n/a", "n/a", + "GPIO_86", "SIO_SPI_2_FS1", "ISH_SPI_1_FS1", "TOUCH_SPI_D0", "n/a", "n/a", + "GPIO_87", "SIO_SPI_2_FS2", "n/a", "TOUCH_SPI_D1", "n/a", "n/a", + "GPIO_88", "SIO_SPI_2_RXD", "ISH_SPI_1_RXD", "TOUCH_SPI_D2", "n/a", "n/a", + "GPIO_89", "SIO_SPI_2_TXD", "ISH_SPI_0_TXD", "TOUCH_SPI_D3", "n/a", "n/a", + "GPIO_90", "FST_SPI_CS0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_91", "FST_SPI_CS1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_92", "FST_SPI_MOSI_IO0", "n/a", "n/a", "n/a", "n/a", + "GPIO_93", "FST_SPI_MISO_IO1", "n/a", "n/a", "n/a", "n/a", + "GPIO_94", "FST_SPI_IO2", "n/a", "n/a", "n/a", "n/a", + "GPIO_95", "FST_SPI_IO3", "n/a", "n/a", "n/a", "n/a", + "GPIO_96", "FST_SPI_CLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_97", "FST_SPI_CLK_FB", "n/a", "n/a", "n/a", "n/a", + "GPIO_98", "PMU_PLTRST_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_99", "PMU_PWRBTN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_100", "PMU_SLP_S0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_101", "PMU_SLP_S3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_102", "PMU_SLP_S4_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_103", "SUSPWRDNACK", "n/a", "n/a", "n/a", "n/a", + "GPIO_104", "EMMC_PWR_EN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_105", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPIO_106", "PMU_BATLOW_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_107", "PMU_RSTBTN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_108", "PMU_SUSCLK", "n/a", "n/a", "n/a", "n/a", + "GPIO_109", "SUS_STAT_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_110", "SIO_I2C5_SDA", "ISH_I2C0_SDA", "n/a", "n/a", "n/a", + "GPIO_111", "SIO_I2C5_SCL", "ISH_I2C0_SCL", "n/a", "n/a", "n/a", + "GPIO_112", "SIO_I2C6_SDA", "ISH_I2C1_SDA", "n/a", "n/a", "n/a", + "GPIO_113", "SIO_I2C6_SCL", "ISH_I2C1_ScL", "n/a", "n/a", "n/a", + "GPIO_114", "SIO_I2C7_SDA", "ISH_I2C2_SDA", "SUSCLK1", "n/a", "n/a", + "GPIO_115", "SIO_I2C7_SCL", "ISH_I2C2_SCL", "SUSCLK2", "n/a", "n/a", + "GPIO_116", "PCIE_WAKE0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_117", "PCIE_WAKE1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_118", "PCIE_WAKE2_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_119", "PCIE_WAKE3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_120", "PCIE_CLKREQ0_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_121", "PCIE_CLKREQ1_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_122", "PCIE_CLKREQ2_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_123", "PCIE_CLKREQ3_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_124", "DDI0_DDC_SDA", "n/a", "n/a", "n/a", "n/a", + "GPIO_125", "DDI0_DDC_SCL", "n/a", "n/a", "n/a", "n/a", + "GPIO_126", "DDI1_DDC_SDA", "SIO_I2C5_SDA", "n/a", "n/a", "n/a", + "GPIO_127", "DDI1_DDC_SCL", "SIO_I2C5_SCL", "n/a", "n/a", "n/a", + "GPIO_128", "PNL0_VDDEN", "n/a", "n/a", "n/a", "n/a", + "GPIO_129", "PNL0_BKLTEN", "n/a", "n/a", "n/a", "n/a", + "GPIO_130", "PNL0_BKLCTL", "n/a", "n/a", "n/a", "n/a", + "GPIO_131", "DDI0_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_132", "DDI1_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_133", "DDI2_HPD", "n/a", "n/a", "n/a", "n/a", + "GPIO_134", "n/a", "n/a", "n/a", "ISH_GPIO_10", "n/a", + "GPIO_135", "n/a", "n/a", "n/a", "ISH_GPIO_11", "n/a", + "GPIO_136", "n/a", "n/a", "n/a", "ISH_GPIO_12", "n/a", + "GPIO_137", "n/a", "n/a", "n/a", "ISH_GPIO_13", "n/a", + "GPIO_138", "n/a", "SIO_UART3_RXD", "ISH_UART0_RXD", "ISH_GPIO_14", "SATA_GP0", + "GPIO_139", "n/a", "SIO_UART3_TXD", "ISH_UART0_TXD", "ISH_GPIO_15", "SATA_GP1", + "GPIO_140", "n/a", "SIO_UART3_RTS_N", "ISH_UART0_RTS_N", "n/a", "SATA_DEVSLP0", + "GPIO_141", "n/a", "SIO_UART3_CTS_N", "ISH_UART0_CTS_N", "n/a", "SATA_DEVSLP1", + "GPIO_142", "n/a", "SIO_SPI_1_CLK", "ISH_SPI_0_CLK", "n/a", "SATA_LEDN", + "GPIO_143", "n/a", "SIO_SPI_1_FS0", "ISH_SPI_0_FS0", "JTAG2_TCK", "n/a", + "GPIO_144", "n/a", "SIO_SPI_1_FS1", "ISH_SPI_0_FS1", "PNL1_VDDEN", "n/a", + "GPIO_145", "n/a", "SIO_SPI_1_RXD", "ISH_SPI_0_RXD", "PNL1_BKLTEN", "n/a", + "GPIO_146", "n/a", "SIO_SPI_1_TXD", "ISH_SPI_0_TXD", "PNL1_BKLTCTL", "n/a", + "GPIO_147", "LPC_SERIRQ", "ESPI_RESET_N", "n/a", "n/a", "n/a", + "GPIO_148", "LPC_CLKOUT0", "ESPI_CLK", "n/a", "n/a", "n/a", + "GPIO_149", "LPC_CLKOUT1", "n/a", "n/a", "n/a", "n/a", + "GPIO_150", "LPC_AD0", "ESPI_IO_0", "n/a", "n/a", "n/a", + "GPIO_151", "LPC_AD1", "ESPI_IO_1", "n/a", "n/a", "n/a", + "GPIO_152", "LPC_AD2", "ESPI_IO_2", "n/a", "n/a", "n/a", + "GPIO_153", "LPC_AD3", "ESPI_IO_3", "n/a", "n/a", "n/a", + "GPIO_154", "LPC_CLKRUN_N", "n/a", "n/a", "n/a", "n/a", + "GPIO_155", "LPC_FRAME_N", "ESPI_CS_N", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_north = { + .display = "----- GPIO Group North -----", + .pad_count = ARRAY_SIZE(glk_group_north_names) / 6, + .func_count = 6, + .pad_names = glk_group_north_names, +}; + +static const struct gpio_group *const glk_community_north_groups[] = { + &glk_group_north, +}; + +static const struct gpio_community glk_community_north = { + .name = "--- GPIO Community North ---", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(glk_community_north_groups), + .groups = glk_community_north_groups, +}; + +static const char *const glk_group_audio_names[] = { + "GPIO_156", "AVS_I2S0_MCLK", "n/a", "n/a", + "GPIO_157", "AVS_I2S0_BCLK", "n/a", "n/a", + "GPIO_158", "AVS_I2S0_WS_SYNC", "n/a", "n/a", + "GPIO_159", "AVS_I2S0_SDI", "n/a", "n/a", + "GPIO_160", "AVS_I2S0_SDO", "n/a", "n/a", + "GPIO_161", "AVS_I2S1_MCLK", "n/a", "n/a", + "GPIO_162", "AVS_I2S1_BCLK", "n/a", "CNV_BT_I2S_BCLK", + "GPIO_163", "AVS_I2S1_WS_SYNC", "n/a", "CNV_BT_I2S_WS_SYNC", + "GPIO_164", "AVS_I2S1_SDI", "n/a", "CNV_BT_I2S_SDI", + "GPIO_165", "AVS_I2S1_SDO", "n/a", "CNV_BT_I2S_SDO", + "GPIO_166", "AVS_HDA_BCLK", "AVS_I2S2_BCLK", "n/a", + "GPIO_167", "AVS_HDA_WS_SYNC", "AVS_I2S2_WS_SYNC", "n/a", + "GPIO_168", "AVS_HDA_SDI", "AVS_I2S2_SDI", "n/a", + "GPIO_169", "AVS_HDA_SDO", "AVS_I2S2_SDO", "n/a", + "GPIO_170", "AVS_HDA_RST_N", "AVS_I2S1_MCLK", "n/a", + "GPIO_171", "AVS_DMIC_CLK_A1", "n/a", "n/a", + "GPIO_172", "AVS_DMIC_CLK_B1", "n/a", "n/a", + "GPIO_173", "AVS_DMIC_DATA_1", "n/a", "n/a", + "GPIO_174", "AVS_DMIC_CLK_AB2", "n/a", "n/a", + "GPIO_175", "AVS_DMIC_DATA_2", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_audio = { + .display = "----- GPIO Group Audio -----", + .pad_count = ARRAY_SIZE(glk_group_audio_names) / 4, + .func_count = 4, + .pad_names = glk_group_audio_names, +}; + +static const struct gpio_group *const glk_community_audio_groups[] = { + &glk_group_audio, +}; + +static const struct gpio_community glk_community_audio = { + .name = "--- GPIO Community Audio ---", + .pcr_port_id = 0xc9, + .group_count = ARRAY_SIZE(glk_community_audio_groups), + .groups = glk_community_audio_groups, +}; + +static const char *const glk_group_scc_names[] = { + "GPIO_176", "SMB_ALERT_N", "n/a", "n/a", + "GPIO_177", "SMB_CLK", "SIO_I2C7_SCL", "n/a", + "GPIO_178", "SMB_DATA", "SIO_I2C7_SDA", "n/a", + "GPIO_187", "SDCARD_LVL_WP", "n/a", "n/a", + "GPIO_179", "SDCARD_CLK", "n/a", "n/a", + "GPIO_180", "SDCARD_CLK_FB", "n/a", "n/a", + "GPIO_181", "SDCARD_D0", "n/a", "n/a", + "GPIO_182", "SDCARD_D1", "n/a", "n/a", + "GPIO_183", "SDCARD_D2", "n/a", "n/a", + "GPIO_184", "SDCARD_D3", "n/a", "n/a", + "GPIO_185", "SDCARD_CMD", "n/a", "n/a", + "GPIO_186", "SDCARD_CD_N", "n/a", "n/a", + "GPIO_188", "SDCARD_PWR_DWN_N", "n/a", "n/a", + "GPIO_210", "n/a", "n/a", "n/a", + "GPIO_189", "OSC_CLK_OUT_0", "n/a", "n/a", + "GPIO_190", "OSC_CLK_OUT_1", "n/a", "n/a", + "GPIO_191", "CNV_BRI_DT", "n/a", "SIO_UART1_RTS_N", + "GPIO_192", "CNV_BRI_RST", "n/a", "SIO_UART1_RXD", + "GPIO_193", "CNV_RGI_DT", "n/a", "SIO_UART1_TXD", + "GPIO_194", "CNV_RGI_RST", "n/a", "SIO_UART1_CTS_N", + "GPIO_195", "CNV_RF_RESET_N", "n/a", "AVS_I2S1_WS_SYNC", + "GPIO_196", "XTAL_CLKREQ", "n/a", "AVS_I2S1_SDO", + "GPIO_197", "SDIO_CLK_FB", "n/a", "n/a", + "GPIO_198", "EMMC_CLK", "n/a", "n/a", + "GPIO_199", "EMMC_D0", "n/a", "n/a", + "GPIO_200", "EMMC_D1", "n/a", "n/a", + "GPIO_201", "EMMC_D2", "n/a", "n/a", + "GPIO_202", "EMMC_D3", "n/a", "n/a", + "GPIO_203", "EMMC_D4", "n/a", "n/a", + "GPIO_204", "EMMC_D5", "n/a", "n/a", + "GPIO_205", "EMMC_D6", "n/a", "n/a", + "GPIO_206", "EMMC_D7", "n/a", "n/a", + "GPIO_207", "EMMC_CMD", "n/a", "n/a", + "GPIO_208", "EMMC_RCLK", "n/a", "n/a", + "GPIO_209", "EMMC_RST_N", "n/a", "n/a", +}; + +static const struct gpio_group glk_group_scc = { + .display = "----- GPIO Group SCC -----", + .pad_count = ARRAY_SIZE(glk_group_scc_names) / 4, + .func_count = 4, + .pad_names = glk_group_scc_names, +}; + +static const struct gpio_group *const glk_community_scc_groups[] = { + &glk_group_scc, +}; + +static const struct gpio_community glk_community_scc = { + .name = "--- GPIO Community SCC ---", + .pcr_port_id = 0xc8, + .group_count = ARRAY_SIZE(glk_community_scc_groups), + .groups = glk_community_scc_groups, +}; + +static const struct gpio_community *const glk_communities[] = { + &glk_community_northwest, &glk_community_north, + &glk_community_audio, &glk_community_scc, +}; + static const char *const apl_group_north_names[] = { "*GPIO_0", "n/a", "n/a", "n/a", "n/a", "n/a", "*GPIO_1", "n/a", "n/a", "n/a", "n/a", "n/a", @@ -2284,6 +2588,12 @@ communities = apl_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_GLK: + community_count = ARRAY_SIZE(glk_communities); + communities = glk_communities; + pad_stepping = 16; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index de66811..4e8f76e 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -304,6 +304,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK, "Gemini Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, /* Intel GPUs */ @@ -399,6 +400,8 @@ "Intel(R) HD Graphics 530" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_530_2, "Intel(R) HD Graphics 530" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_605, + "Intel(R) UHD Graphics 605" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_1, "Intel(R) UHD Graphics 615" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_2, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 1c1841c..48d1198 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -263,8 +263,9 @@ #define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0f00 /* SOC Transaction Router */ #define PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC 0x0f1c #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 -#define CPUID_BAYTRAIL 0x30670 +#define CPUID_BAYTRAIL 0x30670 +#define PCI_DEVICE_ID_INTEL_GLK 0x31e8 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 #define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc @@ -342,6 +343,7 @@ #define PCI_DEVICE_ID_INTEL_HD_520 0x1916 #define PCI_DEVICE_ID_INTEL_HD_530_1 0x191B #define PCI_DEVICE_ID_INTEL_HD_530_2 0x1912 +#define PCI_DEVICE_ID_INTEL_UHD_605 0x3185 #define PCI_DEVICE_ID_INTEL_UHD_615_1 0x591C #define PCI_DEVICE_ID_INTEL_UHD_615_2 0x591E #define PCI_DEVICE_ID_INTEL_UHD_617 0x87C0 diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39..2dcdf25 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -122,6 +122,9 @@ case PCI_DEVICE_ID_INTEL_APL_LPC: p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); break; + case PCI_DEVICE_ID_INTEL_GLK: + p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); + break; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: -- To view, visit https://review.coreboot.org/c/coreboot/+/38909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63b9129a419facbcd2ca4819ba5946c40d7d5498 Gerrit-Change-Number: 38909 Gerrit-PatchSet: 1 Gerrit-Owner: Miroslaw Kocur <mirek190(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/denverton/uart.c: Clean up code
by Felix Singer (Code Review) 02 Mar '20

02 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37121 ) Change subject: soc/intel/denverton/uart.c: Clean up code ...................................................................... soc/intel/denverton/uart.c: Clean up code Since there is only one device ID used for UART, an array is not needed. Therefore, just save the device ID to the device variable. Change-Id: Icd325e1102a85cc175f6025519a47a1b64ee5b46 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/denverton_ns/uart.c 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37121/1 diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 28e0e2e..3b851ee 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -57,15 +57,10 @@ .enable = DEVICE_NOOP }; -static const unsigned short uart_ids[] = { - PCI_DEVICE_ID_INTEL_DENVERTON_HSUART, - 0 -}; - static const struct pci_driver uart_driver __pci_driver = { .ops = &uart_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = uart_ids + .device = PCI_DEVICE_ID_INTEL_DENVERTON_HSUART }; static void hide_hsuarts(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd325e1102a85cc175f6025519a47a1b64ee5b46 Gerrit-Change-Number: 37121 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/denverton: Move PCI IDs to pci_ids.h
by Felix Singer (Code Review) 02 Mar '20

02 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37120 ) Change subject: soc/intel/denverton: Move PCI IDs to pci_ids.h ...................................................................... soc/intel/denverton: Move PCI IDs to pci_ids.h This patch moves the PCI ID definitions to pci_ids.h file and replaces every occurrence with the new names. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 337018 Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/include/device/pci_ids.h M src/soc/intel/denverton_ns/csme_ie_kt.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/denverton_ns/uart.c M src/soc/intel/denverton_ns/xhci.c 10 files changed, 45 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/37120/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 18d6f60..c7b87b0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2675,6 +2675,40 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 +/* Intel Denverton (Atom C3000 family) */ +#define PCI_DEVICE_ID_INTEL_DENVERTON_SA 0x1980 +#define PCI_DEVICE_ID_INTEL_DENVERTONAD_SA 0x1995 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP0 0x19a4 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP1 0x19a5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP2 0x19a6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP3 0x19a7 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP4 0x19a8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP5 0x19a9 +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP6 0x19aa +#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP7 0x19ab +#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS 0x19ac +#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1 0x19b2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2 0x19c2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 +#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_1 0x19d1 +#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_2 0x19d2 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_1 0x19d3 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_2 0x19d4 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT 0x19d5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_3 0x19d6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_HSUART 0x19d8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_1 0x19e5 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_2 0x19e6 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT 0x19e8 +#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_3 0x19e9 +#define PCI_DEVICE_ID_INTEL_DENVERTON_EMMC 0x19db +#define PCI_DEVICE_ID_INTEL_DENVERTON_LPC 0x19dc +#define PCI_DEVICE_ID_INTEL_DENVERTON_P2SB 0x19dd +#define PCI_DEVICE_ID_INTEL_DENVERTON_PMC 0x19de +#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY 0x19df +#define PCI_DEVICE_ID_INTEL_DENVERTON_SPI 0x19e0 +#define PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB 0x19e1 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index 5967840..2b730e9 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -77,8 +77,8 @@ }; static const unsigned short pci_device_ids[] = { - ME_MEKT_DEVID, /* DVN CSME KT */ - IE_MEKT_DEVID, /* DVN IE KT */ + PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT, + PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT, 0 }; diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index faa4d92..a300fd4 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -158,46 +158,4 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define SA_DEVID 0x1980 -#define SA_DEVID_DNVAD 0x1995 -#define SOC_DEVID SA_DEVID -#define RAS_DEVID 0x19a1 -#define RCEC_DEVID 0x19a2 -#define VRP2_DEVID 0x19a3 -#define PCIE_PORT1_DEVID 0x19a4 -#define PCIE_PORT2_DEVID 0x19a5 -#define PCIE_PORT3_DEVID 0x19a6 -#define PCIE_PORT4_DEVID 0x19a7 -#define PCIE_PORT5_DEVID 0x19a8 -#define PCIE_PORT6_DEVID 0x19a9 -#define PCIE_PORT7_DEVID 0x19aa -#define PCIE_PORT8_DEVID 0x19ab -#define SMBUS2_DEVID 0x19ac -#define AHCI_DEVID 0x19b2 -#define AHCI2_DEVID 0x19c2 -#define XHCI_DEVID 0x19d0 -#define VRP0_DEVID 0x19d1 -#define VRP1_DEVID 0x19d2 -#define ME_HECI1_DEVID 0x19d3 -#define ME_HECI2_DEVID 0x19d4 -#define ME_IEDR_DEVID 0x19ea -#define ME_MEKT_DEVID 0x19d5 -#define ME_HECI3_DEVID 0x19d6 -#define HSUART_DEVID 0x19d8 -#define HSUART1_DEVID HSUART_DEVID -#define HSUART2_DEVID HSUART_DEVID -#define HSUART3_DEVID HSUART_DEVID -#define IE_HECI1_DEVID 0x19e5 -#define IE_HECI2_DEVID 0x19e6 -#define IE_IEDR_DEVID 0x19e7 -#define IE_MEKT_DEVID 0x19e8 -#define IE_HECI3_DEVID 0x19e9 -#define MMC_DEVID 0x19db -#define LPC_DEVID 0x19dc -#define P2SB_DEVID 0x19dd -#define PMC_DEVID 0x19de -#define SMBUS_DEVID 0x19df -#define SPI_DEVID 0x19e0 -#define NPK_DEVID 0x19e1 - #endif /* _DENVERTON_NS_PCI_DEVS_H_ */ diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 123fb24..6481cbe 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -324,7 +324,7 @@ static const struct pci_driver lpc_driver __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = LPC_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_LPC, }; static void finalize_chipset(void *unused) diff --git a/src/soc/intel/denverton_ns/npk.c b/src/soc/intel/denverton_ns/npk.c index 0404893..631aac7 100644 --- a/src/soc/intel/denverton_ns/npk.c +++ b/src/soc/intel/denverton_ns/npk.c @@ -46,5 +46,5 @@ static const struct pci_driver pch_pmc __pci_driver = { .ops = &pmc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = NPK_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB, }; diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 8b52087..cbb9a4e 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -113,5 +113,5 @@ static const struct pci_driver pch_pmc __pci_driver = { .ops = &pmc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PMC_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_PMC, }; diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index ddb8b02..d53d553 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -74,8 +74,8 @@ }; static const unsigned short pci_device_ids[] = { - AHCI_DEVID, /* DVN SATA AHCI */ - AHCI2_DEVID, /* DVN SATA2 AHCI */ + PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1, + PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2, 0 }; diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 00d5228..50f25c0 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -345,8 +345,8 @@ /* IDs for System Agent device of Intel Denverton SoC */ static const unsigned short systemagent_ids[] = { - SA_DEVID, /* DVN System Agent */ - SA_DEVID_DNVAD, /* DVN-AD System Agent */ + PCI_DEVICE_ID_INTEL_DENVERTON_SA, + PCI_DEVICE_ID_INTEL_DENVERTONAD_SA, 0 }; diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 50f8a29..28e0e2e 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -58,7 +58,7 @@ }; static const unsigned short uart_ids[] = { - HSUART_DEVID, /* HSUART 0/1/2 */ + PCI_DEVICE_ID_INTEL_DENVERTON_HSUART, 0 }; diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index 0a4b3b1..a0ed6ba 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -47,5 +47,5 @@ static const struct pci_driver pch_usb_xhci __pci_driver = { .ops = &usb_xhci_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = XHCI_DEVID, + .device = PCI_DEVICE_ID_INTEL_DENVERTON_XHCI, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445 Gerrit-Change-Number: 37120 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/amdfwtool: Clarify APOB NV requirements
by Marshall Dawson (Code Review) 02 Mar '20

02 Mar '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38690 ) Change subject: util/amdfwtool: Clarify APOB NV requirements ...................................................................... util/amdfwtool: Clarify APOB NV requirements Relocate the first size check. This was automatically continuing and not looking for the caller incorrectly passing a destination. New information indicates that the APOB_NV should always be present in the system. Augment the missing size check to inferring whether a missing size is valid, as in the case of older products, or truly missing when it's needed. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e --- M util/amdfwtool/amdfwtool.c 1 file changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/38690/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index d5c63de..c41da58 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -808,6 +808,17 @@ return 0; } +static int find_bios_entry(amd_bios_type type) +{ + int i; + + for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) { + if (amd_bios_table[i].type == type) + return i; + } + return -1; +} + static void integrate_bios_firmwares(context *ctx, bios_directory_table *biosdir, bios_directory_table *biosdir2, @@ -817,6 +828,7 @@ ssize_t bytes; unsigned int i, count; int level; + int apob_idx; /* This function can create a primary table, a secondary table, or a * flattened table which contains all applicable types. These if-else @@ -843,9 +855,6 @@ fw_table[i].type != AMD_BIOS_L2_PTR && fw_table[i].type != AMD_BIOS_BIN)) continue; - /* APOB_NV needs a size, else no S3 and skip item */ - if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size) - continue; /* BIOS Directory items may have additional requirements */ @@ -857,6 +866,19 @@ exit(1); } } + /* APOB_NV needs a size, else no choice but to skip the item */ + if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size) { + /* Attempt to determine whether this is an error */ + apob_idx = find_bios_entry(AMD_BIOS_APOB); + if (apob_idx < 0 || !fw_table[apob_idx].dest) { + /* APOV NV not expected to be used */ + continue; + } else { + printf("Error: APOB NV must have a size\n"); + free(ctx->rom); + exit(1); + } + } /* APOB_DATA needs destination */ if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e Gerrit-Change-Number: 38690 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add PCI ID for Dali xHCI
by Marshall Dawson (Code Review) 02 Mar '20

02 Mar '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38169 ) Change subject: soc/amd/picasso: Add PCI ID for Dali xHCI ...................................................................... soc/amd/picasso: Add PCI ID for Dali xHCI soc//picasso is intended to be forward-compatible with the Dali APU, a Family 17h Models 20h-2Fh product. Add the one new device ID it has. See PPR document #55772 (still NDA only) for more information. Change-Id: I7e9b90bb00ae6f4a121f10b1467d2ca398ac860c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/amd/picasso/usb.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/38169/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index bd5b3a5..52c6035 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -459,6 +459,7 @@ #define PCI_DEVICD_ID_AMD_PCO_ACP 0x15e2 #define PCI_DEVICE_ID_AMD_PCO_XHCI0 0x15e0 #define PCI_DEVICE_ID_AMD_PCO_XHCI1 0x15e1 +#define PCI_DEVICE_ID_AMD_DALI_XHCI 0x15e5 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 80e960c..faea3c3 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -48,6 +48,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_PCO_XHCI0, PCI_DEVICE_ID_AMD_PCO_XHCI1, + PCI_DEVICE_ID_AMD_DALI_XHCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/38169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e9b90bb00ae6f4a121f10b1467d2ca398ac860c Gerrit-Change-Number: 38169 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/acpi_s3: Remove trailing dots from debug message
by Paul Menzel (Code Review) 02 Mar '20

02 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30806 Change subject: x86/acpi_s3: Remove trailing dots from debug message ...................................................................... x86/acpi_s3: Remove trailing dots from debug message The dot is not needed, as it is no sentence and followed by a line break. Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/arch/x86/acpi_s3.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30806/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ad9fe00..07c0332 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -34,10 +34,10 @@ { if (acpi_slp_type < 0) { if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume.\n"); + printk(BIOS_DEBUG, "S3 Resume\n"); acpi_slp_type = ACPI_S3; } else { - printk(BIOS_DEBUG, "Normal boot.\n"); + printk(BIOS_DEBUG, "Normal boot\n"); acpi_slp_type = ACPI_S0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Gerrit-Change-Number: 30806 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: lint/lint-extended-007-checkpatch: Fix obsolete paths
by HAOUAS Elyes (Code Review) 02 Mar '20

02 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39171 ) Change subject: lint/lint-extended-007-checkpatch: Fix obsolete paths ...................................................................... lint/lint-extended-007-checkpatch: Fix obsolete paths Change-Id: I7a6ca083e79d285b8c596631f21ccdfe2777e20e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/lint/lint-extended-007-checkpatch 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39171/1 diff --git a/util/lint/lint-extended-007-checkpatch b/util/lint/lint-extended-007-checkpatch index 4610b5e..c221d4a 100755 --- a/util/lint/lint-extended-007-checkpatch +++ b/util/lint/lint-extended-007-checkpatch @@ -21,9 +21,7 @@ src/drivers/dec src/drivers/gic src/drivers/ti \ src/ec/purism \ src/include/boot src/include/superio src/include/sys \ -src/mainboard/adlink src/mainboard/linutop \ -src/mainboard/purism src/mainboard/ti \ -src/soc/rdc \ +src/mainboard/adlink src/mainboard/purism src/mainboard/ti \ src/superio/acpi src/superio/common \ " -- To view, visit https://review.coreboot.org/c/coreboot/+/39171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6ca083e79d285b8c596631f21ccdfe2777e20e Gerrit-Change-Number: 39171 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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