coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: lib/reg_script: Add cast to fix compilation on x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48166 ) Change subject: lib/reg_script: Add cast to fix compilation on x86_64 ...................................................................... lib/reg_script: Add cast to fix compilation on x86_64 Change-Id: Ia713e7dbe8c75b764f7a4ef1a029e64fb2d321fb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/lib/reg_script.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48166/1 diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index e0ae68c..bad9d9c 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -150,11 +150,11 @@ switch (step->size) { case REG_SCRIPT_SIZE_8: - return read8((u8 *)step->reg); + return read8((u8 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_16: - return read16((u16 *)step->reg); + return read16((u16 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_32: - return read32((u32 *)step->reg); + return read32((u32 *)(uintptr_t)step->reg); } return 0; } @@ -165,13 +165,13 @@ switch (step->size) { case REG_SCRIPT_SIZE_8: - write8((u8 *)step->reg, step->value); + write8((u8 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_16: - write16((u16 *)step->reg, step->value); + write16((u16 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_32: - write32((u32 *)step->reg, step->value); + write32((u32 *)(uintptr_t)step->reg, step->value); break; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia713e7dbe8c75b764f7a4ef1a029e64fb2d321fb Gerrit-Change-Number: 48166 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/zork: Mark RW_MRC_CACHE as "Preserve"
by Martin Roth (Code Review) 01 Dec '20

01 Dec '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47776 ) Change subject: mb/google/zork: Mark RW_MRC_CACHE as "Preserve" ...................................................................... mb/google/zork: Mark RW_MRC_CACHE as "Preserve" AGESA checks to make sure that the firmware version reading the MRC cache is the same version that wrote it, so it doesn't need to be erased during a firmware update. BUG=b:173724014 TEST=Flash firmware to DUT, update firmware, check RW_MRC_CACHE was not erased BRANCH=Zork Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ice3d1d467c25366b7ef678cd6481d043f62644ca --- M src/mainboard/google/zork/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47776/1 diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index 7c2b95b..be43e8a 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -1,6 +1,6 @@ FLASH@0xFF000000 16M { SI_BIOS { - RW_MRC_CACHE 64K + RW_MRC_CACHE(PRESERVE) 64K RW_SECTION_A 3M { VBLOCK_A 8K FW_MAIN_A(CBFS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice3d1d467c25366b7ef678cd6481d043f62644ca Gerrit-Change-Number: 47776 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: cpu/x86/sipi: Add x86_64 support
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45187 ) Change subject: cpu/x86/sipi: Add x86_64 support ...................................................................... cpu/x86/sipi: Add x86_64 support Enter long mode on secondary APs. Tested on Lenovo T410 with additional x86_64 patches. Tested on HP Z220 with additional x86_64 patches. Still boots on x86_32. Change-Id: I53eae082123d1a12cfa97ead1d87d84db4a334c0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/sipi_vector.S 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45187/1 diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 65c0fdc..7025517 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -16,7 +16,12 @@ #endif #include <cpu/x86/msr.h> +#if defined(__RAMSTAGE__) +#include <arch/ram_segs.h> +#else #include <arch/rom_segs.h> +#endif + setup_longmode: /* Get page table address */ @@ -42,7 +47,12 @@ movl %eax, %cr0 /* use long jump to switch to 64-bit code segment */ +#if defined(__RAMSTAGE__) + ljmp $RAM_CODE_SEG64, $__longmode_start +#else ljmp $ROM_CODE_SEG64, $__longmode_start + +#endif .code64 __longmode_start: diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7..cde5532 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -5,6 +5,8 @@ #include <cpu/x86/msr.h> #include <arch/ram_segs.h> +#define __RAMSTAGE__ + /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into * C code. */ @@ -192,11 +194,24 @@ mov %eax, %cr4 #endif +#ifdef __x86_64__ + /* entry64.inc preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + + mov %rsi, %rdi /* cpu_num */ + + movl c_handler, %eax + call *%rax +#else /* c_handler(cpu_num), preserve proper stack alignment */ sub $12, %esp push %esi /* cpu_num */ + mov c_handler, %eax call *%eax +#endif + + halt_jump: hlt jmp halt_jump -- To view, visit https://review.coreboot.org/c/coreboot/+/45187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53eae082123d1a12cfa97ead1d87d84db4a334c0 Gerrit-Change-Number: 45187 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: mb/kontron/mal10: Use the system library for headers
by Felix Singer (Code Review) 01 Dec '20

01 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48141 ) Change subject: mb/kontron/mal10: Use the system library for headers ...................................................................... mb/kontron/mal10: Use the system library for headers Use the system library for header files instead of relative filesystem paths. Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I0b356d0188f104d7c49571ce5c8fe65e79589123 --- M src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c M src/mainboard/kontron/mal10/variants/mal10/gpio.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/48141/1 diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c index f1f93bf..674b209 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "include/carrier/gpio.h" +#include <carrier/gpio.h> static const struct pad_config gpio_table[] = { PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME), diff --git a/src/mainboard/kontron/mal10/variants/mal10/gpio.c b/src/mainboard/kontron/mal10/variants/mal10/gpio.c index 1e88e38..3986776 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/gpio.c +++ b/src/mainboard/kontron/mal10/variants/mal10/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "include/variant/gpio.h" +#include <variant/gpio.h> static const struct pad_config gpio_table[] = { /* SPI */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b356d0188f104d7c49571ce5c8fe65e79589123 Gerrit-Change-Number: 48141 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/kontron/mal10/Kconfig: Reorder selects alphabetically
by Felix Singer (Code Review) 01 Dec '20

01 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48140 ) Change subject: mb/kontron/mal10/Kconfig: Reorder selects alphabetically ...................................................................... mb/kontron/mal10/Kconfig: Reorder selects alphabetically Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: Id78c478a1252099cd1aa42c62efd406e7e1c5ef8 --- M src/mainboard/kontron/mal10/Kconfig 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48140/1 diff --git a/src/mainboard/kontron/mal10/Kconfig b/src/mainboard/kontron/mal10/Kconfig index 1705b91..f53746d 100644 --- a/src/mainboard/kontron/mal10/Kconfig +++ b/src/mainboard/kontron/mal10/Kconfig @@ -2,18 +2,18 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_NCT7802Y + select EC_KONTRON_KEMPLD select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT - select SOC_INTEL_APOLLOLAKE - select BOARD_ROMSIZE_KB_16384 - select ONBOARD_VGA_IS_PRIMARY - select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_CRB_TPM - select EC_KONTRON_KEMPLD - select DRIVERS_I2C_NCT7802Y + select MAINBOARD_HAS_LIBGFXINIT + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_APOLLOLAKE config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/48140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id78c478a1252099cd1aa42c62efd406e7e1c5ef8 Gerrit-Change-Number: 48140 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: MAINTAINERS: Add missing trailing slashes
by Felix Singer (Code Review) 01 Dec '20

01 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48137 ) Change subject: MAINTAINERS: Add missing trailing slashes ...................................................................... MAINTAINERS: Add missing trailing slashes Add missing trailing slashes so that gerrit recognizes maintainers correctly. Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I35fcaf41617247e2b86cd6ddd7ee1b319a695797 --- M MAINTAINERS 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/48137/1 diff --git a/MAINTAINERS b/MAINTAINERS index 4f643b2..880c4aa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -233,19 +233,19 @@ GETAC P470 MAINBOARD M: Patrick Georgi <patrick(a)georgi.software> S: Maintained -F: src/mainboard/getac/p470 +F: src/mainboard/getac/p470/ GIGABYTE GA-G41M-ES2L MAINBOARD M: Damien Zammit <damien(a)zamaudio.com> S: Odd Fixes -F: src/mainboard/gigabyte/ga-g41m-es2l +F: src/mainboard/gigabyte/ga-g41m-es2l/ GIGABYTE GA-H61M SERIES MAINBOARDS M: Angel Pons <th3fanbus(a)gmail.com> S: Maintained -F: src/mainboard/gigabyte/ga-h61m-series +F: src/mainboard/gigabyte/ga-h61m-series/ @@ -273,7 +273,7 @@ INTEL D510MO MAINBOARD M: Damien Zammit <damien(a)zamaudio.com> S: Odd Fixes -F: src/mainboard/intel/d510mo +F: src/mainboard/intel/d510mo/ INTEL STRAGO MAINBOARD M: Hannah Williams <hannah.williams(a)intel.com> @@ -314,7 +314,7 @@ M: Piotr Król <piotr.krol(a)3mdeb.com> M: Michał Żygowski <michal.zygowski(a)3mdeb.com> S: Maintained -F: src/mainboard/libretrend/lt1000 +F: src/mainboard/libretrend/lt1000/ OCP DELTALAKE MAINBOARD @@ -325,7 +325,7 @@ M: Ryback Hung <<Ryback.Hung(a)quantatw.com> M: Bryant Ou <Bryant.Ou(a)quantatw.com> S: Supported -F: src/mainboard/ocp/deltalake +F: src/mainboard/ocp/deltalake/ OCP TIOGAPASS MAINBOARD M: Jonathan Zhang <jonzhang(a)fb.com> @@ -335,7 +335,7 @@ M: Ryback Hung <<Ryback.Hung(a)quantatw.com> M: Bryant Ou <Bryant.Ou(a)quantatw.com> S: Maintained -F: src/mainboard/ocp/tiogapass +F: src/mainboard/ocp/tiogapass/ @@ -375,14 +375,14 @@ M: Christian Walter <christian.walter(a)9elements.com> M: Patrick Rudolph <patrick.rudolph(a)9elements.com> S: Maintained -F: src/mainboard/prodrive/hermes +F: src/mainboard/prodrive/hermes/ PURISM MAINBOARDS M: Matt DeVillier <matt.devillier(a)puri.sm> S: Supported -F: src/mainboard/purism +F: src/mainboard/purism/ @@ -556,8 +556,8 @@ M: Felix Held <felix-coreboot(a)felixheld.de> M: Jason Glenesk <jason.glenesk(a)gmail.com> S: Maintained -F: src/soc/amd/picasso -F: src/vendorcode/amd/fsp/picasso +F: src/soc/amd/picasso/ +F: src/vendorcode/amd/fsp/picasso/ INTEL APOLLOLAKE_SOC M: Andrey Petrov <andrey.petrov(a)gmail.com> @@ -569,8 +569,8 @@ M: Michał Żygowski <michal.zygowski(a)3mdeb.com> M: Frans Hendriks <fhendriks(a)eltan.com> S: Maintained -F: /src/soc/intel/braswell -F: /src/vendorcode/intel/fsp/fsp1_1/braswell +F: /src/soc/intel/braswell/ +F: /src/vendorcode/intel/fsp/fsp1_1/braswell/ INTEL Xeon Sacalable Processor Family M: Jonathan Zhang <jonzhang(a)fb.com> @@ -581,13 +581,13 @@ M: Bryant Ou <Bryant.Ou(a)quantatw.com> S: Supported F: src/soc/intel/xeon_sp -F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp -F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp +F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ +F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/ MEDIATEK SOCS M: Hung-Te Lin <hungte(a)chromium.org> S: Supported -F: src/soc/mediatek +F: src/soc/mediatek/ ORPHANED ARM SOCS S: Orphaned @@ -615,13 +615,13 @@ EXTERNAL PAYLOADS INTEGRATION M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> M: Martin Roth <gaumless(a)gmail.com> -F: payloads/external +F: payloads/external/ LINUXBOOT PAYLOAD INTEGRATION M: Christian Walter <christian.walter(a)9elements.com> M: Marcello Sylvester Bauer <info(a)marcellobauer.com> S: Supported -F: payloads/external/LinuxBoot +F: payloads/external/LinuxBoot/ ################################################################################ # Utilities @@ -751,7 +751,7 @@ M: Christian Walter <christian.walter(a)9elements.com> S: Supported F: src/drivers/*/tpm/ -F: src/security/tpm +F: src/security/tpm/ SUPERIOS & SUPERIOTOOL M: Felix Held <felix-coreboot(a)felixheld.de> @@ -769,7 +769,7 @@ M: Frans Hendriks <fhendriks(a)eltan.com> M: Wim Vervoorn <wvervoorn(a)eltan.com> S: Maintained -F: src/vendorcode/eltan +F: src/vendorcode/eltan/ MISSING: TIMERS / DELAYS -- To view, visit https://review.coreboot.org/c/coreboot/+/48137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35fcaf41617247e2b86cd6ddd7ee1b319a695797 Gerrit-Change-Number: 48137 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

6 6

Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 8 information
by Tim Chu (Code Review) 01 Dec '20

01 Dec '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47893 ) Change subject: mb/ocp/deltalake: Update SMBIOS type 8 information ...................................................................... mb/ocp/deltalake: Update SMBIOS type 8 information Update port connector information for Delta Lake. Tested=Execute "dmidecode -t 8" to check all the information of SMBIOS type 8 is correct. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47893/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 52c55b8..3f9e1c9 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -155,6 +155,38 @@ } } +static const struct port_information SMBIOS_type8_info[] = { + /* + * Port Information fields: + * Internal Reference Designator, + * Internal Connector Type, + * External Reference Designator, + * External Connector_Type, + * Port Type + */ + { + "JCN18 - CPU MIPI60", + CONN_OTHER, + "", + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "JCN32 - TPM_CONN", + CONN_OTHER, + "", + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "JCN7 - USB type C", + CONN_USB_TYPE_C, + "", + CONN_NONE, + TYPE_USB + }, +}; + static int create_smbios_type9(int *handle, unsigned long *current) { int index; @@ -256,6 +288,13 @@ { int len = 0; + // add port information + len += smbios_write_type8( + current, handle, + SMBIOS_type8_info, + ARRAY_SIZE(SMBIOS_type8_info) + ); + len += create_smbios_type9(handle, current); return len; -- To view, visit https://review.coreboot.org/c/coreboot/+/47893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f Gerrit-Change-Number: 47893 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: ec/google/chromeec/acpi: Make OperationRegion brace align
by Subrata Banik (Code Review) 01 Dec '20

01 Dec '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48149 ) Change subject: ec/google/chromeec/acpi: Make OperationRegion brace align ...................................................................... ec/google/chromeec/acpi: Make OperationRegion brace align Inject TAB to make OperationRegion closing brace align with opening brace. Change-Id: Idb9f23cf6a2c249fb1fd02f4a2ac314d4f7e180b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/48149/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index d12274f..ce2455f 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -82,7 +82,7 @@ Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power -} + } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) OperationRegion (EMEM, EmbeddedControl, -- To view, visit https://review.coreboot.org/c/coreboot/+/48149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb9f23cf6a2c249fb1fd02f4a2ac314d4f7e180b Gerrit-Change-Number: 48149 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP
by Subrata Banik (Code Review) 01 Dec '20

01 Dec '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48131 ) Change subject: mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP ...................................................................... mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ hence remove the unused GPIO. Wrong GPIO configuration is causing platform reboot issue on ADLRVP with Chrome SKU. Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/include/baseboard/ec.h M src/mainboard/intel/adlrvp/include/baseboard/gpio.h 2 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/48131/1 diff --git a/src/mainboard/intel/adlrvp/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/include/baseboard/ec.h index 4303faf..c018299 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/ec.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/ec.h @@ -56,9 +56,6 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE -/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ -#define EC_ENABLE_SYNC_IRQ - /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h index b61276c..de0adf6 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h @@ -12,7 +12,4 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK -/* EC sync IRQ */ -#define EC_SYNC_IRQ GPP_A15_IRQ - #endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc Gerrit-Change-Number: 48131 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/intel/adlrvp: Add ASL support for WFC annd UFC
by Varshit B Pandya (Code Review) 01 Dec '20

01 Dec '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47497 ) Change subject: mb/intel/adlrvp: Add ASL support for WFC annd UFC ...................................................................... mb/intel/adlrvp: Add ASL support for WFC annd UFC 1. Add 2 Ports and 2 Endpoints 2. Add support for OVTI5675 WFC Cam is on I2C5 and UFC is on I2C1 Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2 --- A src/mainboard/intel/adlrvp/acpi/mipi_camera.asl M src/mainboard/intel/adlrvp/dsdt.asl 2 files changed, 523 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47497/1 diff --git a/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl new file mode 100644 index 0000000..b09f7ae --- /dev/null +++ b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl @@ -0,0 +1,520 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + One + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + One, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C1.CAM0, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C1) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(0,1) /* Clock 0, 19.2MHz */ + + /* Pull PWREN high */ + STXS(GPP_B23) + Sleep(2) /* reset pulse width */ + + /* Pull RST low */ + CTXS(GPP_R5) + Sleep(1) /* t2 */ + + /* Pull RST high */ + STXS(GPP_R5) + Sleep(1) /* t2 */ + + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(0) /* Clock 0 */ + + /* Pull RST low */ + CTXS(GPP_R5) + + /* Pull PWREN low */ + CTXS(GPP_B23) + + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + Name (_UID, 0x03) /* _UID: Unique ID */ + Name (_DDN, "DW AF DAC") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} + +Scope (\_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(1,1) /* Clock 1, 19.2MHz */ + + /* Pull PWREN high */ + STXS(GPP_E16) + Sleep(2) /* reset pulse width */ + + /* Pull RST low */ + CTXS(GPP_E15) + Sleep(1) /* t2 */ + + /* Pull RST high */ + STXS(GPP_E15) + Sleep(1) /* t2 */ + + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(1) /* Clock 1 */ + + /* Pull RST low */ + CTXS(GPP_E15) + + /* Pull PWREN low */ + CTXS(GPP_E16) + + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index d4fb7a4..6e7ccd1 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -27,6 +27,9 @@ #include <soc/intel/common/block/acpi/acpi/ipu.asl> } + /* Camera */ + #include <acpi/mipi_camera.asl> + #if CONFIG(CHROMEOS) /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/47497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2 Gerrit-Change-Number: 47497 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

4 10

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020