coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/tigerlake: Enable support for extended BIOS window
by Srinidhi N Kaushik (Code Review) 01 Dec '20

01 Dec '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48186 ) Change subject: soc/intel/tigerlake: Enable support for extended BIOS window ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I039155506380310cf867f5f8c5542278be40838a Gerrit-Change-Number: 48186 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Nov 2020 23:02:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Reorganize FMAP
by Furquan Shaikh (Code Review) 01 Dec '20

01 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48187 ) Change subject: mb/google/volteer: Reorganize FMAP ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5 Gerrit-Change-Number: 48187 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Nov 2020 23:02:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Enable support for extended BIOS window
by Furquan Shaikh (Code Review) 01 Dec '20

01 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48186 ) Change subject: soc/intel/tigerlake: Enable support for extended BIOS window ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I039155506380310cf867f5f8c5542278be40838a Gerrit-Change-Number: 48186 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Nov 2020 23:01:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/bsl6: Configure GPIOs using mainboard_ops
by Michael Niewöhner (Code Review) 30 Nov '20

30 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47850 ) Change subject: mb/kontron/bsl6: Configure GPIOs using mainboard_ops ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ab8d258c6f81c90d835cb8d07c6387d3de76d85 Gerrit-Change-Number: 47850 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Nov 2020 22:56:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Fix comment
by Felix Singer (Code Review) 30 Nov '20

30 Nov '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48008 ) Change subject: soc/intel/skylake: Fix comment ...................................................................... soc/intel/skylake: Fix comment mainboard_silicon_init_params() is *not* meant for configuring GPIOs. It should only be used to configure FSP options, which can not be configured elsewhere. Change-Id: Ia92d0d173af9c67600e93b473480967304772998 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/chip.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/48008/1 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 77ff78b..28cc1c1 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -432,7 +432,7 @@ soc_irq_settings(params); } -/* Mainboard GPIO Configuration */ +/* Mainboard FSP Configuration */ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/48008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia92d0d173af9c67600e93b473480967304772998 Gerrit-Change-Number: 48008 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/pgtblgen: Improve compatibility
by Patrick Georgi (Code Review) 30 Nov '20

30 Nov '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48004 ) Change subject: util/pgtblgen: Improve compatibility ...................................................................... util/pgtblgen: Improve compatibility Fix build on Debian/jessie Change-Id: I987e7a03441b40ab06ccd54a21e38aac81a1c28d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/pgtblgen/Makefile.inc M util/pgtblgen/pgtblgen.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/48004/1 diff --git a/util/pgtblgen/Makefile.inc b/util/pgtblgen/Makefile.inc index c4f3ef3..08fb620 100644 --- a/util/pgtblgen/Makefile.inc +++ b/util/pgtblgen/Makefile.inc @@ -14,6 +14,6 @@ $(PGTBLGEN): util/pgtblgen/pgtblgen.c printf " MAKE Creating PGTBLGEN tool\n" - $(HOSTCC) $< -I$(obj) -o $@ + $(HOSTCC) -std=c99 $< -I$(obj) -o $@ endif diff --git a/util/pgtblgen/pgtblgen.c b/util/pgtblgen/pgtblgen.c index 640d0ba..7ed98b2 100644 --- a/util/pgtblgen/pgtblgen.c +++ b/util/pgtblgen/pgtblgen.c @@ -9,6 +9,7 @@ #include <fcntl.h> #include <errno.h> #include <inttypes.h> +#include <getopt.h> static void usage(char *argv[]) { -- To view, visit https://review.coreboot.org/c/coreboot/+/48004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I987e7a03441b40ab06ccd54a21e38aac81a1c28d Gerrit-Change-Number: 48004 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Add chipset devicetree
by Felix Singer (Code Review) 30 Nov '20

30 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46314 ) Change subject: soc/intel/skylake: Add chipset devicetree ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/46314/6/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chipset.cb: https://review.coreboot.org/c/coreboot/+/46314/6/src/soc/intel/skylake/chip… PS6, Line 10: > device pci 07. […] Done https://review.coreboot.org/c/coreboot/+/46314/6/src/soc/intel/skylake/chip… PS6, Line 61: pch_spi > maybe fast_spi like in TGL? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Gerrit-Change-Number: 46314 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 30 Nov 2020 21:31:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Add chipset devicetree
by Michael Niewöhner (Code Review) 30 Nov '20

30 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46314 ) Change subject: soc/intel/skylake: Add chipset devicetree ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/46314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Gerrit-Change-Number: 46314 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 30 Nov 2020 21:28:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Add chipset devicetree
by Felix Singer (Code Review) 30 Nov '20

30 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46314 to look at the new patch set (#8). Change subject: soc/intel/skylake: Add chipset devicetree ...................................................................... soc/intel/skylake: Add chipset devicetree Set most of the devices to off to keep current behaviour. Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/Kconfig A src/soc/intel/skylake/chipset.cb 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/46314/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/46314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Gerrit-Change-Number: 46314 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common: Add weak function definitions to get ioapic IDs
by Jason Glenesk (Code Review) 30 Nov '20

30 Nov '20

Hello Jason Glenesk, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46326 to review the following change. Change subject: soc/amd/common: Add weak function definitions to get ioapic IDs ...................................................................... soc/amd/common: Add weak function definitions to get ioapic IDs Add weak definitions for soc_get_fch_ioapic_id() and soc_get_gnb_ioapic_id(). If not overriddden return CONFIG_MAX_CPUS and CONFIG_MAX_CPUS +1 respectively. BUG=b:167421913 TEST=Boot morphius to shell. Confirm weak function return values dumping MADT. BRANCH=Zork Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Change-Id: Ib6778bf5141df580759e8158010a63d6af77e8ae --- M src/soc/amd/common/block/cpu/Makefile.inc A src/soc/amd/common/block/cpu/cpu.c A src/soc/amd/common/block/include/amdblocks/cpu.h 3 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46326/1 diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index 395ab08..51e322d 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -6,3 +6,5 @@ romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/ap_exit_car.S romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S + +ramstage-y += cpu.c diff --git a/src/soc/amd/common/block/cpu/cpu.c b/src/soc/amd/common/block/cpu/cpu.c new file mode 100644 index 0000000..7d2d5c9 --- /dev/null +++ b/src/soc/amd/common/block/cpu/cpu.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <amdblocks/cpu.h> + +__weak uint8_t soc_get_fch_ioapic_id(void) +{ + return CONFIG_MAX_CPUS; +} + +__weak uint8_t soc_get_gnb_ioapic_id(void) +{ + return CONFIG_MAX_CPUS + 1; +} diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h new file mode 100644 index 0000000..7282161 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __AMDBLOCKS_CPU_H__ +#define __AMDBLOCKS_CPU_H__ + +#include <types.h> + +uint8_t soc_get_fch_ioapic_id(void); +uint8_t soc_get_gnb_ioapic_id(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6778bf5141df580759e8158010a63d6af77e8ae Gerrit-Change-Number: 46326 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020