coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: mb/intel/adlrvp: Configure Camera related GPIO as per schematics
by Varshit B Pandya (Code Review) 01 Dec '20

01 Dec '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47496 ) Change subject: mb/intel/adlrvp: Configure Camera related GPIO as per schematics ...................................................................... mb/intel/adlrvp: Configure Camera related GPIO as per schematics Configure RST and PWR_EN signals for both WFC and UFC Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> Change-Id: Ie416da373756b1c73472b8572f87930965a3d6ec --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 9 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/47496/1 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 9f96620..bf1dad2 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -26,8 +26,6 @@ PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* M.2 SSD_2 Reset */ PAD_CFG_GPO(GPP_H0, 1, PLTRST), - /* CAM1-IRQ */ - PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* CAM_STROBE */ PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Audio Codec INT N */ @@ -182,15 +180,6 @@ /* I2S0_RXD */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* I2S1_SCLK */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* I2S1_SFRM */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), - /* I2S1_TXD */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), - /* I2S1_RXD */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), - /* I2S2_SCLK */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SFRM */ @@ -273,6 +262,15 @@ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + + /* CAM1_RST */ + PAD_CFG_GPO(GPP_R5, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), }; void variant_configure_gpio_pads(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/47496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie416da373756b1c73472b8572f87930965a3d6ec Gerrit-Change-Number: 47496 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: mb/intel/adlrvp: Update GPIO configuration as per schematics
by Varshit B Pandya (Code Review) 01 Dec '20

01 Dec '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47495 ) Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ...................................................................... mb/intel/adlrvp: Update GPIO configuration as per schematics Configure I2C related GPIO as per ADL-P Schematics Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 12 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47495/1 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index f91b94f..9f96620 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -134,22 +134,16 @@ /* SPI_MOSI(2) */ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), - /* SPI_MIS0(0) */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* SPI_MIS0(1) */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* SPI_MIS0(2) */ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), - /* SPI_CLK(0) */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* SPI_CLK(1) */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* SPI_CLK(2) */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), - /* SPI_CS(0, 0) */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* SPI_CS(0, 1) */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPI_CS(1, 0) */ @@ -158,34 +152,26 @@ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), /* I2C_SCL(0) */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* I2C_SCL(1) */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* I2C_SCL(2) */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* I2C_SCL(3) */ + /* I2C_SCL(1) */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* I2C_SCL(5) */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - /* I2C_SCL(6) */ - PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), - /* I2C_SCL(7) */ - PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), /* I2C_SDA(0) */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* I2C_SDA(1) */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* I2C_SDA(2) */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* I2C_SDA(3) */ + /* I2C_SDA(1) */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* I2C_SDA(5) */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* I2C_SDA(6) */ - PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), - /* I2C_SDA(7) */ - PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), /* I2S0_SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), -- To view, visit https://review.coreboot.org/c/coreboot/+/47495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e Gerrit-Change-Number: 47495 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mainboard/intel/adlrvp: Enable PCH PCIE device over x1 slot
by Subrata Banik (Code Review) 01 Dec '20

01 Dec '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48080 ) Change subject: mainboard/intel/adlrvp: Enable PCH PCIE device over x1 slot ...................................................................... mainboard/intel/adlrvp: Enable PCH PCIE device over x1 slot List of changes: 1. Enable Root Port 8 aka 0:0x1c:7 2. Assign free running clock for RP8 3. Driven OEB 7:GPP_A7 and OEB 6:GPP_E5 low TEST=Able to detect PCIE SD card over x1 slot localhost ~ # dmesg | grep mmc [ 3.643755] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA [ 3.825201] mmc0: new ultra high speed DDR50 SDHC card at address 17f8 [ 3.835452] mmcblk0: mmc0:17f8 SE16G 14.4 GiB [ 3.849158] mmcblk0: p1 Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/gpio.c 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/48080/1 diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 80edb92..f2f768a 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -51,6 +51,12 @@ register "PcieClkSrcUsage[5]" = "0x5" register "PcieRpClkReqDetect[5]" = "1" + # Enable PCH PCIE RP 8 using free running CLK (0x80) + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieRpClkReqDetect[7]" = "1" + # Enable PCH PCIE RP 9 using CLK 1 register "PcieRpEnable[8]" = "1" register "PcieClkSrcClkReq[1]" = "1" @@ -245,7 +251,7 @@ device pci 1c.4 on end # RP5 device pci 1c.5 on end # RP6 device pci 1c.6 off end # RP7 - device pci 1c.7 off end # RP8 + device pci 1c.7 on end # RP8 device pci 1d.0 on end # RP9 device pci 1d.1 off end # RP10 device pci 1d.2 on end # RP11 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 89e6f58..4cb8c3a 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -72,6 +72,10 @@ PAD_CFG_GPO(GPP_B4, 1, PLTRST), /* M.2_PCH_SSD_PWREN */ PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + /* SRCCLK_OEB6 */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* M.2_SSD_PDET_R */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/48080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17 Gerrit-Change-Number: 48080 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU
by Subrata Banik (Code Review) 01 Dec '20

01 Dec '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48079 ) Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU ...................................................................... mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU List of changes in SPD: 1. tCKAVGmax 2. CAS Latencies supported (First Byte) 3. CAS Latencies supported (Second Byte) 4. CAS Latencies supported (Third Byte) 5. Minimum CAS Latency (tAAmin) 6. Read and Write Latency Set options 7. FTB for tAAmin 8. FTB for tCKAVGmax 9. FTB for tCKAVGmin TEST=Able to build and boot with updated SPD. Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48079/1 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex index 17f270d..e1d338e 100644 --- a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex @@ -1,11 +1,11 @@ -23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 -48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/48079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Gerrit-Change-Number: 48079 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: Makefile.inc: Alloc .bss.* sections for "struct" file type
by Yu-Ping Wu (Code Review) 01 Dec '20

01 Dec '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47903 ) Change subject: Makefile.inc: Alloc .bss.* sections for "struct" file type ...................................................................... Makefile.inc: Alloc .bss.* sections for "struct" file type When the global variable of a "struct" CBFS file is zero (for example, CB:47696), the binary will appear in the .bss.* section in the ELF file (instead of .data). This results in an empty binary file added to CBFS, so that file size check will fail when reading it at runtime. BUG=b:173751635 TEST=emerge-asurada coreboot TEST=Check sdram-lpddr4x-KMDP6001DA-B425-4GB is non-empty in CBFS BRANCH=none Change-Id: Idfd17d10101a948de0eb0522a672afd5c2f83b04 Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47903/1 diff --git a/Makefile.inc b/Makefile.inc index 9273961..f3493d8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -338,7 +338,7 @@ $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \ printf " CC+STRIP $(@)\n"; \ $(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \ - $(OBJCOPY_ramstage) -O binary $(2).tmp $(2); \ + $(OBJCOPY_ramstage) -O binary -set-section-flags .bss.*=alloc,contents,load $(2).tmp $(2); \ rm -f $(2).tmp) \ $(eval DEPENDENCIES += $(2).d) -- To view, visit https://review.coreboot.org/c/coreboot/+/47903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd17d10101a948de0eb0522a672afd5c2f83b04 Gerrit-Change-Number: 47903 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: mb/google/dedede: Add ACPI support for camera in waddledee
by Varshit B Pandya (Code Review) 01 Dec '20

01 Dec '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42205 ) Change subject: mb/google/dedede: Add ACPI support for camera in waddledee ...................................................................... mb/google/dedede: Add ACPI support for camera in waddledee 1. Add support as per the schematics 2. Add 2 Ports and 2 Endpoints 3. Add support for OTVI9734 and OTVI5676 4. Add ON and OFF logic as Power Rails are same for both sensor BUG=None BRANCH=None TEST=Build and Boot waddledee board and able to capture image using world facing camera and user facing camera. Change-Id: I3f6b490832d2c34c86512384eb7470f13a212a66 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl 6 files changed, 559 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/42205/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 25ad61f..b6e1d64 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -18,6 +18,7 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_WHEELIE bool "Wheelie" diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl new file mode 100644 index 0000000..90c7d58 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA0, Zero) + + /* Method to turn off Power Rails */ + Method (POFF, 0) + { + /* Disable PP1200 lane */ + CTXS(GPP_D14) + /* Disable PP2800 lane */ + CTXS(GPP_D13) + } + + Method (PON, 0) + { + /* Enable PP2800 lane */ + STXS(GPP_D13) + /* Enable PP1200 lane */ + STXS(GPP_D14) + } + + PowerResource (FCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + MCON(1, 1) /* Clock 1, 19.2MHz */ + IF(!STA1) + { + /* Other sensor is OFF, so turn on power signals. */ + PON() + } + /* Assert Reset */ + CTXS(GPP_D12) + Sleep(5) /* 5 us */ + /* Deassert Reset */ + STXS(GPP_D12) + Sleep(5) /* 5 us */ + STA0 = 1 + } + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + MCOF(1) /* Clock 1 */ + /* Assert Reset */ + CTXS(GPP_D12) + IF(!STA1) + { + /* Other sensor is OFF, so turn off power signals. */ + POFF() + } + STA0 = 0 + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA0) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hadware ID */ + + Name (_UID, 0x03) /* _UID: Unique ID */ + + Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Setting */ + { + I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3Hot */ + { + FCPR + }) + + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package(0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl new file mode 100644 index 0000000..3e76197 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA1, Zero) + + PowerResource (RCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + MCON(0, 1) /* Clock 0, 19.2MHz */ + /* Check if another sensor is ON */ + IF(!STA0) + { + /* Other sensor is OFF, so turn on power signals. */ + PON() + } + /* Assert Reset */ + CTXS(GPP_D15) + Sleep(5) /* 5 us */ + /* DeAssert Reset */ + STXS(GPP_D15) + Sleep(5) /* 5 us */ + STA1 = 1 + } + + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + MCOF(0) /* Clock 0 */ + /* Assert Reset */ + CTXS(GPP_D15) + IF(!STA0) + { + /* Other sensor is OFF, so turn off power signals. */ + POFF() + } + STA1 = 0 + } + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA1) + } + } + + Device(CAM1) + { + Name (_HID, "OVTI9734") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 9734 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x0ABA9500 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl new file mode 100644 index 0000000..51b4ebc --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "cam0.asl" +#include "cam1.asl" diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl new file mode 100644 index 0000000..89ccb48 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x01) + { + One, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM1, + Zero, + Zero + } + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl new file mode 100644 index 0000000..8d37674 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) /* _ADR: Address */ + + Name (_DDN, "Camera and Imaging Subsystem") /* _DDN: DOS Device Name */ + } +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f6b490832d2c34c86512384eb7470f13a212a66 Gerrit-Change-Number: 42205 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

8 25

Change in coreboot[master]: util/mb/google/puff: remove HECI from overridetree
by Paul Fagerburg (Code Review) 01 Dec '20

01 Dec '20

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48129 ) Change subject: util/mb/google/puff: remove HECI from overridetree ...................................................................... util/mb/google/puff: remove HECI from overridetree The template for overridetree.cb includes HeciEnabled, which has been removed from the CNL config struct, so remove it from the overridetree. BUG=b:174360951 TEST=`new_variant_fulltest.sh puff` succeeds Change-Id: I87f67c53cc75d9ddd40b4960739180a95de6ecd6 --- M util/mainboard/google/puff/template/overridetree.cb 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/48129/1 diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index adb00e4..a30dad0 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -1,7 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" - # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/48129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87f67c53cc75d9ddd40b4960739180a95de6ecd6 Gerrit-Change-Number: 48129 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/siemens/chili: Configure GPIOs in gpio.c
by Felix Singer (Code Review) 01 Dec '20

01 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47974 ) Change subject: mb/siemens/chili: Configure GPIOs in gpio.c ...................................................................... mb/siemens/chili: Configure GPIOs in gpio.c Get rid of variant_gpio_table() and configure GPIOs in gpio.c instead of passing data around. Change-Id: Ib158d6bdbcbceb3c1dc4f47fc7c3e098b9c7e5c4 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A src/mainboard/siemens/chili/include/mainboard/gpio.h M src/mainboard/siemens/chili/include/variant.h M src/mainboard/siemens/chili/romstage.c M src/mainboard/siemens/chili/variants/base/gpio.c M src/mainboard/siemens/chili/variants/chili/gpio.c 5 files changed, 15 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/47974/1 diff --git a/src/mainboard/siemens/chili/include/mainboard/gpio.h b/src/mainboard/siemens/chili/include/mainboard/gpio.h new file mode 100644 index 0000000..ef2a21c --- /dev/null +++ b/src/mainboard/siemens/chili/include/mainboard/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/siemens/chili/include/variant.h b/src/mainboard/siemens/chili/include/variant.h index 2bbe7d7..1d97728 100644 --- a/src/mainboard/siemens/chili/include/variant.h +++ b/src/mainboard/siemens/chili/include/variant.h @@ -7,6 +7,4 @@ void variant_romstage_params(FSPM_UPD *); -const struct pad_config *variant_gpio_table(size_t *num); - #endif /* _VARIANT_H_ */ diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c index a981f50..887ca3b 100644 --- a/src/mainboard/siemens/chili/romstage.c +++ b/src/mainboard/siemens/chili/romstage.c @@ -6,15 +6,6 @@ #include <soc/romstage.h> #include <variant.h> -static void mainboard_init(void) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); -} - void mainboard_memory_init_params(FSPM_UPD *memupd) { uint8_t vtd = 1; @@ -39,7 +30,7 @@ variant_romstage_params(memupd); - mainboard_init(); + mainboard_configure_gpios(); } __weak void variant_romstage_params(FSPM_UPD *const mupd) diff --git a/src/mainboard/siemens/chili/variants/base/gpio.c b/src/mainboard/siemens/chili/variants/base/gpio.c index 61ec27d..9d459cc 100644 --- a/src/mainboard/siemens/chili/variants/base/gpio.c +++ b/src/mainboard/siemens/chili/variants/base/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <variant.h> +#include <mainboard/gpio.h> static const struct pad_config gpio_table[] = { /* GPP_A14 GPIO */ PAD_NC(GPP_A14, NONE), @@ -122,8 +122,7 @@ /* GPP_J11 A4WP_PRESENT */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), }; -const struct pad_config *variant_gpio_table(size_t *num) +void mainboard_configure_gpios(void) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } diff --git a/src/mainboard/siemens/chili/variants/chili/gpio.c b/src/mainboard/siemens/chili/variants/chili/gpio.c index d7e5ab02..a259547 100644 --- a/src/mainboard/siemens/chili/variants/chili/gpio.c +++ b/src/mainboard/siemens/chili/variants/chili/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include <variant.h> +#include <mainboard/gpio.h> static const struct pad_config gpio_table[] = { /* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE), @@ -121,8 +121,7 @@ /* GPP_J11 A4WP_PRESENT 0x0000003944000700 */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), }; -const struct pad_config *variant_gpio_table(size_t *num) +void mainboard_configure_gpios(void) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib158d6bdbcbceb3c1dc4f47fc7c3e098b9c7e5c4 Gerrit-Change-Number: 47974 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/siemens/chili: Introduce include folder for header files
by Felix Singer (Code Review) 01 Dec '20

01 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47973 ) Change subject: mb/siemens/chili: Introduce include folder for header files ...................................................................... mb/siemens/chili: Introduce include folder for header files Use include folder for header files allowing proper includes. Change-Id: I80066fb925b918d040062397e633c5d499a50dbe Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/siemens/chili/Makefile.inc M src/mainboard/siemens/chili/ec.c R src/mainboard/siemens/chili/include/mainboard/ec.h R src/mainboard/siemens/chili/include/variant.h M src/mainboard/siemens/chili/mainboard.c M src/mainboard/siemens/chili/romstage.c M src/mainboard/siemens/chili/variants/base/gpio.c M src/mainboard/siemens/chili/variants/chili/gpio.c M src/mainboard/siemens/chili/variants/chili/romstage.c 9 files changed, 7 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/47973/1 diff --git a/src/mainboard/siemens/chili/Makefile.inc b/src/mainboard/siemens/chili/Makefile.inc index abeedf3..c57c0a5 100644 --- a/src/mainboard/siemens/chili/Makefile.inc +++ b/src/mainboard/siemens/chili/Makefile.inc @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include romstage-y += romstage.c diff --git a/src/mainboard/siemens/chili/ec.c b/src/mainboard/siemens/chili/ec.c index bc0eb7d..7d9b6f2 100644 --- a/src/mainboard/siemens/chili/ec.c +++ b/src/mainboard/siemens/chili/ec.c @@ -4,10 +4,9 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <ec/acpi/ec.h> +#include <mainboard/ec.h> #include <timer.h> -#include "ec.h" - #define EC_STATUS 0x50 #define EC_RUNNING (1 << 1) #define EC_DEVICE_CONTROL_1 0x80 diff --git a/src/mainboard/siemens/chili/ec.h b/src/mainboard/siemens/chili/include/mainboard/ec.h similarity index 100% rename from src/mainboard/siemens/chili/ec.h rename to src/mainboard/siemens/chili/include/mainboard/ec.h diff --git a/src/mainboard/siemens/chili/variant.h b/src/mainboard/siemens/chili/include/variant.h similarity index 100% rename from src/mainboard/siemens/chili/variant.h rename to src/mainboard/siemens/chili/include/variant.h diff --git a/src/mainboard/siemens/chili/mainboard.c b/src/mainboard/siemens/chili/mainboard.c index 91395ea..c1d1a1d 100644 --- a/src/mainboard/siemens/chili/mainboard.c +++ b/src/mainboard/siemens/chili/mainboard.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> - -#include "ec.h" +#include <mainboard/ec.h> static void mainboard_dev_init(struct device *dev) { diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c index c1ec7e4..a981f50 100644 --- a/src/mainboard/siemens/chili/romstage.c +++ b/src/mainboard/siemens/chili/romstage.c @@ -4,8 +4,7 @@ #include <soc/cnl_memcfg_init.h> #include <soc/gpio.h> #include <soc/romstage.h> - -#include "variant.h" +#include <variant.h> static void mainboard_init(void) { diff --git a/src/mainboard/siemens/chili/variants/base/gpio.c b/src/mainboard/siemens/chili/variants/base/gpio.c index 65ea037..61ec27d 100644 --- a/src/mainboard/siemens/chili/variants/base/gpio.c +++ b/src/mainboard/siemens/chili/variants/base/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include "variant.h" +#include <variant.h> static const struct pad_config gpio_table[] = { /* GPP_A14 GPIO */ PAD_NC(GPP_A14, NONE), diff --git a/src/mainboard/siemens/chili/variants/chili/gpio.c b/src/mainboard/siemens/chili/variants/chili/gpio.c index 4b18e79..d7e5ab02 100644 --- a/src/mainboard/siemens/chili/variants/chili/gpio.c +++ b/src/mainboard/siemens/chili/variants/chili/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/gpio.h> -#include "variant.h" +#include <variant.h> static const struct pad_config gpio_table[] = { /* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE), diff --git a/src/mainboard/siemens/chili/variants/chili/romstage.c b/src/mainboard/siemens/chili/variants/chili/romstage.c index ebffc8d3..3a83824 100644 --- a/src/mainboard/siemens/chili/variants/chili/romstage.c +++ b/src/mainboard/siemens/chili/variants/chili/romstage.c @@ -3,8 +3,7 @@ #include <option.h> #include <console/console.h> #include <fsp/soc_binding.h> - -#include "../../variant.h" +#include <variant.h> void variant_romstage_params(FSPM_UPD *const mupd) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80066fb925b918d040062397e633c5d499a50dbe Gerrit-Change-Number: 47973 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/kontron/bsl6: Configure GPIOs using mainboard_ops
by Michael Niewöhner (Code Review) 01 Dec '20

01 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47850 ) Change subject: mb/kontron/bsl6: Configure GPIOs using mainboard_ops ...................................................................... mb/kontron/bsl6: Configure GPIOs using mainboard_ops Hook up the mainboard_ops driver and configure the GPIOs using .init, since mainboard_silicon_init_params() is meant for the configuration of the FSP, not the GPIOs. Change-Id: I6ab8d258c6f81c90d835cb8d07c6387d3de76d85 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47850 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/kontron/bsl6/ramstage.c 1 file changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/kontron/bsl6/ramstage.c b/src/mainboard/kontron/bsl6/ramstage.c index 19518f7..771c6aa 100644 --- a/src/mainboard/kontron/bsl6/ramstage.c +++ b/src/mainboard/kontron/bsl6/ramstage.c @@ -1,9 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/ramstage.h> +#include <device/device.h> #include <mainboard/gpio.h> -void mainboard_silicon_init_params(FSP_SIL_UPD *params) +static void init_mainboard(void *chip_info) { mainboard_configure_gpios(); } + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/47850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ab8d258c6f81c90d835cb8d07c6387d3de76d85 Gerrit-Change-Number: 47850 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020