coreboot-gerrit November 2020

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Change in coreboot[master]: [WIP] soc/amd/picasso: add FSP binary location
by Felix Held (Code Review) 02 Dec '20

02 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42472 ) Change subject: [WIP] soc/amd/picasso: add FSP binary location ...................................................................... [WIP] soc/amd/picasso: add FSP binary location Since the blobs haven't landed yet, it is expected that this breaks the Jenkins build. Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/Kconfig 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/42472/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index dd5731d..bf809f8 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -60,6 +60,20 @@ string default "src/soc/amd/picasso/memlayout.ld" +config FSP_M_FILE + string "FSP-M (memory init) binary path and filename" + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/picasso/PICASSO_M.fd" + help + The path and filename of the FSP-M binary for this platform. + +config FSP_S_FILE + string "FSP-S (silicon init) binary path and filename" + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/picasso/PICASSO_S.fd" + help + The path and filename of the FSP-S binary for this platform. + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/42472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e Gerrit-Change-Number: 42472 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: WIP: soc/mediatek/mt8192: add i2c driver support
by yongqiang niu (Code Review) 02 Dec '20

02 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46573 ) Change subject: WIP: soc/mediatek/mt8192: add i2c driver support ...................................................................... WIP: soc/mediatek/mt8192: add i2c driver support Add i2c controller driver code TEST=Boots correctly on MT8192P1 Signed-off-by: jg_daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Change-Id: Ib8ece265687d37bafe2f0de63459ea0fabab8a11 --- M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/i2c.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/i2c.h 6 files changed, 247 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46573/1 diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index 87925ba..931e36d 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -47,6 +47,7 @@ { uint32_t ret_code = I2C_OK; uint16_t status; + uint16_t dma_sync = 0; uint32_t time_out_val = 0; uint8_t addr; uint32_t write_len = 0; @@ -62,6 +63,12 @@ addr = seg[0].slave; + if (mtk_i2c_bus_controller[bus].mt_i2c_flag == I2C_APDMA_ASYNC) { + dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; + if (mode == I2C_WRITE_READ_MODE) + dma_sync |= I2C_DMA_DIR_CHANGE; + } + switch (mode) { case I2C_WRITE_MODE: assert(seg[0].len > 0 && seg[0].len <= 255); @@ -113,7 +120,7 @@ write32(&regs->slave_addr, addr << 1); /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_TX); + write32(&dma_regs->dma_con, I2C_DMA_CON_TX | dma_sync); write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); write32(&dma_regs->dma_tx_len, write_len); break; @@ -132,7 +139,7 @@ write32(&regs->slave_addr, (addr << 1 | 0x1)); /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_RX); + write32(&dma_regs->dma_con, I2C_DMA_CON_RX | dma_sync); write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); write32(&dma_regs->dma_rx_len, read_len); break; @@ -154,7 +161,7 @@ write32(&regs->slave_addr, addr << 1); /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG | dma_sync); write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); write32(&dma_regs->dma_tx_len, write_len); write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index 0100e26..198a2b57 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -38,6 +38,9 @@ I2C_DMA_INT_FLAG_NONE = 0x0, I2C_DMA_CLR_FLAG = 0x0, I2C_DMA_FLUSH_FLAG = 0x1, + I2C_DMA_ASYNC_MODE = 0x0004, + I2C_DMA_SKIP_CONFIG = 0x0010, + I2C_DMA_DIR_CHANGE = 0x0200, }; enum { @@ -46,6 +49,11 @@ I2C_CONTROL_MASK = (0x3f << 1) }; +enum { + I2C_APDMA_NOASYNC = 0, + I2C_APDMA_ASYNC = 1, +}; + /* Register mask */ enum { I2C_HS_NACKERR = (1 << 2), @@ -80,6 +88,7 @@ struct mtk_i2c { struct mt_i2c_regs *i2c_regs; struct mt_i2c_dma_regs *i2c_dma_regs; + uint32_t mt_i2c_flag; }; extern struct mtk_i2c mtk_i2c_bus_controller[]; diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index d695824..04d57dc 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -5,6 +5,7 @@ bootblock-y += bootblock.c bootblock-y += flash_controller.c bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -19,6 +20,7 @@ verstage-y += auxadc.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c @@ -30,6 +32,7 @@ romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/mmu_operations.c romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -41,6 +44,7 @@ ramstage-y += auxadc.c ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += dpm.c diff --git a/src/soc/mediatek/mt8192/i2c.c b/src/soc/mediatek/mt8192/i2c.c new file mode 100644 index 0000000..6b9c1ea --- /dev/null +++ b/src/soc/mediatek/mt8192/i2c.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <soc/pll.h> +#include <soc/i2c.h> +#include <soc/gpio.h> + +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) +struct mtk_i2c mtk_i2c_bus_controller[] = { + /* i2c0 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x250000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c1 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x70000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x80), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c2 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x71000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x100), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c3 setting */ + { + .i2c_regs = (void *)(I2C_BASE), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x280), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c4 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x72000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x300), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c5 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x150000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c6 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x251000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x500), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c7 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x50000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c8 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x51000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x700), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c9 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x52000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x880), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, +}; + +#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + { + PAD_FUNC(SDA6, SDA6), + PAD_FUNC(SCL6, SCL6), + }, + { + PAD_FUNC(SDA7, SDA7), + PAD_FUNC(SCL7, SCL7), + }, + { + PAD_FUNC(SDA8, SDA8), + PAD_FUNC(SCL8, SCL8), + }, + { + PAD_FUNC(SDA9, SDA9), + PAD_FUNC(SCL9, SCL9), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +static void mtk_i2c_speed_init(uint8_t bus) +{ + uint8_t step_div; + const uint8_t clock_div = 5; + const uint8_t sample_div = 1; + uint32_t i2c_freq; + + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (400 * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && i2c_freq <= 400 * KHz && + i2c_freq >= 380 * KHz); + + /* Init i2c bus Timing register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming, + (sample_div - 1) << 6 | (step_div - 1)); + + /* Init i2c bus clock_div register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div, + clock_div - 1); +} + +void mtk_i2c_bus_init(uint8_t bus) +{ + mtk_i2c_speed_init(bus); + mtk_i2c_set_gpio_pinmux(bus); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 85eac5b..3fd2bca 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -29,6 +29,7 @@ PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + I2C_DMA_BASE = IO_PHYS + 0x00217080, EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, @@ -50,6 +51,7 @@ UFSHCI_BASE = IO_PHYS + 0x01270000, EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, + I2C_BASE = IO_PHYS + 0x01CB0000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, IOCFG_BL_BASE = IO_PHYS + 0x01D30000, IOCFG_BR_BASE = IO_PHYS + 0x01D40000, diff --git a/src/soc/mediatek/mt8192/include/soc/i2c.h b/src/soc/mediatek/mt8192/include/soc/i2c.h new file mode 100644 index 0000000..72a9af1 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/i2c.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_I2C_H +#define SOC_MEDIATEK_MT8192_I2C_H + +#include <soc/i2c_common.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus); + +#endif /* SOC_MEDIATEK_MT8192_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ece265687d37bafe2f0de63459ea0fabab8a11 Gerrit-Change-Number: 46573 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341
by Lean Sheng Tan (Code Review) 02 Dec '20

02 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47803 ) Change subject: vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341 ...................................................................... vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341 The FSP-M/S/T related headers added are generated as per FSP v2341. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I98f738402490b47efa1a346f81db47857e384e13 --- A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FirmwareVersionInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FsptUpd.h A src/vendorcode/intel/fsp/fsp2_0/elkhartlake/MemInfoHob.h 6 files changed, 8,433 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47803/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/47803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f738402490b47efa1a346f81db47857e384e13 Gerrit-Change-Number: 47803 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/elkhartlake: Update Kconfig
by Lean Sheng Tan (Code Review) 02 Dec '20

02 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45078 ) Change subject: soc/intel/elkhartlake: Update Kconfig ...................................................................... soc/intel/elkhartlake: Update Kconfig Update Kconfig: 1. use FSP2.1 instead of 2.2 2. remove HECI_DISABLE_USING_SMM config 3. update CAR related stack & ram size 4. update FSP heap size 5. set IED region size = 0 as it is not used 6. update SMM TSEG size 7. update RP & I2c max device #s 8. update UART base address Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9 --- M src/soc/intel/elkhartlake/Kconfig 1 file changed, 11 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45078/1 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 166bda0..b5462ff 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -32,7 +32,7 @@ select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_2 + select PLATFORM_USES_FSP2_1 select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK @@ -61,29 +61,27 @@ select UDELAY_TSC select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM config DCACHE_RAM_BASE default 0xfef00000 config DCACHE_RAM_SIZE - default 0x80000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x30400 + default 0x30000 help The amount of anticipated stack usage in CAR by bootblock and - other stages. In the case of FSP_USES_CB_STACK default value - will be sum of FSP-M stack requirement(192 KiB) and CB romstage - stack requirement(~1KiB). + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE hex - default 0x20000 + default 0x40000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know @@ -95,7 +93,7 @@ config IED_REGION_SIZE hex - default 0x400000 + default 0x0 config HEAP_SIZE hex @@ -103,7 +101,7 @@ config MAX_ROOT_PORTS int - default 8 + default 7 config MAX_PCIE_CLOCKS int @@ -111,7 +109,7 @@ config SMM_TSEG_SIZE hex - default 0x800000 + default 0x1000000 config SMM_RESERVED_SIZE hex @@ -145,7 +143,7 @@ config SOC_INTEL_I2C_DEV_MAX int - default 6 + default 8 config SOC_INTEL_UART_DEV_MAX int @@ -153,7 +151,7 @@ config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe032000 + default 0xfe042000 depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate -- To view, visit https://review.coreboot.org/c/coreboot/+/45078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9 Gerrit-Change-Number: 45078 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: soc/intel/skylake: Map VBIOS IDs
by Paul Menzel (Code Review) 02 Dec '20

02 Dec '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43853 ) Change subject: soc/intel/skylake: Map VBIOS IDs ...................................................................... soc/intel/skylake: Map VBIOS IDs The extracted VBIOS Option ROM ships the same ID for several generations, not matching the ID on the hardware resulting in a mismatch, and coreboot does not run the Option ROM. PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Add the appropriate mappings. TEST=coreboot runs the ROM on the TUXEDO Book BU1406. Change-Id: Ia167d91627a7ff1b329ea75f150b3ce95c0acccb Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/skylake/graphics.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/43853/1 diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 4ecf67a..f95ca6c 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -3,11 +3,13 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <device/mmio.h> +#include <device/pci_rom.h> #include <device/resource.h> #include <drivers/intel/gma/i915.h> #include <drivers/intel/gma/i915_reg.h> #include <intelblocks/graphics.h> #include <soc/ramstage.h> +#include <soc/systemagent.h> #include <types.h> void graphics_soc_init(struct device *dev) @@ -76,3 +78,21 @@ struct soc_intel_skylake_config *chip = device->chip_info; return &chip->gfx; } + +/* + * Some VGA option roms are used for several chipsets but they only have one PCI ID in their + * header. If we encounter such an option rom, we need to do the mapping ourselves. + */ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x80865916: /* PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM */ + case 0x80865917: /* PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR */ + new_vendev = SA_IGD_OPROM_VENDEV; + break; + } + + return new_vendev; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia167d91627a7ff1b329ea75f150b3ce95c0acccb Gerrit-Change-Number: 43853 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04
by Ronak Kanabar (Code Review) 02 Dec '20

02 Dec '20

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47862 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04 ...................................................................... vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04 The headers added are generated as per FSP v2385_04. Previous FSP version was 2385_02. Changes Include: - add FastPkgCRampDisable, SlowSlewRate, PreWake, RampUp and RampDown UPDs in Fsps.h TEST=Build and boot JSLRVP Change-Id: I477af05c34f767a43990670a711992641eaf6000 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h 1 file changed, 39 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/47862/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h index 34c29dc..dd7db9d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h @@ -981,9 +981,23 @@ **/ UINT8 AcousticNoiseMitigation; -/** Offset 0x048D - Reserved +/** Offset 0x048D - Disable Fast Slew Rate for Deep Package C States for VR domains + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. 0: False; 1: True + $EN_DIS **/ - UINT8 Reserved21[21]; + UINT8 FastPkgCRampDisable[5]; + +/** Offset 0x0492 - Slew Rate configuration for Deep Package C States for VR domains + Slew Rate configuration for Deep Package C States for VR domains based on Acoustic + Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 +**/ + UINT8 SlowSlewRate[5]; + +/** Offset 0x0497 - Reserved +**/ + UINT8 Reserved21[11]; /** Offset 0x04A2 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is @@ -1079,9 +1093,30 @@ **/ UINT32 CpuMpHob; -/** Offset 0x04F4 - Reserved +/** Offset 0x04F4 - Pre Wake Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled. Range 0-255 0. **/ - UINT8 Reserved24[16]; + UINT8 PreWake; + +/** Offset 0x04F5 - Ramp Up Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled.Range 0-255 0. +**/ + UINT8 RampUp; + +/** Offset 0x04F6 - Ramp Down Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled.Range 0-255 0. +**/ + UINT8 RampDown; + +/** Offset 0x04F7 - Reserved +**/ + UINT8 Reserved24[13]; /** Offset 0x0504 - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this -- To view, visit https://review.coreboot.org/c/coreboot/+/47862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I477af05c34f767a43990670a711992641eaf6000 Gerrit-Change-Number: 47862 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Update SPD table for Shuboz
by Kane Chen (Code Review) 02 Dec '20

02 Dec '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47902 ) Change subject: mb/google/zork: Update SPD table for Shuboz ...................................................................... mb/google/zork: Update SPD table for Shuboz Add SPD support in Shuboz memory table as follow: 1. MICRON MT40A512M16TB-062E:J 2. HYNIX H5AN8G6NCJR-XNC 3. MICRON MT40A1G16KD-062E:E 4. SAMSUNG K4AAG165WA-BCWE BUG=b:none BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I5f5f875daab58343f1cc8a9327ea128ba5e1f050 --- M src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc M src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt 3 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47902/1 diff --git a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc index 3edeb96..87b5aa97 100644 --- a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = ddr4-spd-empty.hex +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = H5AN8G6NCJR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 2(0b0010) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt index fa24790..8019b2e 100644 --- a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt @@ -1 +1,5 @@ DRAM Part Name ID to assign +MT40A512M16TB-062E:J 0 (0000) +H5AN8G6NCJR-XNC 1 (0001) +MT40A1G16KD-062E:E 2 (0010) +K4AAG165WA-BCWE 3 (0011) diff --git a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt index 106a705..f2240fd 100644 --- a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt @@ -7,3 +7,7 @@ # See util/spd_tools/ddr4/README.md for more details and instructions. # Part Name, Fixed ID (optional) +MT40A512M16TB-062E:E, 0 +H5AN8G6NCJR-XNC, 1 +MT40A1G16KD-062E:E, 2 +K4AAG165WA-BCWE, 3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5f875daab58343f1cc8a9327ea128ba5e1f050 Gerrit-Change-Number: 47902 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/car.ld: Check for out of bound on no-XIP stages
by Arthur Heymans (Code Review) 02 Dec '20

02 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36623 ) Change subject: arch/x86/car.ld: Check for out of bound on no-XIP stages ...................................................................... arch/x86/car.ld: Check for out of bound on no-XIP stages Check that stages running in CAR have their start and end in CAR. Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36623/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 6ccbd8c..e68beb3 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -119,4 +119,9 @@ #endif #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); +#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_VERSTAGE) +_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !"); +_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!"); +#endif + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609 Gerrit-Change-Number: 36623 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: mediatek/mt8192/spm.c: Use mtlib_load_and_run API
by Yidi Lin (Code Review) 02 Dec '20

02 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47897 ) Change subject: WIP: mediatek/mt8192/spm.c: Use mtlib_load_and_run API ...................................................................... WIP: mediatek/mt8192/spm.c: Use mtlib_load_and_run API Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: Ie40e5b62bbaa738cd38312563e81a23443044a64 --- M src/soc/mediatek/mt8192/spm.c 1 file changed, 32 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47897/1 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index b2d2d47..5e879ab 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -5,11 +5,13 @@ #include <console/console.h> #include <delay.h> #include <device/mmio.h> +#include <soc/mtlib_common.h> #include <soc/spm.h> #include <soc/symbols.h> #include <timer.h> #define SPMFW_HEADER_SIZE 16 +#define SPM_FW_FILE "spm_firmware.bin" static struct pwr_ctrl spm_init_ctrl = { /* Auto-gen Start */ @@ -491,22 +493,14 @@ write32(&mtk_spm->pcm_pwr_io_en, 0); } -static int spm_load_firmware(struct dyna_load_pcm *pcm) +static void spm_parse_firmware(struct mtlib_fw_prop *fw) { - struct stopwatch sw; - const char *file_name = "spm_firmware.bin"; size_t file_size, copy_size; int offset; u16 firmware_size; - stopwatch_init(&sw); - - file_size = cbfs_boot_load_file(file_name, _dram_dma, - REGION_SIZE(dram_dma), CBFS_TYPE_RAW); - if (file_size == 0) { - printk(BIOS_ERR, "SPM binary %s not found\n", file_name); - return -1; - } + struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)fw->priv; + file_size = fw->size; /* * spmfw layout: @@ -519,28 +513,25 @@ /* firmware size */ offset = 0; copy_size = sizeof(firmware_size); - memcpy(&firmware_size, _dram_dma + offset, copy_size); + memcpy(&firmware_size, fw->buf + offset, copy_size); printk(BIOS_DEBUG, "SPM: binary array size = %#x\n", firmware_size); /* binary */ offset = SPMFW_HEADER_SIZE; /* binary start offset */ copy_size = firmware_size * sizeof(u32); assert(offset < file_size); - pcm->buf = (u8 *)(_dram_dma + offset); + pcm->buf = (u8 *)(fw->buf + offset); /* descriptor */ offset += copy_size; assert(offset < file_size); copy_size = sizeof(pcm->desc); - memcpy(&pcm->desc, _dram_dma + offset, copy_size); + memcpy(&pcm->desc, fw->buf + offset, copy_size); /* version */ offset += copy_size; assert(offset < file_size); - printk(BIOS_INFO, "spmfw (version %s) loaded in %ld msecs\n", - _dram_dma + offset, stopwatch_duration_msecs(&sw)); - - return 0; + printk(BIOS_INFO, "SPM: spmfw (version %s)\n", (u8 *)fw->buf + offset); } static void spm_set_wakeup_event(struct pwr_ctrl *pwrctrl) @@ -637,6 +628,23 @@ udelay(SPM_INIT_DONE_US); } +static void reset_spm(struct mtlib_fw_prop *fw) +{ + struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)fw->priv; + + spm_parse_firmware(fw); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(pcm); + spm_init_pcm_register(); + spm_set_wakeup_event(&spm_init_ctrl); + spm_kick_pcm_to_run(&spm_init_ctrl); +} + +static struct mtlib_fw_prop spm = { + .name = SPM_FW_FILE, + .reset = reset_spm, +}; + int spm_init(void) { struct dyna_load_pcm pcm; @@ -648,17 +656,15 @@ spm_set_power_control(&spm_init_ctrl); spm_set_sysclk_settle(); - if (spm_load_firmware(&pcm)) { - printk(BIOS_ERR, "SPM: firmware is not ready\n"); + spm.buf = _dram_dma; + spm.buf_size = REGION_SIZE(dram_dma); + spm.priv = (void *)&pcm; + + if (mtlib_load_and_run(&spm)) { + printk(BIOS_ERR, "%s() failed\n", __func__); return -1; } - spm_reset_and_init_pcm(); - spm_kick_im_to_fetch(&pcm); - spm_init_pcm_register(); - spm_set_wakeup_event(&spm_init_ctrl); - spm_kick_pcm_to_run(&spm_init_ctrl); - printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n", __func__, stopwatch_duration_msecs(&sw), read32(&mtk_spm->md32pcm_pc)); -- To view, visit https://review.coreboot.org/c/coreboot/+/47897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie40e5b62bbaa738cd38312563e81a23443044a64 Gerrit-Change-Number: 47897 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mt8192/dpm.c: use load_blob_file to load the blob files
by Yidi Lin (Code Review) 02 Dec '20

02 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46932 ) Change subject: mt8192/dpm.c: use load_blob_file to load the blob files ...................................................................... mt8192/dpm.c: use load_blob_file to load the blob files Use load_blob_file to load the blob files. TEST=1. emerge-asurada coreboot chromeos-bootimage; 2. See following log during booting. load_blob_file: Load dpm.dm in 15 msecs, size 36 bytes load_blob_file: Load dpm.pm in 18 msecs, size 13848 bytes 3. Test suspend/resume by: a. suspend (on DUT): echo mem > /sys/power/stat b. resume (on host): dut-control power_state:on Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: If5e51d1390a3daf5fac68e1180506ec0431160d2 --- M src/soc/mediatek/mt8192/dpm.c 1 file changed, 10 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46932/1 diff --git a/src/soc/mediatek/mt8192/dpm.c b/src/soc/mediatek/mt8192/dpm.c index ef46c30..912f153 100644 --- a/src/soc/mediatek/mt8192/dpm.c +++ b/src/soc/mediatek/mt8192/dpm.c @@ -1,50 +1,30 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <assert.h> -#include <cbfs.h> #include <console/console.h> -#include <delay.h> #include <device/mmio.h> #include <soc/dpm.h> +#include <soc/mtlib_common.h> #include <timer.h> -#define DM_BUF_SIZE (2 * KiB) -#define PM_BUF_SIZE (20 * KiB) - -static u8 dpm_dm_bin[DM_BUF_SIZE] __aligned(8); -static u8 dpm_pm_bin[PM_BUF_SIZE] __aligned(8); -static void *dpm_pm_reg = (void *)DPM_PM_SRAM_BASE; -static void *dpm_dm_reg = (void *)DPM_DM_SRAM_BASE; /* Return Value: 0 successful, < 0 means failed */ static int dpm_load_firmware(void) { const char *dm_file_name = "dpm.dm"; const char *pm_file_name = "dpm.pm"; - size_t dm_file_bytes, pm_file_bytes; - - dm_file_bytes = cbfs_boot_load_file(dm_file_name, dpm_dm_bin, - sizeof(dpm_dm_bin), CBFS_TYPE_RAW); - if (dm_file_bytes == 0) { - printk(BIOS_ERR, "binary %s not found\n", dm_file_name); - return -1; - } - - pm_file_bytes = cbfs_boot_load_file(pm_file_name, dpm_pm_bin, - sizeof(dpm_pm_bin), CBFS_TYPE_RAW); - if (pm_file_bytes == 0) { - printk(BIOS_ERR, "binary %s not found\n", pm_file_name); - return -2; - } - printk(BIOS_INFO, "dm_file_bytes: %d, pm_file_bytes: %d\n", - (int)dm_file_bytes, (int)pm_file_bytes); /* config DPM SRAM layout */ write32(&mtk_dpm->sw_rstn, read32(&mtk_dpm->sw_rstn) | 0x10000000); - /* copy PM DM to DPM_SRAM */ - memcpy(dpm_pm_reg, dpm_pm_bin, pm_file_bytes); - memcpy(dpm_dm_reg, dpm_dm_bin, dm_file_bytes); + if (load_blob_file(dm_file_name, DPM_DM_SRAM_BASE)) { + printk(BIOS_ERR, "binary %s not found\n", dm_file_name); + return -1; + } + + if (load_blob_file(pm_file_name, DPM_PM_SRAM_BASE)) { + printk(BIOS_ERR, "binary %s not found\n", pm_file_name); + return -2; + } /* write bootargs */ write32(&mtk_dpm->twam_window_len, 0x0); @@ -58,16 +38,10 @@ int dpm_init(void) { - struct stopwatch sw; - stopwatch_init(&sw); - if (dpm_load_firmware()) { printk(BIOS_ERR, "DPM: firmware is not ready\n"); return -1; } - printk(BIOS_INFO, "DPM: load finish in %ld msecs\n", - stopwatch_duration_msecs(&sw)); - return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5e51d1390a3daf5fac68e1180506ec0431160d2 Gerrit-Change-Number: 46932 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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