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Change in coreboot[master]: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry
by Furquan Shaikh (Code Review) 02 Dec '20

02 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48130 ) Change subject: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry ...................................................................... soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry This change drops the special check added for TGL/JSL platforms and performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later in the boot process to ensure that the memory training parameters are written back to SPI flash before performing a reset for CSE RW jump. With the recent changes in CB:44196 ("mrc_cache: Update mrc_cache data in romstage"), MRC cache is updated right away in romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I947a40cd9776342d2067c9d5a366358917466d58 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/48130/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 9c498b5..9011593 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -809,12 +809,4 @@ } } -#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE) -/* - * This needs to happen after the MRC cache write to avoid a 2nd - * memory training sequence. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL); -#else BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I947a40cd9776342d2067c9d5a366358917466d58 Gerrit-Change-Number: 48130 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/amd: factor out SMBUS controller registers into common header
by Felix Held (Code Review) 02 Dec '20

02 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48188 ) Change subject: soc/amd: factor out SMBUS controller registers into common header ...................................................................... soc/amd: factor out SMBUS controller registers into common header The patch also rewrites the bit definition using shifts to make them easier to read. The older non-SoC chips can probably also use the new header file, but for this patch the scope is limited to soc/amd, since the older non-SoC chips don't use the SMBUS controller code in soc/amd/common. TEST=Timeless build for amd/mandolin and amd/gardenia doesn't change. Change-Id: Ifd5e7e64a41f1cb20cdc4d6ad1e675d7f2de352b Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/common/block/include/amdblocks/smbus.h M src/soc/amd/common/block/smbus/smbus.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 6 files changed, 53 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/48188/1 diff --git a/src/soc/amd/common/block/include/amdblocks/smbus.h b/src/soc/amd/common/block/include/amdblocks/smbus.h new file mode 100644 index 0000000..b618b78 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/smbus.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMD_BLOCK_SMBUS_H +#define AMD_BLOCK_SMBUS_H + +/* SMBUS MMIO offsets 0xfed80a00 */ +#define SMBHSTSTAT 0x0 +#define SMBHST_STAT_FAILED (1 << 4) +#define SMBHST_STAT_COLLISION (1 << 3) +#define SMBHST_STAT_ERROR (1 << 2) +#define SMBHST_STAT_INTERRUPT (1 << 1) +#define SMBHST_STAT_BUSY (1 << 0) +#define SMBHST_STAT_CLEAR 0xff +#define SMBHST_STAT_NOERROR (1 << 1) /* TODO: this one looks odd */ +#define SMBHST_STAT_VAL_BITS 0x1f +#define SMBHST_STAT_ERROR_BITS 0x1c + +#define SMBSLVSTAT 0x1 +#define SMBSLV_STAT_ALERT (1 << 5) +#define SMBSLV_STAT_SHADOW2 (1 << 4) +#define SMBSLV_STAT_SHADOW1 (1 << 3) +#define SMBSLV_STAT_SLV_STS (1 << 2) +#define SMBSLV_STAT_SLV_INIT (1 << 1) +#define SMBSLV_STAT_SLV_BUSY (1 << 0) +#define SMBSLV_STAT_CLEAR 0x1f + +#define SMBHSTCTRL 0x2 +#define SMBHST_CTRL_RST (1 << 7) +#define SMBHST_CTRL_STRT (1 << 6) +#define SMBHST_CTRL_QCK_RW (0x0 << 2) +#define SMBHST_CTRL_BTE_RW (0x1 << 2) +#define SMBHST_CTRL_BDT_RW (0x2 << 2) +#define SMBHST_CTRL_WDT_RW (0x3 << 2) +#define SMBHST_CTRL_BLK_RW (0x5 << 2) +#define SMBHST_CTRL_MODE_BITS (0x7 << 2) +#define SMBHST_CTRL_KILL (1 << 1) +#define SMBHST_CTRL_IEN (1 << 0) + +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc +#define SMBTIMING 0xe + +#endif /* AMD_BLOCK_SMBUS_H */ diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c index e304483..e94adf5 100644 --- a/src/soc/amd/common/block/smbus/smbus.c +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -5,7 +5,7 @@ #include <device/smbus_host.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio_map.h> -#include <soc/southbridge.h> +#include <amdblocks/smbus.h> /* * Between 1-10 seconds, We should never timeout normally diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 809eb97..6fdc5ab 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -93,50 +93,6 @@ #define PM_USB_ENABLE 0xef #define PM_USB_ALL_CONTROLLERS 0x7f -/* SMBUS MMIO offsets 0xfed80a00 */ -#define SMBHSTSTAT 0x0 -#define SMBHST_STAT_FAILED BIT(4) -#define SMBHST_STAT_COLLISION BIT(3) -#define SMBHST_STAT_ERROR BIT(2) -#define SMBHST_STAT_INTERRUPT BIT(1) -#define SMBHST_STAT_BUSY BIT(0) -#define SMBHST_STAT_CLEAR 0xff -#define SMBHST_STAT_NOERROR BIT(1) -#define SMBHST_STAT_VAL_BITS 0x1f -#define SMBHST_STAT_ERROR_BITS 0x1c - -#define SMBSLVSTAT 0x1 -#define SMBSLV_STAT_ALERT 0x20 -#define SMBSLV_STAT_SHADOW2 0x10 -#define SMBSLV_STAT_SHADOW1 0x08 -#define SMBSLV_STAT_SLV_STS 0x04 -#define SMBSLV_STAT_SLV_INIT 0x02 -#define SMBSLV_STAT_SLV_BUSY 0x01 -#define SMBSLV_STAT_CLEAR 0x1f - -#define SMBHSTCTRL 0x2 -#define SMBHST_CTRL_RST 0x80 -#define SMBHST_CTRL_STRT 0x40 -#define SMBHST_CTRL_QCK_RW 0x00 -#define SMBHST_CTRL_BTE_RW 0x04 -#define SMBHST_CTRL_BDT_RW 0x08 -#define SMBHST_CTRL_WDT_RW 0x0c -#define SMBHST_CTRL_BLK_RW 0x14 -#define SMBHST_CTRL_MODE_BITS 0x1c -#define SMBHST_CTRL_KILL 0x02 -#define SMBHST_CTRL_IEN 0x01 - -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc -#define SMBTIMING 0xe - /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 #define GPP_CLK0_REQ_SHIFT 0 diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 9772e9b..edbcb60 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -17,6 +17,7 @@ #include <amdblocks/espi.h> #include <amdblocks/lpc.h> #include <amdblocks/acpi.h> +#include <amdblocks/smbus.h> #include <amdblocks/spi.h> #include <soc/acpi.h> #include <soc/cpu.h> diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 59843c1..d346197 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -89,50 +89,6 @@ #define PM_USB_ENABLE 0xef #define PM_USB_ALL_CONTROLLERS 0x7f -/* SMBUS MMIO offsets 0xfed80a00 */ -#define SMBHSTSTAT 0x0 -#define SMBHST_STAT_FAILED 0x10 -#define SMBHST_STAT_COLLISION 0x08 -#define SMBHST_STAT_ERROR 0x04 -#define SMBHST_STAT_INTERRUPT 0x02 -#define SMBHST_STAT_BUSY 0x01 -#define SMBHST_STAT_CLEAR 0xff -#define SMBHST_STAT_NOERROR 0x02 -#define SMBHST_STAT_VAL_BITS 0x1f -#define SMBHST_STAT_ERROR_BITS 0x1c - -#define SMBSLVSTAT 0x1 -#define SMBSLV_STAT_ALERT 0x20 -#define SMBSLV_STAT_SHADOW2 0x10 -#define SMBSLV_STAT_SHADOW1 0x08 -#define SMBSLV_STAT_SLV_STS 0x04 -#define SMBSLV_STAT_SLV_INIT 0x02 -#define SMBSLV_STAT_SLV_BUSY 0x01 -#define SMBSLV_STAT_CLEAR 0x1f - -#define SMBHSTCTRL 0x2 -#define SMBHST_CTRL_RST 0x80 -#define SMBHST_CTRL_STRT 0x40 -#define SMBHST_CTRL_QCK_RW 0x00 -#define SMBHST_CTRL_BTE_RW 0x04 -#define SMBHST_CTRL_BDT_RW 0x08 -#define SMBHST_CTRL_WDT_RW 0x0c -#define SMBHST_CTRL_BLK_RW 0x14 -#define SMBHST_CTRL_MODE_BITS 0x1c -#define SMBHST_CTRL_KILL 0x02 -#define SMBHST_CTRL_IEN 0x01 - -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc -#define SMBTIMING 0xe - /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 #define GPP_CLK2_REQ_MAP_SHIFT 8 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index f411179..84872ab 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -17,6 +17,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> #include <amdblocks/acpi.h> +#include <amdblocks/smbus.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/48188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd5e7e64a41f1cb20cdc4d6ad1e675d7f2de352b Gerrit-Change-Number: 48188 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/amd: factor out common AOAC device enable and status query functions
by Felix Held (Code Review) 02 Dec '20

02 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48183 ) Change subject: soc/amd: factor out common AOAC device enable and status query functions ...................................................................... soc/amd: factor out common AOAC device enable and status query functions The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is the default value after reset for those bits on both platforms. Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/common/block/aoac/Kconfig A src/soc/amd/common/block/aoac/Makefile.inc A src/soc/amd/common/block/aoac/aoac.c M src/soc/amd/common/block/include/amdblocks/aoac.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/aoac.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/uart.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/southbridge.c 10 files changed, 60 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48183/1 diff --git a/src/soc/amd/common/block/aoac/Kconfig b/src/soc/amd/common/block/aoac/Kconfig new file mode 100644 index 0000000..361a46e --- /dev/null +++ b/src/soc/amd/common/block/aoac/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_AOAC + bool + default n + help + Select this option to add the common functions for the AOAC block to + the build. diff --git a/src/soc/amd/common/block/aoac/Makefile.inc b/src/soc/amd/common/block/aoac/Makefile.inc new file mode 100644 index 0000000..4debc55 --- /dev/null +++ b/src/soc/amd/common/block/aoac/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_AOAC),y) + +bootblock-y += aoac.c +romstage-y += aoac.c +verstage-y += aoac.c +ramstage-y += aoac.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_AOAC diff --git a/src/soc/amd/common/block/aoac/aoac.c b/src/soc/amd/common/block/aoac/aoac.c new file mode 100644 index 0000000..25f4642 --- /dev/null +++ b/src/soc/amd/common/block/aoac/aoac.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> + +void power_on_aoac_device(unsigned int dev) +{ + uint8_t byte; + + /* Power on the UART and AMBA devices */ + byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); + byte |= FCH_AOAC_PWR_ON_DEV; + byte &= ~FCH_AOAC_TARGET_DEVICE_STATE; + byte |= FCH_AOAC_D0_INITIALIZED; + aoac_write8(AOAC_DEV_D3_CTL(dev), byte); +} + +void power_off_aoac_device(unsigned int dev) +{ + uint8_t byte; + + /* Power off the UART and AMBA devices */ + byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); + byte &= ~FCH_AOAC_PWR_ON_DEV; + aoac_write8(AOAC_DEV_D3_CTL(dev), byte); +} + +bool is_aoac_device_enabled(unsigned int dev) +{ + uint8_t byte; + + byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); + byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); + if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) + return true; + else + return false; +} diff --git a/src/soc/amd/common/block/include/amdblocks/aoac.h b/src/soc/amd/common/block/include/amdblocks/aoac.h index 81390b5..ea4da61 100644 --- a/src/soc/amd/common/block/include/amdblocks/aoac.h +++ b/src/soc/amd/common/block/include/amdblocks/aoac.h @@ -32,4 +32,8 @@ #define FCH_AOAC_STAT0 BIT(6) #define FCH_AOAC_STAT1 BIT(7) +bool is_aoac_device_enabled(unsigned int dev); +void power_on_aoac_device(unsigned int dev); +void power_off_aoac_device(unsigned int dev); + #endif /* AMD_BLOCK_AOAC_H */ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index c3995c8..9e9c99a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -35,6 +35,7 @@ select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_PCI diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index 21031f7..7fd839b 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -30,40 +30,6 @@ FCH_AOAC_DEV_ESPI, }; -void power_on_aoac_device(unsigned int dev) -{ - uint8_t byte; - - /* Power on the UART and AMBA devices */ - byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); - byte |= FCH_AOAC_PWR_ON_DEV; - byte &= ~FCH_AOAC_TARGET_DEVICE_STATE; - byte |= FCH_AOAC_D0_INITIALIZED; - aoac_write8(AOAC_DEV_D3_CTL(dev), byte); -} - -void power_off_aoac_device(unsigned int dev) -{ - uint8_t byte; - - /* Power off the UART and AMBA devices */ - byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); - byte &= ~FCH_AOAC_PWR_ON_DEV; - aoac_write8(AOAC_DEV_D3_CTL(dev), byte); -} - -bool is_aoac_device_enabled(unsigned int dev) -{ - uint8_t byte; - - byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); - byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); - if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) - return true; - else - return false; -} - void wait_for_aoac_enabled(unsigned int dev) { while (!is_aoac_device_enabled(dev)) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 8a2ae49..809eb97 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -247,9 +247,6 @@ } __packed aoac_devs_t; void enable_aoac_devices(void); -bool is_aoac_device_enabled(unsigned int dev); -void power_on_aoac_device(unsigned int dev); -void power_off_aoac_device(unsigned int dev); void wait_for_aoac_enabled(unsigned int dev); void sb_clk_output_48Mhz(void); void sb_enable(struct device *dev); diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 1aa42ef..a71a0e9 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -6,6 +6,7 @@ #include <device/mmio.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> #include <soc/southbridge.h> #include <soc/gpio.h> #include <soc/uart.h> diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 86df361..f24d202 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -27,6 +27,7 @@ select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_HDA diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b427c18..f411179 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -146,28 +146,6 @@ return irq_association; } -static void power_on_aoac_device(unsigned int dev) -{ - uint8_t byte; - - /* Power on the UART and AMBA devices */ - byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); - byte |= FCH_AOAC_PWR_ON_DEV; - aoac_write8(AOAC_DEV_D3_CTL(dev), byte); -} - -static bool is_aoac_device_enabled(unsigned int dev) -{ - uint8_t byte; - - byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); - byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); - if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) - return true; - else - return false; -} - void enable_aoac_devices(void) { bool status; -- To view, visit https://review.coreboot.org/c/coreboot/+/48183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754 Gerrit-Change-Number: 48183 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/amd: factor out common AOAC definitions
by Felix Held (Code Review) 02 Dec '20

02 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48182 ) Change subject: soc/amd: factor out common AOAC definitions ...................................................................... soc/amd: factor out common AOAC definitions The register locations and bit definitions are the same for Stoneyridge and Picasso. Since not all devices are present on all SoCs, keep those numbers in the SoC-specific code. Change-Id: Ib882927e399031c376738e5a35793b3d7654b9cf Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/common/block/include/amdblocks/aoac.h M src/soc/amd/picasso/aoac.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 39 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/48182/1 diff --git a/src/soc/amd/common/block/include/amdblocks/aoac.h b/src/soc/amd/common/block/include/amdblocks/aoac.h new file mode 100644 index 0000000..81390b5 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/aoac.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_AOAC_H +#define AMD_BLOCK_AOAC_H + +#include <types.h> + +/* FCH AOAC Registers 0xfed81e00 */ +#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) +#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) + +/* Bit definitions for Device D3 Control AOACx0000[40...7E] */ +#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) +#define FCH_AOAC_D0_UNINITIALIZED 0 +#define FCH_AOAC_D0_INITIALIZED 1 +#define FCH_AOAC_D1_2_3_WARM 2 +#define FCH_AOAC_D3_COLD 3 +#define FCH_AOAC_DEVICE_STATE BIT(2) +#define FCH_AOAC_PWR_ON_DEV BIT(3) +#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4) +#define FCH_AOAC_SW_REF_CLK_OK BIT(5) +#define FCH_AOAC_SW_RST_B BIT(6) +#define FCH_AOAC_IS_SW_CONTROL BIT(7) + +/* Bit definitions for Device D3 State AOACx0000[41...7f] */ +#define FCH_AOAC_PWR_RST_STATE BIT(0) +#define FCH_AOAC_RST_CLK_OK_STATE BIT(1) +#define FCH_AOAC_RST_B_STATE BIT(2) +#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3) +#define FCH_AOAC_D3COLD BIT(4) +#define FCH_AOAC_CLK_OK_STATE BIT(5) +#define FCH_AOAC_STAT0 BIT(6) +#define FCH_AOAC_STAT1 BIT(7) + +#endif /* AMD_BLOCK_AOAC_H */ diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index 00f26fe..21031f7 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -2,6 +2,7 @@ #include <stdint.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> #include <soc/southbridge.h> #include <delay.h> diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index d193661..8a2ae49 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -183,10 +183,7 @@ #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) -/* FCH AOAC Registers 0xfed81e00 */ -#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) -#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) - +/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ #define FCH_AOAC_DEV_CLK_GEN 0 #define FCH_AOAC_DEV_I2C2 7 #define FCH_AOAC_DEV_I2C3 8 @@ -198,29 +195,6 @@ #define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 -/* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */ -#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) -#define FCH_AOAC_D0_UNINITIALIZED 0 -#define FCH_AOAC_D0_INITIALIZED 1 -#define FCH_AOAC_D1_2_3_WARM 2 -#define FCH_AOAC_D3_COLD 3 -#define FCH_AOAC_DEVICE_STATE BIT(2) -#define FCH_AOAC_PWR_ON_DEV BIT(3) -#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4) -#define FCH_AOAC_SW_REF_CLK_OK BIT(5) -#define FCH_AOAC_SW_RST_B BIT(6) -#define FCH_AOAC_IS_SW_CONTROL BIT(7) - -/* Bit definitions for Device D3 State AOACx0000[41...7f] step 2 */ -#define FCH_AOAC_PWR_RST_STATE BIT(0) -#define FCH_AOAC_RST_CLK_OK_STATE BIT(1) -#define FCH_AOAC_RST_B_STATE BIT(2) -#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3) -#define FCH_AOAC_D3COLD BIT(4) -#define FCH_AOAC_CLK_OK_STATE BIT(5) -#define FCH_AOAC_STAT0 BIT(6) -#define FCH_AOAC_STAT1 BIT(7) - #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ #define FCH_LEGACY_UART_MAP_SHIFT 8 #define FCH_LEGACY_UART_MAP_SIZE 2 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9450a92..59843c1 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -189,10 +189,7 @@ #define DEBUG_PORT_ENABLE BIT(18) #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) -/* FCH AOAC Registers 0xfed81e00 */ -#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) -#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) - +/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ #define FCH_AOAC_DEV_CLK_GEN 0 #define FCH_AOAC_DEV_I2C0 5 #define FCH_AOAC_DEV_I2C1 6 @@ -204,25 +201,6 @@ #define FCH_AOAC_DEV_USB2 18 #define FCH_AOAC_DEV_USB3 23 -/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */ -#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) -#define FCH_AOAC_DEVICE_STATE BIT(2) -#define FCH_AOAC_PWR_ON_DEV BIT(3) -#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4) -#define FCH_AOAC_SW_REF_CLK_OK BIT(5) -#define FCH_AOAC_SW_RST_B BIT(6) -#define FCH_AOAC_IS_SW_CONTROL BIT(7) - -/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ -#define FCH_AOAC_PWR_RST_STATE BIT(0) -#define FCH_AOAC_RST_CLK_OK_STATE BIT(1) -#define FCH_AOAC_RST_B_STATE BIT(2) -#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3) -#define FCH_AOAC_D3COLD BIT(4) -#define FCH_AOAC_CLK_OK_STATE BIT(5) -#define FCH_AOAC_STAT0 BIT(6) -#define FCH_AOAC_STAT1 BIT(7) - #define PM1_LIMIT 16 #define GPE0_LIMIT 28 #define TOTAL_BITS(a) (8 * sizeof(a)) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 05f3072..b427c18 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -12,6 +12,7 @@ #include <acpi/acpi_gnvs.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/agesawrapper.h> +#include <amdblocks/aoac.h> #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/48182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib882927e399031c376738e5a35793b3d7654b9cf Gerrit-Change-Number: 48182 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/acpi/sb_fch: add SPI controller
by Felix Held (Code Review) 02 Dec '20

02 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47826 ) Change subject: soc/amd/picasso/acpi/sb_fch: add SPI controller ...................................................................... soc/amd/picasso/acpi/sb_fch: add SPI controller Change-Id: If1bc33dd264327f9119e1019700510ba9acca810 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/acpi/sb_fch.asl 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/47826/1 diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 6cbfc5f..5ab363d 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -19,6 +19,21 @@ } } +Device (SPI0) +{ + Name (_HID, "AMDI0061") + Name (_UID, 0) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed (ReadWrite, SPI_BASE_ADDRESS, 0x100) + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0f) + } +} + Device (GPIO) { Name (_HID, GPIO_DEVICE_NAME) -- To view, visit https://review.coreboot.org/c/coreboot/+/47826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1bc33dd264327f9119e1019700510ba9acca810 Gerrit-Change-Number: 47826 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet p...
by Mike Banon (Code Review) 02 Dec '20

02 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40495 ) Change subject: AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet patches ...................................................................... AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet patches These scripts will help you to securely and conveniently apply five changes CB:40484, CB:40485, CB:40490, CB:40488, CB:40489 to add the DDR3 XMP support. Save to ./coreboot/ then run ./get_xmp_patches.sh , ./check... and ./apply... Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ibcb04871e5d969eee1cfd49d21962ae4bbcc4e5d --- A apply_xmp_patches.sh A check_xmp_patches.sh A get_xmp_patches.sh A sha256sums_xmp_correct.txt 4 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/40495/1 diff --git a/apply_xmp_patches.sh b/apply_xmp_patches.sh new file mode 100755 index 0000000..4320ee2 --- /dev/null +++ b/apply_xmp_patches.sh @@ -0,0 +1,27 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/40484 +### nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 +### +patch -p1 < "./b8b7fb7.diff" +### +### https://review.coreboot.org/c/coreboot/+/40485 +### vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable +### +patch -p1 < "./a81f3eb.diff" +### +### https://review.coreboot.org/c/coreboot/+/40490 +### vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table +### +patch -p1 < "./bf4bd85.diff" +### +### https://review.coreboot.org/c/coreboot/+/40488 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles +### +patch -p1 < "./3b9288e.diff" +### +### https://review.coreboot.org/c/coreboot/+/40489 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile +### +patch -p1 < "./413db53.diff" +### diff --git a/check_xmp_patches.sh b/check_xmp_patches.sh new file mode 100755 index 0000000..88a0375 --- /dev/null +++ b/check_xmp_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +rm -f "./sha256sums_xmp_my.txt" +sha256sum "./b8b7fb7.diff" > "./sha256sums_xmp_my.txt" +sha256sum "./a81f3eb.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./bf4bd85.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./3b9288e.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./413db53.diff" >> "./sha256sums_xmp_my.txt" +if cmp -s "./sha256sums_xmp_my.txt" "./sha256sums_xmp_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_xmp_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_xmp_my.txt and ./sha256sums_xmp_correct.txt" + exit 1 +fi +# diff --git a/get_xmp_patches.sh b/get_xmp_patches.sh new file mode 100755 index 0000000..34eba96 --- /dev/null +++ b/get_xmp_patches.sh @@ -0,0 +1,37 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/40484 +### nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 +### +rm -f "./b8b7fb7.diff" +wget "https://review.coreboot.org/changes/40484/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./b8b7fb7.diff" +### +### https://review.coreboot.org/c/coreboot/+/40485 +### vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable +### +rm -f "./a81f3eb.diff" +wget "https://review.coreboot.org/changes/40485/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./a81f3eb.diff" +### +### https://review.coreboot.org/c/coreboot/+/40490 +### vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table +### +rm -f "./bf4bd85.diff" +wget "https://review.coreboot.org/changes/40490/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./bf4bd85.diff" +### +### https://review.coreboot.org/c/coreboot/+/40488 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles +### +rm -f "./3b9288e.diff" +wget "https://review.coreboot.org/changes/40488/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./3b9288e.diff" +### +### https://review.coreboot.org/c/coreboot/+/40489 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile +### +rm -f "./413db53.diff" +wget "https://review.coreboot.org/changes/40489/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./413db53.diff" +### diff --git a/sha256sums_xmp_correct.txt b/sha256sums_xmp_correct.txt new file mode 100644 index 0000000..e3ccb04 --- /dev/null +++ b/sha256sums_xmp_correct.txt @@ -0,0 +1,5 @@ +0b19e790c27cc4344f5427e2af62b3d8f5c729c49a528709689e4c1536e55daf ./b8b7fb7.diff +0f5816d40a56e5fe3201e539c2f6cae51a03ae606085731f3c70eb7f2a007bd5 ./a81f3eb.diff +6749bbe5a8a33b0a32d214e32ffba4b6d7df740c73fd674c344653041e5103aa ./bf4bd85.diff +4579e9a7f3454e4909789b56d2fd6422129e31185a363cf6cd13485907b82b1d ./3b9288e.diff +d5161276160d1cf4d77a5252cb7f9855d2ff5de00dedea28790627d9a144b556 ./413db53.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/40495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb04871e5d969eee1cfd49d21962ae4bbcc4e5d Gerrit-Change-Number: 40495 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile
by Mike Banon (Code Review) 02 Dec '20

02 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40489 ) Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile ...................................................................... vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile The ability to set up a custom memory profile is useful if you don't like the XMP memory profiles (if they exist) of your RAM sticks, or want to try some overclocking. Read SPD data will be overriden by your custom values. Took Crucial BLT8G3D1869DT1TX0 XMP 1 (1866MHz 9-9-9-27) as an example. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 --- M src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 10 files changed, 337 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/40489/1 diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig index 817c4b3..461b04d 100644 --- a/src/vendorcode/amd/agesa/Kconfig +++ b/src/vendorcode/amd/agesa/Kconfig @@ -38,6 +38,119 @@ help XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! +config CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + bool "CUSTOM" + help + Custom memory profile. Use the XMP SPD values as the base, if available. + +if CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + +config CUSTOM_SPD_DIVIDENT + int "[10]: Medium Timebase (MTB) Dividend" + default 1 + range 1 255 + +config CUSTOM_SPD_DIVISOR + int "[11]: Medium Timebase (MTB) Divisor" + default 14 + range 1 255 + +config CUSTOM_SPD_TCK + int "[12]: SDRAM Minimum Cycle Time, tCK" + default 15 + range 1 255 + +config CUSTOM_SPD_CASLO + int "[14]: CAS Latencies Supported, Lower Byte" + default 124 + range 0 255 + +config CUSTOM_SPD_CASHI + int "[15]: CAS Latencies Supported, Higher Byte" + default 0 + range 0 255 + +config CUSTOM_SPD_TAA + int "[16]: Min CAS Latency Time, tAA" + default 132 + range 1 255 + +config CUSTOM_SPD_TWR + int "[17]: Min Write Recovery Time, tWR" + default 210 + range 1 255 + +config CUSTOM_SPD_TRCD + int "[18]: Min RAS# to CAS# Delay Time, tRCD" + default 132 + range 1 255 + +config CUSTOM_SPD_TRRD + int "[19]: Min Row Active to Row Active Delay Time, tRRD" + default 84 + range 1 255 + +config CUSTOM_SPD_TRP + int "[20]: Min Row Precharge Delay Time, tRP" + default 132 + range 1 255 + +config CUSTOM_SPD_UPPER_TRC + int "[21][7:4]: Min Active to Active/Refresh Delay, UPPER tRC" + default 2 + range 0 16 + +config CUSTOM_SPD_UPPER_TRAS + int "[21][3:0]: Min Active to Precharge Delay Time, UPPER tRAS" + default 1 + range 0 16 + +config CUSTOM_SPD_TRAS + int "[22]: Min Active to Precharge Delay Time, LOWER tRAS" + default 138 + range 1 255 + +config CUSTOM_SPD_TRC + int "[23]: Min Active to Active/Refresh Delay, LOWER tRC" + default 181 + range 1 255 + +if CPU_AMD_AGESA_FAMILY16_KB + +config CUSTOM_SPD_TRFC_LO + int "[24]: Min Refresh Recovery Delay Time, LOWER tRFC" + default 56 + range 1 255 + +config CUSTOM_SPD_TRFC_HI + int "[25]: Min Refresh Recovery Delay Time, UPPER tRFC" + default 14 + range 0 255 + +endif + +config CUSTOM_SPD_TWTR + int "[26]: Min Internal Write to Read Command Delay, tWTR" + default 105 + range 1 255 + +config CUSTOM_SPD_TRTP + int "[27]: Min Internal Read to Precharge Command Delay, tRTP" + default 105 + range 1 255 + +config CUSTOM_SPD_UPPER_TFAW + int "[28][3:0]: Min Four Activate Window Delay, UPPER tFAW" + default 1 + range 0 16 + +config CUSTOM_SPD_TFAW + int "[29]: Min Four Activate Window Delay Time, tFAW" + default 164 + range 1 255 + +endif + endchoice endif diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 86fe800..e38e675 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -798,6 +798,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c index 392b7fc..cf3942b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c @@ -64,6 +64,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -101,6 +102,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -293,6 +304,60 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -369,6 +434,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index c7f490d..2797f80 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,7 +95,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index 70c2135..82ebab7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -2027,6 +2027,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c index f2e5848..1030d7a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c @@ -62,6 +62,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -99,6 +100,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -302,6 +313,60 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -378,6 +443,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index bbe5c12..ede7067 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,7 +94,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index 90c4e3f..4349e4e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -996,6 +996,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c index d497aec..dfc1e35 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c @@ -62,6 +62,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -99,6 +100,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -314,6 +325,62 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TRFC_LO] = CONFIG_CUSTOM_SPD_TRFC_LO; + Buffer[SPD_TRFC_HI] = CONFIG_CUSTOM_SPD_TRFC_HI; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -390,6 +457,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bc608a5..472add0 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,7 +95,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 -- To view, visit https://review.coreboot.org/c/coreboot/+/40489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 Gerrit-Change-Number: 40489 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
by Mike Banon (Code Review) 02 Dec '20

02 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40488 ) Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ...................................................................... vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles XMP memory profiles support which has been tested on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs) Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 245 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/40488/1 diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 3e3a0e9..7f85852 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -42,6 +42,10 @@ endchoice +if CPU_AMD_AGESA_OPENSOURCE +source "src/vendorcode/amd/agesa/Kconfig" +endif + if CPU_AMD_AGESA_BINARY_PI source "src/vendorcode/amd/pi/Kconfig" endif diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..817c4b3 --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,43 @@ +# +# This file is part of the coreboot project. +# +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if CPU_AMD_AGESA_FAMILY14 || CPU_AMD_AGESA_FAMILY15_TN || CPU_AMD_AGESA_FAMILY16_KB + +choice + prompt "DDR3 memory profile" + default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + help + Choose the DDR3 memory profile to use for your RAM sticks, i.e. XMP 1. + XMP support is experimental, and your PC will fail booting if you choose + a profile which does not exist on ANY of your RAM sticks! If in doubt, + check their SPD Data using a coreboot's great fork of memtest86+ 5.01. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + bool "JEDEC" + help + JEDEC memory profile, standard and stable. Is guaranteed to be working. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + bool "XMP 1" + help + XMP 1 memory profile. Check that it exists on ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + bool "XMP 2" + help + XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! + +endchoice + +endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index 3b37429..c7f490d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -103,18 +105,70 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index ab46e4a..bbe5c12 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,6 +94,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -102,18 +104,70 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bf13c7f..bc608a5 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -103,18 +105,82 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 + +#define SPD_TRFC_LO 24 +#define SPD_TRFC_HI 25 + #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 + +#define SPD_TRFC_LO 199 +#define SPD_TRFC_HI 200 + +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 + +#define SPD_TRFC_LO 234 +#define SPD_TRFC_HI 235 + +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 @@ -122,9 +188,6 @@ #define SPD_TRP_FTB 37 #define SPD_TRC_FTB 38 -#define SPD_TRFC_LO 24 -#define SPD_TRFC_HI 25 - /*----------------------------- * Jedec DDR II related equates *----------------------------- -- To view, visit https://review.coreboot.org/c/coreboot/+/40488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d Gerrit-Change-Number: 40488 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Fix compilation under x86_64
by Patrick Rudolph (Code Review) 02 Dec '20

02 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48177 ) Change subject: soc/intel/skylake: Fix compilation under x86_64 ...................................................................... soc/intel/skylake: Fix compilation under x86_64 Change-Id: I37382ab06a8f1760e955d1ec76a6a00958b05999 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/irq.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/48177/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 743b33f..98d9313 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -169,7 +169,7 @@ #if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + gnvs->cbmc = (u32)(uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); #endif if (CONFIG(CHROMEOS)) { @@ -554,7 +554,7 @@ /* Add it to DSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32) (uintptr_t)gnvs); acpigen_pop_len(); } } diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index ad75f02..2f0fd97 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -175,7 +175,7 @@ intdeventry = ARRAY_SIZE(devintconfig); /* update irq table */ memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *) - (params->DevIntConfigPtr), devintconfig, intdeventry * + (uintptr_t)(params->DevIntConfigPtr), devintconfig, intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); params->NumOfDevIntConfig = intdeventry; -- To view, visit https://review.coreboot.org/c/coreboot/+/48177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37382ab06a8f1760e955d1ec76a6a00958b05999 Gerrit-Change-Number: 48177 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Add fw_config entries for boot device
by Duncan Laurie (Code Review) 02 Dec '20

02 Dec '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48160 ) Change subject: mb/google/volteer: Add fw_config entries for boot device ...................................................................... mb/google/volteer: Add fw_config entries for boot device Add the fw_config entries for the newly added boot device fields. These are added as separate fields since a board may have more than one selected. BUG=b:173129299 TEST=abuild google/volteer Change-Id: I2af9ffcf0b90d4f4b7f2f31613ee110d8f350454 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/48160/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 455b9ab..1b3b1cc 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -46,6 +46,18 @@ option KB_LAYOUT_DEFAULT 0 option KB_LAYOUT_1 1 end + field BOOT_DEVICE_EMMC 22 + option BOOT_EMMC_DISABLED 0 + option BOOT_EMMC_ENABLED 1 + end + field BOOT_DEVICE_NVME 23 + option BOOT_NVME_DISABLED 0 + option BOOT_NVME_ENABLED 1 + end + field BOOT_DEVICE_SATA 24 + option BOOT_SATA_DISABLED 0 + option BOOT_SATA_ENABLED 1 + end end chip soc/intel/tigerlake -- To view, visit https://review.coreboot.org/c/coreboot/+/48160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2af9ffcf0b90d4f4b7f2f31613ee110d8f350454 Gerrit-Change-Number: 48160 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020