coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: soc/mediatek/mt8192: add rtc MT6359P driver
by Roger Lu (Code Review) 04 Dec '20

04 Dec '20

Hello Roger Lu, Yuchen Huang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46877 to review the following change. Change subject: soc/mediatek/mt8192: add rtc MT6359P driver ...................................................................... soc/mediatek/mt8192: add rtc MT6359P driver fix rtc for boot reason check TEST=boot asurada Signed-off-by: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Change-Id: I86b5c1b8d8ccedbb51bbc6e4c9d490c893fb4506 --- M src/soc/mediatek/common/rtc.c M src/soc/mediatek/mt8192/include/soc/rtc.h M src/soc/mediatek/mt8192/rtc.c 3 files changed, 71 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46877/1 diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index d0b90f7..5ac19eb 100755 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -141,9 +141,6 @@ rtc_info("con=%x, pwrkey1=%x, pwrkey2=%x\n", con, pwrky1, pwrky2); - if (con & RTC_CON_LPSTA_RAW) - return RTC_STATE_INIT; - if (!rtc_busy_wait()) return RTC_STATE_RECOVER; @@ -168,9 +165,11 @@ rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_write_trigger(); rtc_osc_init(); + rtc_info("RTC_STATE_REBOOT\n"); break; case RTC_STATE_RECOVER: rtc_init(1); + rtc_info("RTC_STATE_RECOVER\n"); break; case RTC_STATE_INIT: default: diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h index b1be85c..bad7c68 100755 --- a/src/soc/mediatek/mt8192/include/soc/rtc.h +++ b/src/soc/mediatek/mt8192/include/soc/rtc.h @@ -108,10 +108,18 @@ RTC_EMBCK_SRC_SEL = 1U << 8, RTC_EMBCK_SEL_OPTION = 1U << 9, RTC_GPS_CKOUT_EN = 1U << 10, + RTC_EOSC32_VCT_EN = 1U << 11, + RTC_EOSC32_CHOP_EN = 1U << 12, + RTC_GP_OSC32_CON = 2U << 13, /* Keep RG_EOSC_RSV[0] to low for lower leakage current hw design change */ RTC_REG_XOSC32_ENB = 1U << 15 }; enum { + OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | RTC_EOSC32_VCT_EN |\ + RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION | RTC_EMB_K_EOSC32_MODE +}; + +enum { RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13, RTC_LPD_OPT_EOSC_LPD = 1U << 13, RTC_LPD_OPT_XOSC_LPD = 2U << 13, @@ -142,6 +150,15 @@ PMIC_RG_FQMTR_CK_PDN_SHIFT = 11 }; +enum { + PMIC_RG_BANK_FQMTR_RST = 0x522 +}; + +enum { + PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4, + PMIC_RG_BANK_FQMTR_RST_SHIFT = 6 +}; + /* PMIC DCXO Register Definition */ enum { PMIC_RG_DCXO_CW00 = 0x0788, @@ -208,6 +225,12 @@ RTC_TC_MTH_MASK = 0xf }; +enum { + RTC_K_EOSC_RSV_0 = 1 << 8, + RTC_K_EOSC_RSV_1 = 1 << 9, + RTC_K_EOSC_RSV_2 = 1 << 10 +}; + int rtc_read(u16 addr, u16 *rdata); int rtc_write(u16 addr, u16 wdata); void rtc_write_field(u16 reg, u16 val, u16 mask, u16 shift); diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/mt8192/rtc.c index a8e28b5..f02c633 100755 --- a/src/soc/mediatek/mt8192/rtc.c +++ b/src/soc/mediatek/mt8192/rtc.c @@ -57,15 +57,12 @@ } u16 bbpu, con, osc32con, sec; - rtc_read(RTC_BBPU, &bbpu); rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_write_trigger(); rtc_read(RTC_OSC32CON, &osc32con); - osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK - | RTC_GPS_CKOUT_EN); - osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB - | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION; + osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK); + osc32con |= (OSC32CON_ANALOG_SETTING | RTC_REG_XOSC32_ENB); if (!rtc_xosc_write(osc32con)) { rtc_info("rtc_xosc_write() failed\n"); @@ -99,7 +96,7 @@ static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) { u16 bbpu, osc32con; - u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; + u16 fqmtr_busy, fqmtr_data, fqmtr_tcksel; struct stopwatch sw; if (val) { @@ -111,32 +108,34 @@ (val & RTC_XOSCCALI_MASK)); } + /* RG_BANK_FQMTR_RST=1, reset FQMTR*/ + rtc_write_field(PMIC_RG_BANK_FQMTR_RST, 1, 1, + PMIC_RG_BANK_FQMTR_RST_SHIFT); + udelay(20); + /* RG_BANK_FQMTR_RST=0, release FQMTR*/ + rtc_write_field(PMIC_RG_BANK_FQMTR_RST, 0, 1, + PMIC_RG_BANK_FQMTR_RST_SHIFT); + /* enable FQMTR clock */ rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, - PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); - rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, PMIC_RG_FQMTR_CK_PDN_SHIFT); - /* FQMTR reset */ - rtc_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT); + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); - do { - rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); - rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); - } while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY)); - rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst); - /* FQMTR normal */ - rtc_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT); + rtc_write_field(PMIC_RG_FQMTR_CON0, 1, 1, + PMIC_RG_FQMTR_DCXO26M_EN_SHIFT); + /* set frequency meter window value (0=1X32K(fixed clock)) */ rtc_write(PMIC_RG_FQMTR_WINSET, window_size); /* enable 26M and set test clock source */ rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src); /* enable 26M -> delay 100us -> enable FQMTR */ - udelay(100); + mdelay(1); rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); /* enable FQMTR */ rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN); - udelay(100); + mdelay(1); stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US); /* FQMTR read until ready */ do { @@ -149,30 +148,35 @@ /* read data should be closed to 26M/32k = 794 */ rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); - rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* disable FQMTR */ + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN); /* disable FQMTR -> delay 100us -> disable 26M */ - udelay(100); + mdelay(1); /* disable 26M */ rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN); - rtc_info("input=0x%x, output=%d\n", val, fqmtr_data); + rtc_info("input=%d, output=%d\n", val, fqmtr_data); + /* disable FQMTR clock */ rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, - PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); - rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, PMIC_RG_FQMTR_CK_PDN_SHIFT); + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + return fqmtr_data; } /* 32k clock calibration */ static u16 rtc_eosc_cali(void) { - u16 middle, diff1, diff2, cksel; + u16 diff1, diff2, cksel; u16 val = 0; - u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END; + static u16 middle = 0; + static u16 left = RTC_XOSCCALI_START; + static u16 right = RTC_XOSCCALI_END; rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); cksel &= ~PMIC_FQMTR_CKSEL_MASK; @@ -183,16 +187,20 @@ while (left <= right) { middle = (right + left) / 2; - if (middle == left) + if (middle == left) { break; + } /* select 26M as target clock */ val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); - if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) { break; - if (val > RTC_FQMTR_HIGH_BASE) + } + if (val > RTC_FQMTR_HIGH_BASE) { right = middle; - else + } + else { left = middle; + } } if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) @@ -212,6 +220,7 @@ else diff2 = RTC_FQMTR_LOW_BASE - val; + rtc_info("left:%d, middle:%d, right: %d\n", left, middle, right); if (diff1 < diff2) return left; else @@ -332,6 +341,7 @@ int rtc_init(u8 recover) { int ret; + u16 year; rtc_info("recovery: %d\n", recover); @@ -347,7 +357,7 @@ goto err; } - //rtc_osc_init(); + rtc_osc_init(); if (recover) mdelay(20); @@ -367,6 +377,11 @@ goto err; } + /* solution1 for EOSC cali*/ + rtc_read(RTC_AL_YEA, &year); + rtc_write(RTC_AL_YEA, (year | RTC_K_EOSC_RSV_0) & (~RTC_K_EOSC_RSV_1) & (~RTC_K_EOSC_RSV_2)); + rtc_write_trigger(); + if (!rtc_lpd_init()) { ret = -RTC_STATUS_LPD_INIT_FAIL; goto err; -- To view, visit https://review.coreboot.org/c/coreboot/+/46877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86b5c1b8d8ccedbb51bbc6e4c9d490c893fb4506 Gerrit-Change-Number: 46877 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Lu <roger.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Roger Lu <roger.lu(a)mediatek.com> Gerrit-Reviewer: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/mediatek/mt8192: Support SSPM
by Yidi Lin (Code Review) 04 Dec '20

04 Dec '20

Hello Erin Lo, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47346 to review the following change. Change subject: soc/mediatek/mt8192: Support SSPM ...................................................................... soc/mediatek/mt8192: Support SSPM SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> Change-Id: Ie174e8c4f4fc2055b731a3a5ee8d5b49df8af9ac --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/sspm.h A src/soc/mediatek/mt8192/sspm.c 4 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47346/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index f348a20..22674ca 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c +ramstage-y += sspm.c ramstage-y += devapc.c ramstage-y += ufs.c ramstage-y += mcupm.c diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 43a1bdc..b031b16 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -34,6 +34,8 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + SSPM_SRAM_BASE = IO_PHYS + 0x00400000, + SSPM_CFG_BASE = IO_PHYS + 0x00440000, AUXADC_BASE = IO_PHYS + 0x01001000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, diff --git a/src/soc/mediatek/mt8192/include/soc/sspm.h b/src/soc/mediatek/mt8192/include/soc/sspm.h new file mode 100644 index 0000000..5749fa4 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/sspm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_SSPM_H +#define SOC_MEDIATEK_MT8192_SSPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_sspm_regs { + u32 sw_rstn; +}; +static struct mt8192_sspm_regs *const mt8192_sspm = (void *)SSPM_CFG_BASE; +void sspm_init(void); +#endif /* SOC_MEDIATEK_MT8192_SSPM_H */ diff --git a/src/soc/mediatek/mt8192/sspm.c b/src/soc/mediatek/mt8192/sspm.c new file mode 100644 index 0000000..7f66535 --- /dev/null +++ b/src/soc/mediatek/mt8192/sspm.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/barrier.h> +#include <cbfs.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/sspm.h> +#include <string.h> + +#define BUF_SIZE (64 * KiB) +static uint8_t sspm_bin[BUF_SIZE] __aligned(8); + +void sspm_init(void) +{ + const char *file_name = "sspm.bin"; + size_t fw_size = cbfs_boot_load_file(file_name, + sspm_bin, + sizeof(sspm_bin), + CBFS_TYPE_RAW); + + if (fw_size == 0) + die("SSPM file :sspm.bin not found."); + + memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size); + /* Memory barrier to ensure that all fw code is loaded + before we release the reset pin. */ + mb(); + write32(&mt8192_sspm->sw_rstn, 0x1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie174e8c4f4fc2055b731a3a5ee8d5b49df8af9ac Gerrit-Change-Number: 47346 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: Retrieve CBI about Retimer and notify TBT firmware
by John Zhao (Code Review) 04 Dec '20

04 Dec '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46571 ) Change subject: Retrieve CBI about Retimer and notify TBT firmware ...................................................................... Retrieve CBI about Retimer and notify TBT firmware Boards might have 20 Gbps or 40 Gbps retimer respectively. It is required to inform Thunderbolt firmware about the Type-C port speed capability. This change retrieves CBI FW_CONFIG tag which has on board retimer setting and notifies LC by programming the dedicated PCIe configuration register. LC delays link establishment until it gets the port speed notification. BUG=b:163110905 TEST=booted to kernel and validated TCSS functions on Volteer boards which have 20 Gbps and 40 Gbps retimer respectively. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I0bbad465dcab5b44b1ddbd6431391b5a3a18fa12 --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 42 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46571/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 03a78fd..9a0f5c9 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -4,6 +4,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> #include <device/device.h> +#include <device/pci.h> #include <drivers/spi/tpm/tpm.h> #include <ec/ec.h> #include <fw_config.h> @@ -79,19 +80,57 @@ override_pads, override_num); } +static void mainboard_retimer_notify(struct device *dev, bool usb4_gen) +{ + uint32_t reg32; + + /* + * Program host interface PCIe configuration register TBT_DMA_CFG_VS_CAP_17 for + * 20G and 40G retimer respectively. + * TBT_DMA_CFG_VS_CAP_17[0]: "speed indication valid" - 0->invalid, 1->valid + * TBT_DMA_CFG_VS_CAP_17[1]: "speed indication value" - 0->20 Gbps, 1->40 Gbps + */ + #define TBT_DMA_CFG_VS_CAP_17 0xe8 + + reg32 = pci_read_config32(dev, TBT_DMA_CFG_VS_CAP_17); + /* Skip programming if it had previously been configured */ + if (reg32 & 0x1) + return; + + if (usb4_gen) + reg32 |= 0x2; + else + reg32 &= 0x2; + + pci_write_config32(dev, TBT_DMA_CFG_VS_CAP_17, (reg32 | 0x1)); +} + void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + struct device *dev; bool has_usb4; + bool usb4_gen2, usb4_gen3; /* If device doesn't have USB4 hardware, disable tbt */ - has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || - fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); + usb4_gen2 = fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)); + usb4_gen3 = fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)); + has_usb4 = (usb4_gen2 || usb4_gen3); - if (!has_usb4) + if (!has_usb4) { memset(params->ITbtPcieRootPortEn, 0, ARRAY_SIZE(params->ITbtPcieRootPortEn) * sizeof(*params->ITbtPcieRootPortEn)); + return; + } + + dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); + if (!dev) + return; + + /* usb4_gen2 for 20G and usb4_gen3 for 40G retimer */ + dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); + mainboard_retimer_notify(dev, ((!usb4_gen2 && usb4_gen3) ? 1 : 0)); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bbad465dcab5b44b1ddbd6431391b5a3a18fa12 Gerrit-Change-Number: 46571 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: spi/flashconsole: Fix internal buffer overflow
by Nico Huber (Code Review) 04 Dec '20

04 Dec '20

Hello Paul Menzel, Michael Niewöhner, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48074 to review the following change. Change subject: spi/flashconsole: Fix internal buffer overflow ...................................................................... spi/flashconsole: Fix internal buffer overflow Once the console's FMAP region is full, we stop clearing the line buffer and `line_offset` is not reset anymore. Hence, sanity check `line_offset` everytime before writing to the buffer. Change-Id: I36e9037d7baf8c1ed8b2d0c120bfffa58c089c95 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/spi/flashconsole.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/48074/1 diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 654177f..d5c4382 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -75,7 +75,8 @@ size_t region_size = region_device_sz(rdev_ptr); - line_buffer[line_offset++] = c; + if (line_offset < LINE_BUFFER_SIZE) + line_buffer[line_offset++] = c; if (line_offset >= LINE_BUFFER_SIZE || offset + line_offset >= region_size || c == '\n') { -- To view, visit https://review.coreboot.org/c/coreboot/+/48074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36e9037d7baf8c1ed8b2d0c120bfffa58c089c95 Gerrit-Change-Number: 48074 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: src/mainboard/hp/z220_sff_workstation/Kconfig: Add select MAINBOARD_U...
by Ao Zhong (Code Review) 04 Dec '20

04 Dec '20

Ao Zhong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48007 ) Change subject: src/mainboard/hp/z220_sff_workstation/Kconfig: Add select MAINBOARD_USES_IFD_GBE_REGION ...................................................................... src/mainboard/hp/z220_sff_workstation/Kconfig: Add select MAINBOARD_USES_IFD_GBE_REGION Add select MAINBOARD_USES_IFD_GBE_REGION to make CONFIG_HAVE_GBE_BIN (Add gigabit ethernet configuration) selection avaliable. Without that onboard Ethernet won't work. Signed-off-by: Ao Zhong <hacc1225(a)gmail.com> Change-Id: I9fe138363fc47254285ebaa4a7dbe5b94a0a8784 --- M src/mainboard/hp/z220_sff_workstation/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/48007/1 diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index b1cf89c..12643bd 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -18,6 +18,7 @@ select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT select GFX_GMA_ANALOG_I2C_HDMI_B + select MAINBOARD_USES_IFD_GBE_REGION config VBOOT select VBOOT_VBNV_CMOS -- To view, visit https://review.coreboot.org/c/coreboot/+/48007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fe138363fc47254285ebaa4a7dbe5b94a0a8784 Gerrit-Change-Number: 48007 Gerrit-PatchSet: 1 Gerrit-Owner: Ao Zhong <hacc1225(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: [TESTONLY] build with TRACE=y
by Kyösti Mälkki (Code Review) 03 Dec '20

03 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43870 ) Change subject: [TESTONLY] build with TRACE=y ...................................................................... [TESTONLY] build with TRACE=y Change-Id: Iee20e3c1fc31aba704d813f909c39986df3e2c29 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/43870/1 diff --git a/src/Kconfig b/src/Kconfig index a4c2fa6..fb7cd2d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1055,7 +1055,7 @@ config TRACE bool "Trace function calls" - default n + default y help If enabled, every function will print information to console once the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd) -- To view, visit https://review.coreboot.org/c/coreboot/+/43870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee20e3c1fc31aba704d813f909c39986df3e2c29 Gerrit-Change-Number: 43870 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: src/soc/tigerlake: Define and use a Kconfig for no of USB ports.
by Meera Ravindranath (Code Review) 03 Dec '20

03 Dec '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38682 ) Change subject: src/soc/tigerlake: Define and use a Kconfig for no of USB ports. ...................................................................... src/soc/tigerlake: Define and use a Kconfig for no of USB ports. BUG=None BRANCH=None TEST=Compilation for jasper lake board is working Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/fsp_params_jsl.c M src/soc/intel/tigerlake/fsp_params_tgl.c 3 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cef1fd0..f50e40e 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -156,6 +156,16 @@ default 3 if SOC_INTEL_JASPERLAKE default 4 if SOC_INTEL_TIGERLAKE +config SOC_INTEL_USB2_DEV_MAX + int + default 8 if SOC_INTEL_JASPERLAKE + default 10 if SOC_INTEL_TIGERLAKE + +config SOC_INTEL_USB3_DEV_MAX + int + default 6 if SOC_INTEL_JASPERLAKE + default 4 if SOC_INTEL_TIGERLAKE + config SOC_INTEL_I2C_DEV_MAX int default 6 diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 8046b2e..d5d623b 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -106,7 +106,7 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); /* USB configuration */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; @@ -116,7 +116,7 @@ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e..f027ee0 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -89,7 +89,7 @@ params->IomTypeCPortPadCfg[i] = 0x09000000; /* USB */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; @@ -98,7 +98,7 @@ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Gerrit-Change-Number: 38682 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

7 27

Change in coreboot[master]: TEST-ONLY: soc/mediatek/mt8192: workaround for samsung dram(type: 0)
by Xi Chen (Code Review) 03 Dec '20

03 Dec '20

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47987 ) Change subject: TEST-ONLY: soc/mediatek/mt8192: workaround for samsung dram(type: 0) ...................................................................... TEST-ONLY: soc/mediatek/mt8192: workaround for samsung dram(type: 0) Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I232e325af5e8ce77a1289e2001900850fadcec21 --- M src/mainboard/google/asurada/sdram_configs.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/47987/1 diff --git a/src/mainboard/google/asurada/sdram_configs.c b/src/mainboard/google/asurada/sdram_configs.c index acefada..6fbc376 100644 --- a/src/mainboard/google/asurada/sdram_configs.c +++ b/src/mainboard/google/asurada/sdram_configs.c @@ -18,10 +18,10 @@ { uint32_t ramcode = ram_code(); - if (ramcode >= ARRAY_SIZE(sdram_configs) || - cbfs_boot_load_file(sdram_configs[ramcode], &params, sizeof(params), - CBFS_TYPE_STRUCT) != sizeof(params)) + if (ramcode >= ARRAY_SIZE(sdram_configs)) die("Cannot load SDRAM parameter file for RAM code: %#x", ramcode); + // patch for samsung: dram type: 0 + params.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2; return &params; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232e325af5e8ce77a1289e2001900850fadcec21 Gerrit-Change-Number: 47987 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: x86: Put bootblock startup code into .text._start section
by Julius Werner (Code Review) 03 Dec '20

03 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46834 to review the following change. Change subject: x86: Put bootblock startup code into .text._start section ...................................................................... x86: Put bootblock startup code into .text._start section The initial bootblock assembly code on x86 is just put into the .text section, which just happens to come before all the individual .text.* function sections in the program.ld script. So it tends to be at the start of the image, bit if you inserted another linker script section with contents before .text, it would cause a problem. (I'm not sure if it's an architectural requirement for _start16bit to come at the start of the image, but at least its 4K alignment requirement would waste a lot of space if it didn't.) This patch moves the section to .text._start which is the name other architectures use for the code they want in the very front of the image and which is listed first in program.ld. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ia84e6e33ec29584d356e226e8fdcb8c9334d49af --- M src/arch/x86/bootblock_crt0.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46834/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3f41464..82ae97f 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -10,7 +10,7 @@ #include <cpu/x86/cr.h> -.section .text +.section .text._start /* * Include the old code for reset vector and protected mode entry. That code has -- To view, visit https://review.coreboot.org/c/coreboot/+/46834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia84e6e33ec29584d356e226e8fdcb8c9334d49af Gerrit-Change-Number: 46834 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

6 11

Change in coreboot[master]: cbfstool: Hide hash printing behind -v and add to parseable output
by Julius Werner (Code Review) 03 Dec '20

03 Dec '20

Hello Patrick Georgi, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41119 to review the following change. Change subject: cbfstool: Hide hash printing behind -v and add to parseable output ...................................................................... cbfstool: Hide hash printing behind -v and add to parseable output With the upcoming introduction of CBFS verification, a lot more CBFS files will have hashes. The current cbfstool default of always printing hash attributes when they exist will make cbfstool print very messy. Therefore, hide hash attribute output unless the user passed -v. It would also be useful to be able to get file attributes like hashes in machine parseable output. Unfortunately, our machine parseable format (-k) doesn't really seem designed to be extensible. To avoid breaking older parsers, this patch adds new attribute output behind -v (which hopefully no current users pass since it doesn't change anything for -k at the moment). With this patch cbfstool print -k -v may print an arbitrary amount of extra tokens behind the predefined ones on a file line. Tokens always begin with an identifying string (e.g. 'hash'), followed by extra fields that should be separated by colons. Multiple tokens are separated by the normal separator character (tab). cbfstool print -k -v may also print additional information that applies to the whole CBFS on separate lines. These lines will always begin with a '[' (which hopefully nobody would use as a CBFS filename character although we technically have no restrictions at the moment). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I9e16cda393fa0bc1d8734d4b699e30e2ae99a36d --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c 3 files changed, 41 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/41119/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 7942b27..3a83694 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1503,6 +1503,9 @@ decompressed_size ); + if (!verbose) + return 0; + struct cbfs_file_attr_hash *attr = NULL; while ((attr = cbfs_file_get_next_hash(entry, attr)) != NULL) { size_t hash_len = vb2_digest_size(attr->hash.algo); @@ -1522,9 +1525,6 @@ free(hash_str); } - if (!verbose) - return 0; - DEBUG(" cbfs_file=0x%x, offset=0x%x, content_address=0x%x+0x%x\n", cbfs_get_entry_addr(image, entry), ntohl(entry->offset), cbfs_get_entry_addr(image, entry) + ntohl(entry->offset), @@ -1587,21 +1587,45 @@ fprintf(fp, "%s%s", type, sep); fprintf(fp, "0x%zx%s", metadata_size, sep); fprintf(fp, "0x%zx%s", data_size, sep); - fprintf(fp, "0x%zx\n", metadata_size + data_size); + fprintf(fp, "0x%zx", metadata_size + data_size); + + if (verbose) { + unsigned int decompressed_size = 0; + unsigned int compression = cbfs_file_get_compression_info(entry, + &decompressed_size); + if (compression != CBFS_COMPRESS_NONE) + fprintf(fp, "%scomp:%s:0x%x", sep, lookup_name_by_type( + types_cbfs_compression, compression, "????"), + decompressed_size); + + struct cbfs_file_attr_hash *attr = NULL; + while ((attr = cbfs_file_get_next_hash(entry, attr)) != NULL) { + size_t hash_len = vb2_digest_size(attr->hash.algo); + if (!hash_len) + continue; + char *hash_str = bintohex(attr->hash.raw, hash_len); + int valid = vb2_hash_verify(CBFS_SUBHEADER(entry), + ntohl(entry->len), &attr->hash) == VB2_SUCCESS; + fprintf(fp, "%shash:%s:%s:%s", sep, + vb2_get_hash_algorithm_name(attr->hash.algo), + hash_str, valid ? "valid" : "invalid"); + free(hash_str); + } + } + fprintf(fp, "\n"); return 0; } -int cbfs_print_directory(struct cbfs_image *image) +void cbfs_print_directory(struct cbfs_image *image) { if (cbfs_is_legacy_cbfs(image)) cbfs_print_header_info(image); printf("%-30s %-10s %-12s Size Comp\n", "Name", "Offset", "Type"); cbfs_legacy_walk(image, cbfs_print_entry_info, NULL); - return 0; } -int cbfs_print_parseable_directory(struct cbfs_image *image) +void cbfs_print_parseable_directory(struct cbfs_image *image) { size_t i; const char *header[] = { @@ -1618,7 +1642,6 @@ fprintf(stdout, "%s%s", header[i], sep); fprintf(stdout, "%s\n", header[i]); cbfs_legacy_walk(image, cbfs_print_parseable_entry_info, stdout); - return 0; } int cbfs_merge_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index a3a6fb9..d633fee 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -174,8 +174,8 @@ int cbfs_is_valid_entry(struct cbfs_image *image, struct cbfs_file *entry); /* Print CBFS component information. */ -int cbfs_print_directory(struct cbfs_image *image); -int cbfs_print_parseable_directory(struct cbfs_image *image); +void cbfs_print_directory(struct cbfs_image *image); +void cbfs_print_parseable_directory(struct cbfs_image *image); int cbfs_print_header_info(struct cbfs_image *image); int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, void *arg); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index f97745e..6015603 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1087,12 +1087,16 @@ if (cbfs_image_from_buffer(&image, param.image_region, param.headeroffset)) return 1; - if (param.machine_parseable) - return cbfs_print_parseable_directory(&image); - else { + if (param.machine_parseable) { + if (verbose) + printf("[FMAP REGION]\t%s\n", param.region_name); + cbfs_print_parseable_directory(&image); + } else { printf("FMAP REGION: %s\n", param.region_name); - return cbfs_print_directory(&image); + cbfs_print_directory(&image); } + + return 0; } static int cbfs_extract(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/41119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e16cda393fa0bc1d8734d4b699e30e2ae99a36d Gerrit-Change-Number: 41119 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020