coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: mb/google/volteer/var/voema: Add MIPI camera support
by David Wu (Code Review) 05 Dec '20

05 Dec '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47668 ) Change subject: mb/google/volteer/var/voema: Add MIPI camera support ...................................................................... mb/google/volteer/var/voema: Add MIPI camera support 1. Adds VARIANT_HAS_MIPI_CAMERA to Kconfig.name 2. Adds mipi_camera.asl BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I63d133246dbdc6aff7bf97d98f95052edf53bac9 --- M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47668/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index b651430..53f1e83 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -86,4 +86,5 @@ config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl new file mode 100644 index 0000000..418f2e0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/acpi/mipi_camera.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/47668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63d133246dbdc6aff7bf97d98f95052edf53bac9 Gerrit-Change-Number: 47668 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

6 7

Change in coreboot[master]: [WIP]cpu/x86/64bit: Add code to call FSP in protected mode
by Patrick Rudolph (Code Review) 05 Dec '20

05 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48175 ) Change subject: [WIP]cpu/x86/64bit: Add code to call FSP in protected mode ...................................................................... [WIP]cpu/x86/64bit: Add code to call FSP in protected mode Change-Id: I22af2d224b546c0be9e7295330b4b6602df106d6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/cpu/x86/64bit/helper.S M src/cpu/x86/Makefile.inc M src/drivers/intel/fsp2_0/memory_init.c 3 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/48175/1 diff --git a/src/cpu/x86/64bit/helper.S b/src/cpu/x86/64bit/helper.S new file mode 100644 index 0000000..dd8f1b5 --- /dev/null +++ b/src/cpu/x86/64bit/helper.S @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifdef ENV_X86_64 +.text +.code64 + .section ".text.protected_mode_call", "ax", @progbits + .globl protected_mode_call_2arg +protected_mode_call_2arg: + + push %rbp + mov %rsp, %rbp + /* Preserve registers */ + push %rbx + push %r12 + push %r13 + push %r14 + push %r15 + + /* Arguments to stack */ + push %rdi + push %rsi + push %rdx + push %rcx + + #include <cpu/x86/64bit/exit32.inc> + + movl -48(%ebp), %eax /* Argument count */ + movl -64(%ebp), %edx /* Argument 0 */ + movl -72(%ebp), %ecx /* Argument 1 */ + + /* Align the stack */ + andl $0xFFFFFFF0, %esp + test %eax, %eax + je 1f /* Zero arguments */ + + subl $1, %eax + test %eax, %eax + je 2f /* One argument */ + + /* Two arguments */ + subl $8, %esp + pushl %ecx /* Argument 1 */ + pushl %edx /* Argument 0 */ + jmp 1f +2: + subl $12, %esp + pushl %edx /* Argument 0 */ + +1: + movl -56(%ebp), %ebx /* Function to call */ + call *%ebx + movl %eax, %ebx + + /* Preserves ebx */ + #include <cpu/x86/64bit/entry64.inc> + + /* Place return value in rax */ + movl %ebx, %eax + + /* Restore registers */ + mov -40(%rbp), %r15 + mov -32(%rbp), %r14 + mov -24(%rbp), %r13 + mov -16(%rbp), %r12 + mov -8(%rbp), %rbx + + /* Restore stack pointer */ + mov %rbp, %rsp + pop %rbp + + ret +#endif diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 2f789f7..6d0c4ac 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,4 +1,6 @@ subdirs-y += pae +all-y += 64bit/helper.S + subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-y += backup_default_smm.c diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d62888e..0f6c701 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -223,6 +223,8 @@ struct memranges memmap; }; +int protected_mode_call_2arg(size_t arg_count, uint64_t func, uint64_t arg1, uint64_t arg2); + static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) { uint32_t status; @@ -296,7 +298,11 @@ post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); +#if ENV_X86_64 + status = protected_mode_call_2arg(2, (uintptr_t)fsp_raminit, (uintptr_t)&fspm_upd, (uintptr_t)fsp_get_hob_list_ptr()); +#else status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); +#endif post_code(POST_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); -- To view, visit https://review.coreboot.org/c/coreboot/+/48175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22af2d224b546c0be9e7295330b4b6602df106d6 Gerrit-Change-Number: 48175 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: mb/google/volteer/variant/lindar: Correct SD crad reader power sequen...
by Kevin Chang (Code Review) 05 Dec '20

05 Dec '20

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47799 ) Change subject: mb/google/volteer/variant/lindar: Correct SD crad reader power sequence for lindar ...................................................................... mb/google/volteer/variant/lindar: Correct SD crad reader power sequence for lindar Modify SD card reader 3.3V power enable timing, add GPIO pin(GPP_D16) in GPIO early table.. BUG=b:173676531 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS, test USB function normally. Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f --- M src/mainboard/google/volteer/variants/lindar/gpio.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47799/1 diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c index 4f3d5f7..08f1401 100644 --- a/src/mainboard/google/volteer/variants/lindar/gpio.c +++ b/src/mainboard/google/volteer/variants/lindar/gpio.c @@ -134,6 +134,9 @@ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f Gerrit-Change-Number: 47799 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: drivers/i2c/sx9324: Add more registers and reorder
by EricR Lai (Code Review) 05 Dec '20

05 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47866 ) Change subject: drivers/i2c/sx9324: Add more registers and reorder ...................................................................... drivers/i2c/sx9324: Add more registers and reorder Export all registers that driver is looking for. And put in alphabet order. The missing registers are: reg_irq_msk reg_irq_cfg0 reg_irq_cfg2 reg_afe_ph0/1/2/3 BUG=b:172397658 BRANCH=zork TEST=Build passed Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic9d7a959b1769b6846bba302e3aeab9a3a1cedac --- M src/drivers/i2c/sx9324/registers.h 1 file changed, 32 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/47866/1 diff --git a/src/drivers/i2c/sx9324/registers.h b/src/drivers/i2c/sx9324/registers.h index 160e5e7..7d00261 100644 --- a/src/drivers/i2c/sx9324/registers.h +++ b/src/drivers/i2c/sx9324/registers.h @@ -4,29 +4,6 @@ #error "define REGISTER(NAME) before including this file" #endif -REGISTER(reg_gnrl_ctrl0); -REGISTER(reg_gnrl_ctrl1); - -REGISTER(reg_afe_ctrl0); -REGISTER(reg_afe_ctrl1); -REGISTER(reg_afe_ctrl2); -REGISTER(reg_afe_ctrl3); -REGISTER(reg_afe_ctrl4); -REGISTER(reg_afe_ctrl5); -REGISTER(reg_afe_ctrl6); -REGISTER(reg_afe_ctrl7); -REGISTER(reg_afe_ctrl8); -REGISTER(reg_afe_ctrl9); - -REGISTER(reg_prox_ctrl0); -REGISTER(reg_prox_ctrl1); -REGISTER(reg_prox_ctrl2); -REGISTER(reg_prox_ctrl3); -REGISTER(reg_prox_ctrl4); -REGISTER(reg_prox_ctrl5); -REGISTER(reg_prox_ctrl6); -REGISTER(reg_prox_ctrl7); - REGISTER(reg_adv_ctrl0); REGISTER(reg_adv_ctrl1); REGISTER(reg_adv_ctrl2); @@ -48,3 +25,35 @@ REGISTER(reg_adv_ctrl18); REGISTER(reg_adv_ctrl19); REGISTER(reg_adv_ctrl20); + +REGISTER(reg_afe_ctrl0); +REGISTER(reg_afe_ctrl1); +REGISTER(reg_afe_ctrl2); +REGISTER(reg_afe_ctrl3); +REGISTER(reg_afe_ctrl4); +REGISTER(reg_afe_ctrl5); +REGISTER(reg_afe_ctrl6); +REGISTER(reg_afe_ctrl7); +REGISTER(reg_afe_ctrl8); +REGISTER(reg_afe_ctrl9); + +REGISTER(reg_afe_ph0); +REGISTER(reg_afe_ph1); +REGISTER(reg_afe_ph2); +REGISTER(reg_afe_ph3); + +REGISTER(reg_gnrl_ctrl0); +REGISTER(reg_gnrl_ctrl1); + +REGISTER(reg_irq_msk); +REGISTER(reg_irq_cfg0); +REGISTER(reg_irq_cfg2); + +REGISTER(reg_prox_ctrl0); +REGISTER(reg_prox_ctrl1); +REGISTER(reg_prox_ctrl2); +REGISTER(reg_prox_ctrl3); +REGISTER(reg_prox_ctrl4); +REGISTER(reg_prox_ctrl5); +REGISTER(reg_prox_ctrl6); +REGISTER(reg_prox_ctrl7); -- To view, visit https://review.coreboot.org/c/coreboot/+/47866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9d7a959b1769b6846bba302e3aeab9a3a1cedac Gerrit-Change-Number: 47866 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/google/zork/var/vliboz: Add LTE_RST power sequence
by EricR Lai (Code Review) 05 Dec '20

05 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47912 ) Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ...................................................................... mb/google/zork/var/vliboz: Add LTE_RST power sequence Latest HW schematic add LTE_RST pin to control module power sequence. BUG=b:173490220 BRANCH=zork TEST=measure the waveform is meet the LTE module spec. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed --- M src/mainboard/google/zork/smihandler.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/vilboz/Makefile.inc M src/mainboard/google/zork/variants/vilboz/gpio.c M src/mainboard/google/zork/variants/vilboz/variant.c 5 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47912/1 diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 1c26d45..0b732a8 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -10,11 +10,17 @@ #include <variant/gpio.h> #include <console/console.h> +void __weak variant_smi_sleep(u8 slp_typ) +{ + /* Leave for the variant to implement if necessary. */ +} + void mainboard_smi_gpi(u32 gpi_sts) { if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_process_events(); } + void mainboard_smi_sleep(u8 slp_typ) { size_t num_gpios; @@ -26,6 +32,8 @@ gpios = variant_sleep_gpio_table(&num_gpios, slp_typ); program_gpios(gpios, num_gpios); + + variant_smi_sleep(slp_typ); } int mainboard_smi_apmc(u8 apmc) diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 4ec6add..3a360a8 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -82,5 +82,7 @@ bool variant_has_fingerprint(void); /* Return true if the board needs an extra fpmcu delay. */ bool fpmcu_needs_delay(void); +/* allow each variants to customize smi sleep flow. */ +void variant_smi_sleep(u8 slp_typ); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc index af38c88..963eee4 100644 --- a/src/mainboard/google/zork/variants/vilboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc @@ -4,3 +4,5 @@ ramstage-y += variant.c ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 6fba0e2..3ce59db 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -19,6 +19,29 @@ static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = { /* P sensor INT */ PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), + /* LTE_FW_RST_L */ + PAD_GPO(GPIO_89, HIGH), +}; + +static const struct soc_amd_gpio vilboz_early_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* LTE_FW_RST_L */ + PAD_GPO(GPIO_89, LOW), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -41,3 +64,9 @@ *size = ARRAY_SIZE(vilboz_gpio_set_stage_ram); return vilboz_gpio_set_stage_ram; } + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(vilboz_early_gpio_table); + return vilboz_early_gpio_table; +} diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index cbc160e..3d587cc 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <baseboard/variants.h> +#include <gpio.h> +#include <soc/gpio.h> #include <soc/pci_devs.h> static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { @@ -31,3 +34,11 @@ *ddi_descs = &hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); } + +void variant_smi_sleep(u8 slp_typ) +{ + if (slp_typ == ACPI_S5) { + /* Assert LTE_FW_RST_L */ + gpio_output(GPIO_89, 0); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed Gerrit-Change-Number: 47912 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: soc/intel/jasperlake: Fill software noise mitigation related UPDs
by Maulik V Vaghela (Code Review) 05 Dec '20

05 Dec '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47879 ) Change subject: soc/intel/jasperlake: Fill software noise mitigation related UPDs ...................................................................... soc/intel/jasperlake: Fill software noise mitigation related UPDs Purpose of this patch is to expose and fill software noise mitigation related parameters from coreboot so that we can fine tune noise mitigation This is work in progress patch and final patchset will allow values to be filled from devietree once values are finalized BUG=NONE BRANCH=NONE TEST=code compiles and UPDs are updated Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47879/1 diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 92c35c6..a76bea3 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -236,6 +236,25 @@ config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, config->PchPmPwrCycDur); + /* Disable Fast slew rate for Deeper C states */ + /* Note that each index is for specific VR */ + params->FastPkgCRampDisable[0] = 0x00; + params->FastPkgCRampDisable[1] = 0x00; + params->FastPkgCRampDisable[2] = 0x00; + params->FastPkgCRampDisable[3] = 0x00; + params->FastPkgCRampDisable[4] = 0x00; + + params->SlowSlewRate[0] = 0x00; + params->SlowSlewRate[1] = 0x00; + params->SlowSlewRate[2] = 0x00; + params->SlowSlewRate[3] = 0x00; + params->SlowSlewRate[4] = 0x00; + + params->AcousticNoiseMitigation = 0x00; + params->PreWake = 0x00; + params->RampUp = 0x00; + params->RampDown = 0x00; + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02 Gerrit-Change-Number: 47879 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/google/volteer: Add additional SD cards to device list
by Duncan Laurie (Code Review) 04 Dec '20

04 Dec '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48159 ) Change subject: mb/google/volteer: Add additional SD cards to device list ...................................................................... mb/google/volteer: Add additional SD cards to device list The initial commit only focused on GL9755S and RTS5261, but there were recently other cards added to the fw_config and those also need to be added to the probe lists. BUG=b:173207454 TEST=abuild google/volteer Change-Id: Ic27074a016ffbd4c4dd86104a6d85437357c4b82 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 2 files changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48159/1 diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 5080d9b..c444b4c 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -66,7 +66,7 @@ PAD_NC(GPP_R7, NONE), }; -static const struct pad_config sd_gl9755s_pads[] = { +static const struct pad_config sd_power_enable_pads[] = { PAD_CFG_GPO(GPP_D16, 1, DEEP), }; @@ -99,9 +99,12 @@ gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } - if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S))) { - printk(BIOS_INFO, "Configure GPIOs for SD GL9755S.\n"); - gpio_configure_pads(sd_gl9755s_pads, ARRAY_SIZE(sd_gl9755s_pads)); + if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S)) || + fw_config_probe(FW_CONFIG(DB_SD, SD_RTS5227S)) || + fw_config_probe(FW_CONFIG(DB_SD, SD_GL9750)) || + fw_config_probe(FW_CONFIG(DB_SD, SD_OZ711LV2LN))) { + printk(BIOS_INFO, "Configure GPIOs for SD power enable.\n"); + gpio_configure_pads(sd_power_enable_pads, ARRAY_SIZE(sd_power_enable_pads)); } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index bc1febb..455b9ab 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -39,7 +39,7 @@ option SD_GL9755S 1 option SD_RTS5261 2 option SD_RTS5227S 3 - option SD_L9750 4 + option SD_GL9750 4 option SD_OZ711LV2LN 5 end field KB_LAYOUT 20 21 @@ -459,12 +459,18 @@ device ref pcie_rp8 on probe DB_SD SD_GL9755S probe DB_SD SD_RTS5261 + probe DB_SD SD_RTS5227S + probe DB_SD SD_GL9750 + probe DB_SD SD_OZ711LV2LN chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" register "srcclk_pin" = "3" device generic 0 on probe DB_SD SD_GL9755S + probe DB_SD SD_RTS5227S + probe DB_SD SD_GL9750 + probe DB_SD SD_OZ711LV2LN end end chip soc/intel/common/block/pcie/rtd3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic27074a016ffbd4c4dd86104a6d85437357c4b82 Gerrit-Change-Number: 48159 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/google/brya: Initiate device tree
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48139 ) Change subject: mb/google/brya: Initiate device tree ...................................................................... mb/google/brya: Initiate device tree Initiate device tree based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/48139/1 diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index fbd7d72..e01c4ff 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -2,4 +2,42 @@ device cpu_cluster 0 on device lapic 0 on end end + + device domain 0 on + device ref igpu on end + device ref dptf on end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_dma0 on end + device ref tbt_dma1 on end + device ref gna on end + device ref north_xhci on end + device ref cnvi_bt on end + device ref south_xhci on end + device ref shared_ram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref heci1 on end + device ref sata on end + device ref pcie_rp1 on end #USB3-1 Type A + device ref pcie_rp4 on end #USB3-4 WWAN + device ref pcie_rp5 on end #PCIE5 WLAN + device ref pcie_rp6 on end #PCIE6 WWAN + device ref pcie_rp8 on end #PCIE8 SD card + device ref pcie_rp9 on end #PCIE9-12 SSD + device ref uart0 on end + device ref gspi0 on end + device ref gspi1 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref hda on end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/48139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd Gerrit-Change-Number: 48139 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

2 14

Change in coreboot[master]: soc/intel/alderlake: Align chipset.cb with pci_devs.h
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48153 ) Change subject: soc/intel/alderlake: Align chipset.cb with pci_devs.h ...................................................................... soc/intel/alderlake: Align chipset.cb with pci_devs.h Refer pci_devs.h naming to align chipset.cb. Correct thc0, thc1 and add cnvi_bt. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6 --- M src/soc/intel/alderlake/chipset.cb 1 file changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/48153/1 diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index ff81560..de880e3 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -13,18 +13,19 @@ device pci 08.0 alias gna off end device pci 09.0 alias north_tracehub off end device pci 0a.0 alias crashlog off end - device pci 0d.0 alias north_xhci off end - device pci 0d.1 alias north_xdci off end - device pci 0d.2 alias tbt_dma0 off end - device pci 0d.3 alias tbt_dma1 off end + device pci 0d.0 alias tcss_xhci off end + device pci 0d.1 alias tcss_xdci off end + device pci 0d.2 alias tcss_dma0 off end + device pci 0d.3 alias tcss_dma1 off end device pci 0e.0 alias vmd off end - device pci 10.6 alias thc0 off end - device pci 10.7 alias thc1 off end + device pci 10.0 alias thc0 off end + device pci 10.1 alias thc1 off end + device pci 10.2 alias cnvi_bt off end device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end device pci 13.0 alias gspi3 off end - device pci 14.0 alias south_xhci off end - device pci 14.1 alias south_xdci off end + device pci 14.0 alias xhci off end + device pci 14.1 alias usb_otg off end device pci 14.2 alias shared_sram off end device pci 14.3 alias cnvi_wifi off end device pci 15.0 alias i2c0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/48153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6 Gerrit-Change-Number: 48153 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: mb/google/brya:Add EC smihandler
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48115 ) Change subject: mb/google/brya:Add EC smihandler ...................................................................... mb/google/brya:Add EC smihandler Add implementation of EC smihandler BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48 --- M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/smihandler.c 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/48115/1 diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index ba81ff5..6f73181 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -10,6 +10,8 @@ ramstage-y += mainboard.c ramstage-y += ec.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/baseboard diff --git a/src/mainboard/google/brya/smihandler.c b/src/mainboard/google/brya/smihandler.c new file mode 100644 index 0000000..717facff --- /dev/null +++ b/src/mainboard/google/brya/smihandler.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> +#include <elog.h> +#include <intelblocks/smihandler.h> +#include <variant/ec.h> + +void mainboard_smi_gpi_handler(const struct gpi_status *sts) +{ + /* TODO: Process SMI events from GPI */ +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48 Gerrit-Change-Number: 48115 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

2 8

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020