coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: mb/google/brya: Enable EC
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48114 ) Change subject: mb/google/brya: Enable EC ...................................................................... mb/google/brya: Enable EC Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Makefile.inc M src/mainboard/google/brya/chromeos.c M src/mainboard/google/brya/dsdt.asl A src/mainboard/google/brya/ec.c M src/mainboard/google/brya/mainboard.c A src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/brya/variants/brya0/include/variant/ec.h 9 files changed, 122 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/48114/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1d29f90..89c09ae 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,6 +1,8 @@ config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n select BOARD_ROMSIZE_KB_32768 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS @@ -15,6 +17,8 @@ config CHROMEOS bool default y + select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select VBOOT_LID_SWITCH config DEVICETREE diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index 3735e20..ba81ff5 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -8,6 +8,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-y += ec.c VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index e222ca2..b6f747b 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -17,18 +17,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_lid_switch(void) -{ - /* TODO: use Chrome EC switches when EC support is added */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - /* TODO: use Chrome EC switches when EC support is added */ - return 0; -} - int get_write_protect_state(void) { /* No write protect */ diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index 5930430..50dca76 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi.h> +#include <variant/ec.h> DefinitionBlock( "dsdt.aml", @@ -29,4 +30,13 @@ /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } } diff --git a/src/mainboard/google/brya/ec.c b/src/mainboard/google/brya/ec.c new file mode 100644 index 0000000..6d0c426 --- /dev/null +++ b/src/mainboard/google/brya/ec.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <variant/ec.h> + +void mainboard_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_ERR, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 4a56f97..f4758cf 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> #include <device/device.h> +#include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(void *chip_info) @@ -19,8 +20,14 @@ return current; } +static void mainboard_dev_init(struct device *dev) +{ + mainboard_ec_init(); +} + static void mainboard_enable(struct device *dev) { + dev->ops->init = mainboard_dev_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..09906d9 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. Power button + * 3. Key press + * 4. Mode change + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) +/* + * ACPI related definitions for ASL code. + */ +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h index a708db1..6f41718 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h @@ -6,4 +6,9 @@ #include <soc/gpe.h> #include <soc/gpio.h> +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brya/variants/brya0/include/variant/ec.h b/src/mainboard/google/brya/variants/brya0/include/variant/ec.h new file mode 100644 index 0000000..4fc0622 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif /* MAINBOARD_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 Gerrit-Change-Number: 48114 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: mb/google/brya: Set UART console
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48070 ) Change subject: mb/google/brya: Set UART console ...................................................................... mb/google/brya: Set UART console Follow latest schematic UART_PCH_DBG is UART 0. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202 --- M src/mainboard/google/brya/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48070/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e448e18..4348ef5 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -31,4 +31,8 @@ string default "brya0" if BOARD_GOOGLE_BRYA0 +config UART_FOR_CONSOLE + int + default 0 + endif # BOARD_GOOGLE_BASEBOARD_BRYA -- To view, visit https://review.coreboot.org/c/coreboot/+/48070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202 Gerrit-Change-Number: 48070 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: mb/google/brya: Enable ACPI and add ACPI table
by EricR Lai (Code Review) 04 Dec '20

04 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48069 ) Change subject: mb/google/brya: Enable ACPI and add ACPI table ...................................................................... mb/google/brya: Enable ACPI and add ACPI table Enable ACPI configuration and add DSDT ACPI table. BUG=b:144768001 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/dsdt.asl M src/mainboard/google/brya/mainboard.c 3 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/48069/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 3c08757..e448e18 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SOC_INTEL_ALDERLAKE diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index 10d08e2..f15f25e 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -11,4 +11,19 @@ 0x20110725 // OEM revision ) { + /* Some generic macros */ + #include <soc/intel/common/acpi/platform.asl> + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + } + } + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index d7c3156..27a94dc 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <baseboard/variants.h> #include <device/device.h> @@ -11,9 +12,16 @@ gpio_configure_pads(pads, num); } +static unsigned long mainboard_write_acpi_tables( + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) +{ + return current; +} + static void mainboard_enable(struct device *dev) { - /* TODO: Enable mainboard */ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/48069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414 Gerrit-Change-Number: 48069 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 21

Change in coreboot[master]: mb/amd/mandolin: Unify devicetree formatting for 00:14 devices
by Paul Menzel (Code Review) 04 Dec '20

04 Dec '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46560 ) Change subject: mb/amd/mandolin: Unify devicetree formatting for 00:14 devices ...................................................................... mb/amd/mandolin: Unify devicetree formatting for 00:14 devices To accommodate also `off`, two spaces are used after `on` to align comments. This unifies the devicetree files of the two variants. Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46560/1 diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 1553288..fd07e19 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -160,8 +160,8 @@ device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.0 on end # SMBus - device pci 14.3 on # D14F3 bridge + device pci 14.0 on end # SMBus + device pci 14.3 on # D14F3 bridge chip superio/smsc/sio1036 # optional debug card end end diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index b519e4a..2651916 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -160,8 +160,8 @@ device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.0 on end # SM - device pci 14.3 on # - D14F3 bridge + device pci 14.0 on end # SMBus + device pci 14.3 on # D14F3 bridge chip superio/smsc/sio1036 # optional debug card end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62 Gerrit-Change-Number: 46560 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in comment
by Paul Menzel (Code Review) 04 Dec '20

04 Dec '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46559 ) Change subject: mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in comment ...................................................................... mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in comment This reduces the difference with Cereme’s devicetree file. Change-Id: I1e6ba5891245562d5132307eab224623031e11c8 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46559/1 diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 3de5812..b519e4a 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -148,7 +148,7 @@ device pci 8.1 on # Bridge to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocesor + device pci 0.2 on end # Crypto Coprocessor device pci 0.3 on end # USB 3.1 device pci 0.4 on end # USB 3.1 device pci 0.5 on end # Audio -- To view, visit https://review.coreboot.org/c/coreboot/+/46559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6ba5891245562d5132307eab224623031e11c8 Gerrit-Change-Number: 46559 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/common: Program SF Mask MSRs for eNEM
by Shreesh Chhabbi (Code Review) 04 Dec '20

04 Dec '20

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47983 to review the following change. Change subject: soc/common: Program SF Mask MSRs for eNEM ...................................................................... soc/common: Program SF Mask MSRs for eNEM Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Change-Id: I5781008a1447813317878a722cb894edcd6df946 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 36 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47983/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f427340..06f8c2e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -315,7 +315,7 @@ config USE_CANNONLAKE_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR - select USE_CAR_NEM_ENHANCED_V1 + select INTEL_CAR_NEM_ENHANCED help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9023b58..e66b0fb 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,21 +51,6 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -config USE_CAR_NEM_ENHANCED_V1 - bool - select INTEL_CAR_NEM_ENHANCED - help - This config supports INTEL_CAR_NEM_ENHANCED mode on - SKL, KBL, CNL, WHL, CML and ICL and JSL platforms. - -config USE_CAR_NEM_ENHANCED_V2 - bool - select INTEL_CAR_NEM_ENHANCED - select COS_MAPPED_TO_MSB - help - This config supports INTEL_CAR_NEM_ENHANCED mode on - TGL platform. - config COS_MAPPED_TO_MSB bool depends on INTEL_CAR_NEM_ENHANCED @@ -73,6 +58,14 @@ On TGL and JSL platform the class of service configuration is mapped to MSB of MSR IA32_PQR_ASSOC. +config CAR_HAS_SF_MASKS + bool + depends on INTEL_CAR_NEM_ENHANCED + help + In the case of non-inclusive cache architecture Snoop Filter MSR + IA32_L3_SF_MASK_x programming is required along with the data ways. + This is applicable for TGL and beyond. + config USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" default n diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5af1fc6..600399c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -403,8 +403,28 @@ set_eviction_mask: mov %ebx, %ecx /* back up the number of ways */ mov %eax, %ebx /* back up the non-eviction mask*/ + +#if CONFIG(CAR_HAS_SF_MASKS) /* * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 + * Program MSR 0x1891 IA32_CR_SF_QOS_MASK_1 with + * total number of LLC ways + */ + mov %ecx, %eax + movl $IA32_CR_SF_QOS_MASK_1, %ecx + xorl %edx, %edx + wrmsr + /* + * Program MSR 0x1892 IA32_CR_SF_QOS_MASK_2 with + * total number of LLC ways + */ + movl $IA32_CR_SF_QOS_MASK_2, %ecx + xorl %edx, %edx + wrmsr +#endif + + /* + * Program MSR 0xC91 IA32_L3_MASK_1 * This MSR contain one bit per each way of LLC * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction @@ -417,26 +437,18 @@ xor $~0, %eax /* invert 32 bits */ and %ecx, %eax -#if CONFIG(USE_CAR_NEM_ENHANCED_V1) movl $IA32_L3_MASK_1, %ecx -#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) - movl $IA32_CR_SF_QOS_MASK_1, %ecx -#endif xorl %edx, %edx wrmsr /* - * Set MSR 0xC92 IA32_L3_MASK_1 or MSR 0x1892 IA32_CR_SF_QOS_MASK_2 + * Program MSR 0xC92 IA32_L3_MASK_2 * This MSR contain one bit per each way of LLC * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction */ mov %ebx, %eax -#if CONFIG(USE_CAR_NEM_ENHANCED_V1) movl $IA32_L3_MASK_2, %ecx -#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) - movl $IA32_CR_SF_QOS_MASK_2, %ecx -#endif xorl %edx, %edx wrmsr /* diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 4981205..4fe491f 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -170,7 +170,7 @@ config USE_DENVERTON_NS_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR - select USE_CAR_NEM_ENHANCED_V1 + select INTEL_CAR_NEM_ENHANCED help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 52e9a74..fee52e6 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -23,6 +23,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -64,7 +65,6 @@ select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - select USE_CAR_NEM_ENHANCED_V1 config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 294f19f8..0a15f05 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -23,6 +23,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -61,7 +62,6 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202005_BINDING - select USE_CAR_NEM_ENHANCED_V1 select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ba3af84..731e033 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -32,6 +32,7 @@ select HAVE_FSP_LOGO_SUPPORT select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select HAVE_INTEL_FSP_REPO @@ -77,7 +78,6 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING - select USE_CAR_NEM_ENHANCED_V1 config FSP_HYPERTHREADING bool "Enable Hyper-Threading" diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index b97b92e..dd14ad2 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -23,7 +23,8 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select USE_CAR_NEM_ENHANCED_V1 if !INTEL_CAR_NEM + select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM + select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP -- To view, visit https://review.coreboot.org/c/coreboot/+/47983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5781008a1447813317878a722cb894edcd6df946 Gerrit-Change-Number: 47983 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: soc/mediatek/mt8183: use load_blob_file API to load SSPM
by tinghan shen (Code Review) 04 Dec '20

04 Dec '20

tinghan shen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47798 ) Change subject: soc/mediatek/mt8183: use load_blob_file API to load SSPM ...................................................................... soc/mediatek/mt8183: use load_blob_file API to load SSPM TEST=build pass Signed-off-by: TingHan.Shen <tinghan.shen(a)mediatek.com> Change-Id: Ia72c852caad0cf63f00b5a461f89725e4d7241c2 --- M src/soc/mediatek/mt8183/sspm.c 1 file changed, 4 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47798/1 diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c index efcf545..9287321 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/mt8183/sspm.c @@ -1,29 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/barrier.h> -#include <cbfs.h> -#include <console/console.h> #include <device/mmio.h> +#include <soc/mtlib_common.h> #include <soc/sspm.h> -#include <string.h> - -#define BUF_SIZE (64 * KiB) -static uint8_t sspm_bin[BUF_SIZE] __aligned(8); void sspm_init(void) { - const char *file_name = "sspm.bin"; - size_t fw_size = cbfs_boot_load_file(file_name, - sspm_bin, - sizeof(sspm_bin), - CBFS_TYPE_RAW); - - if (fw_size == 0) - die("SSPM file :sspm.bin not found."); - - memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size); - /* Memory barrier to ensure that all fw code is loaded - before we release the reset pin. */ - mb(); - write32(&mt8183_sspm->sw_rstn, 0x1); + const char *sspm_file_name = "sspm.bin"; + if (load_blob_file(sspm_file_name, SSPM_SRAM_BASE) == CB_SUCCESS) + write32(&mt8183_sspm->sw_rstn, 0x1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia72c852caad0cf63f00b5a461f89725e4d7241c2 Gerrit-Change-Number: 47798 Gerrit-PatchSet: 1 Gerrit-Owner: tinghan shen <tinghan.shen(a)mediatek.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: HACK: soc/mediatek/mt8192: Support sspm uart
by Yidi Lin (Code Review) 04 Dec '20

04 Dec '20

Hello Erin Lo, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47349 to review the following change. Change subject: HACK: soc/mediatek/mt8192: Support sspm uart ...................................................................... HACK: soc/mediatek/mt8192: Support sspm uart After rework asurada board, switch gpio pinmux Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> Change-Id: Ief8410aee7e06c32040fbae87e2360cd0bb9d441 --- M src/soc/mediatek/mt8192/sspm.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47349/1 diff --git a/src/soc/mediatek/mt8192/sspm.c b/src/soc/mediatek/mt8192/sspm.c index c9ed840..3fcc1e2 100755 --- a/src/soc/mediatek/mt8192/sspm.c +++ b/src/soc/mediatek/mt8192/sspm.c @@ -3,6 +3,7 @@ #include <arch/barrier.h> #include <cbfs.h> #include <console/console.h> +#include <soc/gpio.h> #include <device/mmio.h> #include <soc/sspm.h> #include <string.h> @@ -24,6 +25,10 @@ memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size); /* Memory barrier to ensure that all fw code is loaded before we release the reset pin. */ + + gpio_set_mode(GPIO(URXD1), 4); + gpio_set_mode(GPIO(UTXD1), 4); + mb(); write32(&mt8192_sspm->sw_rstn, 0x1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief8410aee7e06c32040fbae87e2360cd0bb9d441 Gerrit-Change-Number: 47349 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: enlarge sspm buffer size
by Yidi Lin (Code Review) 04 Dec '20

04 Dec '20

Hello Ben Ho, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47348 to review the following change. Change subject: enlarge sspm buffer size ...................................................................... enlarge sspm buffer size Signed-off-by: Ben Ho <Ben.Ho(a)mediatek.com> Change-Id: Id470399dd2167f67b3e80fe5f268f1cd0cb8fda2 --- M src/soc/mediatek/mt8192/sspm.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47348/1 diff --git a/src/soc/mediatek/mt8192/sspm.c b/src/soc/mediatek/mt8192/sspm.c old mode 100644 new mode 100755 index 7f66535..c9ed840 --- a/src/soc/mediatek/mt8192/sspm.c +++ b/src/soc/mediatek/mt8192/sspm.c @@ -7,7 +7,7 @@ #include <soc/sspm.h> #include <string.h> -#define BUF_SIZE (64 * KiB) +#define BUF_SIZE (192 * KiB) static uint8_t sspm_bin[BUF_SIZE] __aligned(8); void sspm_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/47348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id470399dd2167f67b3e80fe5f268f1cd0cb8fda2 Gerrit-Change-Number: 47348 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Ben Ho <Ben.Ho(a)mediatek.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: soc/mediatek/mt8192: Init SSPM
by Yidi Lin (Code Review) 04 Dec '20

04 Dec '20

Hello Erin Lo, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47347 to review the following change. Change subject: soc/mediatek/mt8192: Init SSPM ...................................................................... soc/mediatek/mt8192: Init SSPM Load SSPM firmware and boot up SSPM. Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> Change-Id: I051478e8bac9f48b9639ee55157ec539fe89f67c --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/soc.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47347/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 22674ca..1ba67a6 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -75,6 +75,11 @@ spm_firmware.bin-type := raw spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += sspm.bin +sspm.bin-file := $(MT8192_BLOB_DIR)/sspm.bin +sspm.bin-type := raw +sspm.bin-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += mcupm.bin mcupm.bin-file := $(MT8192_BLOB_DIR)/mcupm.bin mcupm.bin-type := raw diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 5a2fa37..883f4dc 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -5,6 +5,7 @@ #include <soc/emi.h> #include <soc/mcupm.h> #include <soc/mmu_operations.h> +#include <soc/sspm.h> #include <soc/ufs.h> #include <symbols.h> @@ -18,6 +19,7 @@ mtk_mmu_disable_l2c_sram(); dapc_init(); mcupm_init(); + sspm_init(); ufs_disable_refclk(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I051478e8bac9f48b9639ee55157ec539fe89f67c Gerrit-Change-Number: 47347 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Erin Lo <erin.lo(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 2

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020