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Change in coreboot[master]: Makefile: Allow platform to provide additional params for add cmd
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47884 ) Change subject: Makefile: Allow platform to provide additional params for add cmd ...................................................................... Makefile: Allow platform to provide additional params for add cmd This change adds optional CBFSTOOL_ADD_CMD_OPTIONS that can be used by arch/SoC/mainboard Makefiles to supply any additional arguments that need to be passed into cbfstool when using cbfstool add command. This is useful when platform wants to add these parameters depending upon some arch/SoC/mainboard specific configs. Immediate use case is the fast SPI controller on Intel platforms adding arguments for extended window base and size. BUG=b:171534504 Change-Id: I2f48bc3f494d9a5da7e99b530a39d6078b4a881c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M Makefile.inc 1 file changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/47884/1 diff --git a/Makefile.inc b/Makefile.inc index 9273961..2dc615f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -836,6 +836,10 @@ # cbfs-add-cmd-for-region # $(call cbfs-add-cmd-for-region,file in extract_nth format,region name) +# +# CBFSTOOL_ADD_CMD_OPTIONS can be used by arch/SoC/mainboard to supply +# add commands with any additional arguments for cbfstool. +# Example: --ext-win-base <base> --ext-win-size <size> define cbfs-add-cmd-for-region $(CBFSTOOL) $@.tmp \ add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if \ @@ -850,8 +854,8 @@ -r $(2) \ $(if $(call extract_nth,6,$(1)),-a $(call extract_nth,6,$(file)), \ $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file)))) \ - $(call extract_nth,7,$(1)) - + $(call extract_nth,7,$(1)) \ + $(CBFSTOOL_ADD_CMD_OPTIONS) endef # Empty line before endef is necessary so cbfs-add-cmd-for-region ends in a @@ -1086,7 +1090,8 @@ $(TXTIBB) \ $(CBNTIBB) \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ - $(TS_OPTIONS) + $(TS_OPTIONS) \ + $(CBFSTOOL_ADD_CMD_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp write -u \ -r BOOTBLOCK \ @@ -1098,10 +1103,11 @@ -f $@.tmp.2 \ -n "header pointer" \ -t "cbfs header" \ - -b -4 + -b -4 \ + $(CBFSTOOL_ADD_CMD_OPTIONS) rm -f $@.tmp.2 endif # ifeq ($(CONFIG_ARCH_X86),y) - $(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) + $(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS) $(prebuild-files) true mv $@.tmp $@ else # ifneq ($(CONFIG_UPDATE_IMAGE),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/47884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f48bc3f494d9a5da7e99b530a39d6078b4a881c Gerrit-Change-Number: 47884 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/volteer: Update I2C5 bus freq and trackpad gpio settings.
by Stanley Wu (Code Review) 08 Dec '20

08 Dec '20

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48150 ) Change subject: mb/google/volteer: Update I2C5 bus freq and trackpad gpio settings. ...................................................................... mb/google/volteer: Update I2C5 bus freq and trackpad gpio settings. Update lindar gpio settings for Synaptics trackpad no function issue. Update I2C5 bus freq to 400kHz. BUG=b:160013582 TEST=emerge-volteer coreboot and check system dmesg and evtest can get device. Verify trackpad function workable. Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf --- M src/mainboard/google/volteer/variants/lindar/gpio.c M src/mainboard/google/volteer/variants/lindar/overridetree.cb 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/48150/1 diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c index 4f3d5f7..f99ffbd 100644 --- a/src/mainboard/google/volteer/variants/lindar/gpio.c +++ b/src/mainboard/google/volteer/variants/lindar/gpio.c @@ -134,6 +134,9 @@ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E15 : ISH_GP6 ==> NC */ + PAD_NC(GPP_E15, NONE), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 2e61071..7bdb625 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -9,6 +9,44 @@ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 register "SaGv" = "SaGv_Disabled" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + .data_hold_time_ns = 0, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" # I2C Port Config register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/48150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf Gerrit-Change-Number: 48150 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: util/cbfstool: Add support for mapping extended window for x86 platforms
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47882 ) Change subject: util/cbfstool: Add support for mapping extended window for x86 platforms ...................................................................... util/cbfstool: Add support for mapping extended window for x86 platforms All x86 platforms until now have memory mapped up to a maximum of 16MiB of SPI flash just below 4G boundary in host address space. For newer platforms, cbfstool needs to be able to accommodate additional windows in the host address space for mapping SPI flash size greater than 16MiB. This change adds two input parameters to cbfstool ext-win-base and ext-win-size which a platform can use to provide the details of the extended window in host address space. The extended window does not necessarily have to be contiguous with the standard decode window below 4G. But, it is left upto the platform to ensure that the fmap sections are defined such that they do not cross the window boundary. create_mmap_windows() uses the input parameters from the platform for the extended window and the flash size to determine if extended mmap window is used. If the entire window in host address space is not covered by the SPI flash region below the top 16MiB, then mapping is assumed to be done at the top of the extended window in host space. BUG=b:171534504 Change-Id: Ie8f95993e9c690e34b0e8e792f9881c81459c6b6 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/cbfstool/cbfstool.c 1 file changed, 90 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47882/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index c0f13e7..86bc866 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -93,6 +93,18 @@ char *initrd; char *cmdline; int force; + /* + * Base and size of extended window for decoding SPI flash greater than 16MiB in host + * address space on x86 platforms. The assumptions here are: + * 1. Top 16MiB is still decoded in the fixed decode window just below 4G boundary. + * 2. Rest of the SPI flash below the top 16MiB is mapped at the top of extended + * window. Even though the platform might support a larger extended window, the SPI + * flash part used by the mainboard might not be large enough to be mapped in the entire + * window. In such cases, the mapping is assumed to be in the top part of the extended + * window with the bottom part remaining unused. + */ + uint32_t ext_win_base; + uint32_t ext_win_size; } param = { /* All variables not listed are initialized as zero. */ .arch = CBFS_ARCHITECTURE_UNKNOWN, @@ -124,6 +136,8 @@ enum mmap_window_type { X86_DEFAULT_DECODE_WINDOW, /* Decode window just below 4G boundary */ + X86_EXTENDED_DECODE_WINDOW, /* Extended decode window for mapping greater than 16MiB + flash */ MMAP_MAX_WINDOWS, }; @@ -145,25 +159,69 @@ mmap_window_table[idx].host_space.size = window_size; } -static void create_mmap_windows(void) +static bool create_mmap_windows(void) { static bool done; if (done) - return; + return done; const size_t image_size = partitioned_file_total_size(param.image_file); - const size_t window_size = MIN(16 * MiB, image_size); + const size_t std_window_size = MIN(16 * MiB, image_size); + const size_t std_window_flash_offset = image_size - std_window_size; /* * Default decode window lives just below 4G boundary in host space and maps up to a * maximum of 16MiB. If the window is smaller than 16MiB, the SPI flash window is mapped * at the top of the host window just below 4G. */ - add_mmap_window(X86_DEFAULT_DECODE_WINDOW, image_size - window_size, - 4ULL * GiB - window_size, window_size); + add_mmap_window(X86_DEFAULT_DECODE_WINDOW, std_window_flash_offset, + 4ULL * GiB - std_window_size, std_window_size); + + if (param.ext_win_size && (image_size > 16 * MiB)) { + /* + * If the platform supports extended window and the SPI flash size is greater + * than 16MiB, then create a mapping for the extended window as well. + * The assumptions here are: + * 1. Top 16MiB is still decoded in the fixed decode window just below 4G + * boundary. + * 2. Rest of the SPI flash below the top 16MiB is mapped at the top of extended + * window. Even though the platform might support a larger extended window, the + * SPI flash part used by the mainboard might not be large enough to be mapped + * in the entire window. In such cases, the mapping is assumed to be in the top + * part of the extended window with the bottom part remaining unused. + * + * Example: + * ext_win_base = 0xF8000000 + * ext_win_size = 32 * MiB + * ext_win_limit = ext_win_base + ext_win_size - 1 = 0xF9FFFFFF + * + * If SPI flash is 32MiB, then top 16MiB is mapped from 0xFF000000 - 0xFFFFFFFF + * whereas the bottom 16MiB is mapped from 0xF9000000 - 0xF9FFFFFF. The extended + * window 0xF8000000 - 0xF8FFFFFF remains unused. + */ + const size_t ext_window_mapped_size = MIN(param.ext_win_size, + image_size - std_window_size); + const size_t ext_window_top = param.ext_win_base + param.ext_win_size; + add_mmap_window(X86_EXTENDED_DECODE_WINDOW, + std_window_flash_offset - ext_window_mapped_size, + ext_window_top - ext_window_mapped_size, + ext_window_mapped_size); + + if (region_overlap(&mmap_window_table[X86_EXTENDED_DECODE_WINDOW].host_space, + &mmap_window_table[X86_DEFAULT_DECODE_WINDOW].host_space)) { + const struct region *ext_region; + + ext_region = &mmap_window_table[X86_EXTENDED_DECODE_WINDOW].host_space; + ERROR("Extended window(base=0x%zx, limit=0x%zx) overlaps with default window!\n", + region_offset(ext_region), region_end(ext_region)); + + return false; + } + } done = true; + return done; } static unsigned int convert_address(const struct region *to, const struct region *from, @@ -236,7 +294,7 @@ { assert(region); - create_mmap_windows(); + assert(create_mmap_windows()); if (IS_HOST_SPACE_ADDRESS(addr)) return convert_host_to_flash(region, addr); @@ -1410,6 +1468,8 @@ /* begin after ASCII characters */ LONGOPT_START = 256, LONGOPT_IBB = LONGOPT_START, + LONGOPT_EXT_WIN_BASE, + LONGOPT_EXT_WIN_SIZE, LONGOPT_END, }; @@ -1453,6 +1513,8 @@ {"mach-parseable",no_argument, 0, 'k' }, {"unprocessed", no_argument, 0, 'U' }, {"ibb", no_argument, 0, LONGOPT_IBB }, + {"ext-win-base", required_argument, 0, LONGOPT_EXT_WIN_BASE }, + {"ext-win-size", required_argument, 0, LONGOPT_EXT_WIN_SIZE }, {NULL, 0, 0, 0 } }; @@ -1543,11 +1605,16 @@ " -U Unprocessed; don't decompress or make ELF\n" " -v Provide verbose output\n" " -h Display this help message\n\n" + " --ext-win-base Base of extended decode window in host address\n" + " space(x86 only)\n" + " --ext-win-size Size of extended decode window in host address\n" + " space(x86 only)\n" "COMMANDs:\n" " add [-r image,regions] -f FILE -n NAME -t TYPE [-A hash] \\\n" " [-c compression] [-b base-address | -a alignment] \\\n" " [-p padding size] [-y|--xip if TYPE is FSP] \\\n" - " [-j topswap-size] (Intel CPUs only) [--ibb] " + " [-j topswap-size] (Intel CPUs only) [--ibb] \\\n" + " [--ext-win-base win-base --ext-win-size win-size] " "Add a component\n" " " " -j valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 \n" @@ -1558,7 +1625,8 @@ " add-stage [-r image,regions] -f FILE -n NAME [-A hash] \\\n" " [-c compression] [-b base] [-S section-to-ignore] \\\n" " [-a alignment] [-P page-size] [-Q|--pow2page] \\\n" - " [-y|--xip] [--ibb] " + " [-y|--xip] [--ibb] \\\n" + " [--ext-win-base win-base --ext-win-size win-size] " "Add a stage to the ROM\n" " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n" " [-A hash] -l load-address -e entry-point \\\n" @@ -1890,6 +1958,20 @@ case LONGOPT_IBB: param.ibb = true; break; + case LONGOPT_EXT_WIN_BASE: + param.ext_win_base = strtoul(optarg, &suffix, 0); + if (!*optarg || (suffix && *suffix)) { + ERROR("Invalid ext window base '%s'.\n", optarg); + return 1; + } + break; + case LONGOPT_EXT_WIN_SIZE: + param.ext_win_size = strtoul(optarg, &suffix, 0); + if (!*optarg || (suffix && *suffix)) { + ERROR("Invalid ext window size '%s'.\n", optarg); + return 1; + } + break; case 'h': case '?': usage(argv[0]); -- To view, visit https://review.coreboot.org/c/coreboot/+/47882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8f95993e9c690e34b0e8e792f9881c81459c6b6 Gerrit-Change-Number: 47882 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

5 22

Change in coreboot[master]: Add xlate_window
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47658 ) Change subject: Add xlate_window ...................................................................... Add xlate_window Change-Id: Id5b21ffca2c8d6a9dfc37a878429aed4a8301651 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/commonlib/include/commonlib/region.h M src/commonlib/region.c M src/soc/intel/apollolake/mmap_boot.c 3 files changed, 78 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47658/1 diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index b9a984f..f8e0de4 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -215,9 +215,14 @@ * space. The sub region is the window within the 1st address space and * the request is modified prior to accessing the second address space * provided by access_dev. */ -struct xlate_region_device { +struct xlate_window { const struct region_device *access_dev; struct region sub_region; +}; + +struct xlate_region_device { + size_t window_count; + const struct xlate_window *window_arr; struct region_device rdev; }; @@ -225,36 +230,28 @@ extern const struct region_device_ops xlate_rdev_rw_ops; -#define XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, sub_size_, \ - parent_sz_, ops_) \ +#define XLATE_REGION_DEV_INIT(window_count_, window_arr_, parent_sz_, ops_) \ { \ - .access_dev = access_dev_, \ - .sub_region = { \ - .offset = (sub_offset_), \ - .size = (sub_size_), \ - }, \ + .window_count = window_count_, \ + .window_arr = window_arr_, \ .rdev = REGION_DEV_INIT((ops_), 0, (parent_sz_)), \ } -#define XLATE_REGION_DEV_RO_INIT(access_dev_, sub_offset_, sub_size_, \ - parent_sz_) \ - XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \ - sub_size_, parent_sz_, &xlate_rdev_ro_ops), \ +#define XLATE_REGION_DEV_RO_INIT(window_count_, window_arr_, parent_sz_) \ + XLATE_REGION_DEV_INIT(window_count_, window_arr_, \ + parent_sz_, &xlate_rdev_ro_ops), \ -#define XLATE_REGION_DEV_RW_INIT(access_dev_, sub_offset_, sub_size_, \ - parent_sz_) \ - XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \ - sub_size_, parent_sz_, &xlate_rdev_rw_ops), \ +#define XLATE_REGION_DEV_RW_INIT(window_count_, window_arr_, parent_sz_) \ + XLATE_REGION_DEV_INIT(window_count_, window_arr_, \ + parent_sz_, &xlate_rdev_rw_ops), \ /* Helper to dynamically initialize xlate region device. */ void xlate_region_device_ro_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size); void xlate_region_device_rw_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size); /* This type can be used for incoherent access where the read and write diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 467e8ff..ece8848 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -188,33 +188,29 @@ static void xlate_region_device_init(struct xlate_region_device *xdev, const struct region_device_ops *ops, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size) { memset(xdev, 0, sizeof(*xdev)); - xdev->access_dev = access_dev; - xdev->sub_region.offset = sub_offset; - xdev->sub_region.size = sub_size; + xdev->window_count = window_count; + xdev->window_arr = window_arr; region_device_init(&xdev->rdev, ops, 0, parent_size); } void xlate_region_device_ro_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size) { - xlate_region_device_init(xdev, &xlate_rdev_ro_ops, access_dev, - sub_offset, sub_size, parent_size); + xlate_region_device_init(xdev, &xlate_rdev_ro_ops, window_count, window_arr, + parent_size); } void xlate_region_device_rw_init(struct xlate_region_device *xdev, - const struct region_device *access_dev, - size_t sub_offset, size_t sub_size, + size_t window_count, const struct xlate_window *window_arr, size_t parent_size) { - xlate_region_device_init(xdev, &xlate_rdev_rw_ops, access_dev, - sub_offset, sub_size, parent_size); + xlate_region_device_init(xdev, &xlate_rdev_rw_ops, window_count, window_arr, + parent_size); } static void *mdev_mmap(const struct region_device *rd, size_t offset, @@ -321,6 +317,21 @@ return 0; } +static const struct xlate_window *xlate_find_window(const struct xlate_region_device *xldev, + const struct region *req) +{ + size_t i; + const struct xlate_window *xlwindow; + + for (i = 0; i < xldev->window_count; i++) { + xlwindow = &xldev->window_arr[i]; + if (region_is_subregion(&xlwindow->sub_region, req)) + return xlwindow; + } + + return NULL; +} + static void *xlate_mmap(const struct region_device *rd, size_t offset, size_t size) { @@ -329,24 +340,22 @@ .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return NULL; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_mmap(xldev->access_dev, offset, size); + return rdev_mmap(xlwindow->access_dev, offset, size); } -static int xlate_munmap(const struct region_device *rd, void *mapping) +static int xlate_munmap(const struct region_device *rd __unused, void *mapping __unused) { - const struct xlate_region_device *xldev; - - xldev = container_of(rd, __typeof__(*xldev), rdev); - - return rdev_munmap(xldev->access_dev, mapping); + return 0; } static ssize_t xlate_readat(const struct region_device *rd, void *b, @@ -356,16 +365,18 @@ .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return -1; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_readat(xldev->access_dev, b, offset, size); + return rdev_readat(xlwindow->access_dev, b, offset, size); } static ssize_t xlate_writeat(const struct region_device *rd, const void *b, @@ -375,16 +386,18 @@ .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return -1; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_writeat(xldev->access_dev, b, offset, size); + return rdev_writeat(xlwindow->access_dev, b, offset, size); } static ssize_t xlate_eraseat(const struct region_device *rd, @@ -394,16 +407,18 @@ .offset = offset, .size = size, }; + const struct xlate_window *xlwindow; const struct xlate_region_device *xldev; xldev = container_of(rd, __typeof__(*xldev), rdev); - if (!region_is_subregion(&xldev->sub_region, &req)) + xlwindow = xlate_find_window(xldev, &req); + if (!xlwindow) return -1; - offset -= region_offset(&xldev->sub_region); + offset -= region_offset(&xlwindow->sub_region); - return rdev_eraseat(xldev->access_dev, offset, size); + return rdev_eraseat(xlwindow->access_dev, offset, size); } const struct region_device_ops xlate_rdev_ro_ops = { diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 30c629e..775354d 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -43,6 +43,7 @@ static struct mem_region_device shadow_dev; static struct xlate_region_device real_dev; +static struct xlate_window real_dev_window; static void bios_mmap_init(void) { @@ -68,17 +69,26 @@ mem_region_device_ro_init(&shadow_dev, (void *)base, bios_mapped_size); - xlate_region_device_ro_init(&real_dev, &shadow_dev.rdev, - start, bios_mapped_size, - CONFIG_ROM_SIZE); + real_dev_window.access_dev = &shadow_dev.rdev; + real_dev_window.sub_region.offset = start; + real_dev_window.sub_region.size = bios_mapped_size; + + xlate_region_device_ro_init(&real_dev, 1, &real_dev_window, CONFIG_ROM_SIZE); bios_size = size; /* Check that the CBFS lies within the memory mapped area. It's too easy to forget the SRAM mapping when crafting an FMAP file. */ struct region cbfs_region; - if (!fmap_locate_area("COREBOOT", &cbfs_region) && - !region_is_subregion(&real_dev.sub_region, &cbfs_region)) + void *map; + + if (fmap_locate_area("COREBOOT", &cbfs_region)) + return; + + map = rdev_mmap(&real_dev.rdev, region_offset(&cbfs_region), region_sz(&cbfs_region)); + if (map) + rdev_munmap(&real_dev.rdev, map); + else printk(BIOS_CRIT, "ERROR: CBFS @ %zx size %zx exceeds mem-mapped area @ %zx size %zx\n", region_offset(&cbfs_region), region_sz(&cbfs_region), -- To view, visit https://review.coreboot.org/c/coreboot/+/47658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b21ffca2c8d6a9dfc37a878429aed4a8301651 Gerrit-Change-Number: 47658 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: util/cbfstool/fmaptool: Generate list of terminal sections
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47883 ) Change subject: util/cbfstool/fmaptool: Generate list of terminal sections ...................................................................... util/cbfstool/fmaptool: Generate list of terminal sections This change adds support in fmaptool to generate a macro in C header file that provides a list of section names that do not have any subsections. This is useful for performing build time tests on these sections. BUG=b:171534504 Change-Id: Ie32bb8af4a722d329f9d4729722b131ca352d47a Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/cbfstool/fmaptool.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47883/1 diff --git a/util/cbfstool/fmaptool.c b/util/cbfstool/fmaptool.c index 9f5803d..4ba5967 100644 --- a/util/cbfstool/fmaptool.c +++ b/util/cbfstool/fmaptool.c @@ -14,6 +14,12 @@ #define HEADER_FMAP_OFFSET "FMAP_OFFSET" #define HEADER_FMAP_SIZE "FMAP_SIZE" +/* + * Macro name used in the generated C header file to provide list of section names that do not + * have any sub-sections. + */ +#define HEADER_FMAP_TERMINAL_SECTIONS "FMAP_TERMINAL_SECTIONS" + enum fmaptool_return { FMAPTOOL_EXIT_SUCCESS = 0, FMAPTOOL_EXIT_BAD_ARGS, @@ -71,6 +77,20 @@ fputc('\n', out); } +static void write_header_fmap_terminal_section_names(FILE *header, + const struct flashmap_descriptor *root) +{ + assert(root); + + if (root->list_len == 0) { + fprintf(header, "%s ", root->name); + return; + } + + fmd_foreach_child(child, root) + write_header_fmap_terminal_section_names(header, child); +} + static void write_header_fmap_sections(FILE *header, const struct flashmap_descriptor *root, unsigned int offset) { @@ -116,6 +136,10 @@ fprintf(header, "#define %s %#x\n", HEADER_FMAP_OFFSET, fmap_offset); fprintf(header, "#define %s %#x\n\n", HEADER_FMAP_SIZE, fmap_size); + fprintf(header, "#define %s \"", HEADER_FMAP_TERMINAL_SECTIONS); + write_header_fmap_terminal_section_names(header, root); + fprintf(header, "\"\n\n"); + write_header_fmap_sections(header, root, 0); fputs("\n", header); -- To view, visit https://review.coreboot.org/c/coreboot/+/47883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32bb8af4a722d329f9d4729722b131ca352d47a Gerrit-Change-Number: 47883 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: util/cbfstool: Rename IS_TOP_ALIGNED_ADDRESS to IS_HOST_SPACE_ADDRESS
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47830 ) Change subject: util/cbfstool: Rename IS_TOP_ALIGNED_ADDRESS to IS_HOST_SPACE_ADDRESS ...................................................................... util/cbfstool: Rename IS_TOP_ALIGNED_ADDRESS to IS_HOST_SPACE_ADDRESS This change renames the macro `IS_TOP_ALIGNED_ADDRESS` to `IS_HOST_SPACE_ADDRESS` to make it clear that the macro checks if given address is an address in the host space as opposed to the SPI flash space. Change-Id: I84bb505df62ac41f1d364a662be145603c0bd5fa Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfstool.c M util/cbfstool/common.h 3 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/47830/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 3f1bf43..da65960 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -731,7 +731,7 @@ assert(image); assert(buffer); assert(buffer->data); - assert(!IS_TOP_ALIGNED_ADDRESS(content_offset)); + assert(!IS_HOST_SPACE_ADDRESS(content_offset)); const char *name = header->filename; diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index c719b8f..061ff82 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -563,7 +563,7 @@ return -1; } - if (IS_TOP_ALIGNED_ADDRESS(offset)) + if (IS_HOST_SPACE_ADDRESS(offset)) offset = convert_to_from_absolute_top_aligned(param.image_region, -offset); if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { @@ -646,7 +646,7 @@ * passed in by the caller. */ if (param.stage_xip) { - if (!IS_TOP_ALIGNED_ADDRESS(address)) + if (!IS_HOST_SPACE_ADDRESS(address)) address = -convert_to_from_absolute_top_aligned( param.image_region, address); } else { diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 7dbc1f5..9f62e77 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -15,7 +15,12 @@ /* Endianness */ #include "swab.h" -#define IS_TOP_ALIGNED_ADDRESS(x) ((uint32_t)(x) > 0x80000000) +/* + * There are two address spaces that this tool deals with - SPI flash address space and host + * address space. This macros checks if the address is greater than 2GiB under the assumption + * that the low MMIO lives in the top half of the 4G address space of the host. + */ +#define IS_HOST_SPACE_ADDRESS(addr) ((uint32_t)(addr) > 0x80000000) #define unused __attribute__((unused)) -- To view, visit https://review.coreboot.org/c/coreboot/+/47830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bb505df62ac41f1d364a662be145603c0bd5fa Gerrit-Change-Number: 47830 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: util/cbfstool: Treat region offsets differently than absolute addresses
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47829 ) Change subject: util/cbfstool: Treat region offsets differently than absolute addresses ...................................................................... util/cbfstool: Treat region offsets differently than absolute addresses cbfstool overloads baseaddress to represent multiple things: 1. Address in SPI flash space 2. Address in host space (for x86 platforms) 3. Offset from end of region (accepted as negative number) This was done so that the different functions that use these addresses/offsets don't need to be aware of what the value represents and can use the helper functions convert_to_from* to get the required values. Thus, even if the user provides a negative value to represent offset from end of region, it was stored as an unsigned integer. There are special checks in convert_to_from_top_aligned which guesses if the value provided is really an offset from the end of region and converts it to an offset from start of region. This has worked okay until now for x86 platforms because there is a single fixed decode window mapping the SPI flash to host address space. However, going forward new platforms might need to support more decode windows that are not contiguous in the host space. Thus, it is important to distinguish between offsets from end of region and addresses in host/SPI flash space and treat them separately. As a first step towards supporting this requirement for multiple decode windows on new platforms, this change handles the negative offset provided as input in dispatch_command before the requested cbfs operation is performed. This change adds baseaddress_input, headeroffset_input and cbfsoffset_input to struct param and converts them to offsets from start of region before storing into baseaddress, headeroffset and cbfsoffset if the inputs are negative. In follow up changes, cbfstool will be extended to add support for multiple decode windows. TEST=Verified using abuild with timeless option for all coreboot boards that there is no change in the resultant coreboot.rom file. Change-Id: Ib74a7e6ed9e88fbc5489640d73bedac14872953f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfstool.c 2 files changed, 54 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47829/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index a042f0d..3f1bf43 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -277,14 +277,6 @@ bootblock_offset, bootblock->size, header_offset, sizeof(image->header), entries_offset); - // Adjust legacy top-aligned address to ROM offset. - if (IS_TOP_ALIGNED_ADDRESS(entries_offset)) - entries_offset = size + (int32_t)entries_offset; - if (IS_TOP_ALIGNED_ADDRESS(bootblock_offset)) - bootblock_offset = size + (int32_t)bootblock_offset; - if (IS_TOP_ALIGNED_ADDRESS(header_offset)) - header_offset = size + (int32_t)header_offset; - DEBUG("cbfs_create_image: (real offset) bootblock=0x%x, " "header=0x%x, entries_offset=0x%x\n", bootblock_offset, header_offset, entries_offset); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index d2df1cc..c719b8f 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -47,15 +47,22 @@ uint64_t u64val; uint32_t type; uint32_t baseaddress; + /* + * Input can be negative. It will be transformed to corresponding region offset and + * stored in baseaddress. + */ + long long int baseaddress_input; uint32_t baseaddress_assigned; uint32_t loadaddress; uint32_t headeroffset; + long long int headeroffset_input; uint32_t headeroffset_assigned; uint32_t entrypoint; uint32_t size; uint32_t alignment; uint32_t pagesize; uint32_t cbfsoffset; + long long int cbfsoffset_input; uint32_t cbfsoffset_assigned; uint32_t arch; uint32_t padding; @@ -102,8 +109,7 @@ /* * Converts between offsets from the start of the specified image region and - * "top-aligned" offsets from the top of the entire boot media. See comment - * below for convert_to_from_top_aligned() about forming addresses. + * "top-aligned" offsets from the top of the entire boot media. */ static unsigned convert_to_from_absolute_top_aligned( const struct buffer *region, unsigned offset) @@ -116,25 +122,26 @@ } /* - * Converts between offsets from the start of the specified image region and - * "top-aligned" offsets from the top of the image region. Works in either - * direction: pass in one type of offset and receive the other type. - * N.B. A top-aligned offset is always a positive number, and should not be - * confused with a top-aligned *address*, which is its arithmetic inverse. */ -static unsigned convert_to_from_top_aligned(const struct buffer *region, - unsigned offset) + * This function takes offset value which represents the offset from one end of the region and + * returns the offset from the other end of the region. offset is expected to be positive. + */ +static unsigned convert_region_offset(unsigned offset) { - assert(region); + size_t size; - /* Cover the situation where a negative base address is given by the - * user. Callers of this function negate it, so it'll be a positive - * number smaller than the region. - */ - if ((offset > 0) && (offset < region->size)) { - return region->size - offset; + if (param.size) { + size = param.size; + } else { + assert(param.image_region); + size = param.image_region->size; } - return convert_to_from_absolute_top_aligned(region, offset); + if (size < offset) { + ERROR("Cannot convert region offset (size=0x%zx, offset=0x%x\n", size, offset); + return 0; + } + + return size - offset; } static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size, @@ -242,10 +249,6 @@ goto done; } - if (IS_TOP_ALIGNED_ADDRESS(offset)) - offset = convert_to_from_top_aligned(param.image_region, - -offset); - header = cbfs_create_file_header(CBFS_COMPONENT_RAW, buffer.size, name); if (cbfs_add_entry(&image, &buffer, offset, header, 0) != 0) { @@ -434,8 +437,7 @@ buffer_clone(buffer, &new_bootblock); /* Update the location (offset) of bootblock in the region */ - *offset = convert_to_from_top_aligned(param.image_region, - buffer_size(buffer)); + *offset = convert_region_offset(buffer_size(buffer)); return 0; } @@ -519,11 +521,9 @@ /* to the cbfs file and therefore set the position */ /* the real beginning of the data. */ if (type == CBFS_COMPONENT_STAGE) - attrs->position = htonl(offset + - sizeof(struct cbfs_stage)); + attrs->position = htonl(offset - sizeof(struct cbfs_stage)); else if (type == CBFS_COMPONENT_SELF) - attrs->position = htonl(offset + - sizeof(struct cbfs_payload)); + attrs->position = htonl(offset - sizeof(struct cbfs_payload)); else attrs->position = htonl(offset); } @@ -564,8 +564,8 @@ } if (IS_TOP_ALIGNED_ADDRESS(offset)) - offset = convert_to_from_top_aligned(param.image_region, - -offset); + offset = convert_to_from_absolute_top_aligned(param.image_region, + -offset); if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); free(header); @@ -1336,6 +1336,16 @@ {NULL, 0, 0, 0 } }; +static uint32_t get_region_offset(long long int offset) +{ + /* If offset is not negative, no transformation required. */ + if (offset >= 0) + return offset; + + /* Calculate offset from start of region. */ + return convert_region_offset(-offset); +} + static int dispatch_command(struct command command) { if (command.accesses_region) { @@ -1373,6 +1383,17 @@ return 1; } } + + /* + * Once image region is read, input offsets can be adjusted accordingly if the + * inputs are provided as negative integers i.e. offsets from end of region. + */ + if (param.baseaddress_assigned) + param.baseaddress = get_region_offset(param.baseaddress_input); + if (param.headeroffset_assigned) + param.headeroffset = get_region_offset(param.headeroffset_input); + if (param.cbfsoffset_assigned) + param.cbfsoffset = get_region_offset(param.cbfsoffset_input); } if (command.function()) { @@ -1592,7 +1613,7 @@ param.source_region = optarg; break; case 'b': - param.baseaddress = strtoul(optarg, &suffix, 0); + param.baseaddress_input = strtoll(optarg, &suffix, 0); if (!*optarg || (suffix && *suffix)) { ERROR("Invalid base address '%s'.\n", optarg); @@ -1643,8 +1664,7 @@ param.bootblock = optarg; break; case 'H': - param.headeroffset = strtoul( - optarg, &suffix, 0); + param.headeroffset_input = strtoll(optarg, &suffix, 0); if (!*optarg || (suffix && *suffix)) { ERROR("Invalid header offset '%s'.\n", optarg); @@ -1680,7 +1700,7 @@ param.force_pow2_pagesize = 1; break; case 'o': - param.cbfsoffset = strtoul(optarg, &suffix, 0); + param.cbfsoffset_input = strtoll(optarg, &suffix, 0); if (!*optarg || (suffix && *suffix)) { ERROR("Invalid cbfs offset '%s'.\n", optarg); @@ -1817,6 +1837,7 @@ seen_primary_cbfs = true; param.image_region = image_regions + region; + if (dispatch_command(commands[i])) { partitioned_file_close(param.image_file); return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/47829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib74a7e6ed9e88fbc5489640d73bedac14872953f Gerrit-Change-Number: 47829 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: drivers/fsp/fsp2_0: Use more direct includes
by Patrick Rudolph (Code Review) 08 Dec '20

08 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47761 ) Change subject: drivers/fsp/fsp2_0: Use more direct includes ...................................................................... drivers/fsp/fsp2_0: Use more direct includes * Forwared declare structs in fsp/util.h * Include the correct header files in source files directly * Stop including everything in fsp/util.h and fsp/debug.h * This reduces the used headers to prevent conflicts with non FSP header files included in the following patch Change-Id: I8668608a6867876268b08cbd6d9eeafd9cd35687 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/hob_display.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/debug.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/util.c M src/soc/intel/apollolake/meminit.c 12 files changed, 21 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/47761/1 diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 3d66587..650e648 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -3,7 +3,7 @@ #include <console/console.h> #include <console/streams.h> #include <cpu/x86/mtrr.h> -#include <fsp/util.h> +#include <fsp/debug.h> asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes) { diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 60ab7cb..9d29f4e 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -6,6 +6,7 @@ #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> +#include <fsp/debug.h> #include <stdint.h> #include <string.h> diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index f21ebfe..1529148 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <console/console.h> -#include <fsp/util.h> +#include <fsp/debug.h> struct hob_type_name { uint16_t type; diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 9bfb0f1..28b45af 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -2,7 +2,7 @@ #include <cbmem.h> #include <console/console.h> -#include <fsp/util.h> +#include <fsp/debug.h> void fsp_verify_memory_init_hobs(void) { diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 97e2fea..3c2978c 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -31,6 +31,10 @@ END_OF_FIRMWARE = 0xF0 }; +struct fsp_notify_params { + enum fsp_notify_phase phase; +}; + /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(bool s3wake); diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index e3d1918..5afaec3 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -3,7 +3,9 @@ #ifndef _FSP2_0_DEBUG_H_ #define _FSP2_0_DEBUG_H_ +#include <fsp/api.h> #include <fsp/util.h> +#include <fsp/info_header.h> /* FSP debug API */ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index a57b1bb..077f9cd 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -6,8 +6,6 @@ #include <boot/coreboot_tables.h> #include <commonlib/region.h> #include <arch/cpu.h> -#include <fsp/api.h> -#include <fsp/info_header.h> #include <memrange.h> #include <program_loading.h> #include <types.h> @@ -19,10 +17,6 @@ uint16_t length; } __packed; -struct fsp_notify_params { - enum fsp_notify_phase phase; -}; - enum fsp_multi_phase_action { GET_NUMBER_OF_PHASES = 0, EXECUTE_PHASE = 1 @@ -91,6 +85,7 @@ void lb_string_platform_blob_version(struct lb_header *header); void report_fspt_output(void); +struct fsp_header; /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, const struct region_device *rdev); @@ -131,7 +126,6 @@ (void *raminit_upd, void **hob_list); typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd); typedef asmlinkage uint32_t (*fsp_multi_phase_si_init_fn)(struct fsp_multi_phase_params *); +struct fsp_notify_params; typedef asmlinkage uint32_t (*fsp_notify_fn)(struct fsp_notify_params *); -#include <fsp/debug.h> - #endif /* _FSP2_0_UTIL_H_ */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 68cc121..3542c8b 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -11,6 +11,7 @@ #include <elog.h> #include <fsp/api.h> #include <fsp/util.h> +#include <fsp/debug.h> #include <memrange.h> #include <mrc_cache.h> #include <program_loading.h> diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 76cdf12..3632fca 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -3,6 +3,9 @@ #include <bootstate.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <fsp/api.h> +#include <fsp/info_header.h> +#include <fsp/debug.h> #include <fsp/util.h> #include <timestamp.h> diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0b6540e..a9b39c0 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -6,6 +6,7 @@ #include <commonlib/stdlib.h> #include <console/console.h> #include <fsp/api.h> +#include <fsp/debug.h> #include <fsp/util.h> #include <program_loading.h> #include <soc/intel/common/vbt.h> diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index acc3f4b..3a980be 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -7,7 +7,10 @@ #include <commonlib/bsd/compression.h> #include <commonlib/fsp.h> #include <console/console.h> +#include <fsp/api.h> #include <fsp/util.h> +#include <fsp/info_header.h> +#include <fsp/debug.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 8601571..6d969b2 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <fsp/api.h> #include <fsp/util.h> #include <memory_info.h> #include <soc/meminit.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/47761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8668608a6867876268b08cbd6d9eeafd9cd35687 Gerrit-Change-Number: 47761 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: cbfs: Simplify load/map API names, remove type arguments
by Julius Werner (Code Review) 08 Dec '20

08 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39304 to review the following change. Change subject: cbfs: Simplify load/map API names, remove type arguments ...................................................................... cbfs: Simplify load/map API names, remove type arguments This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e --- M src/arch/x86/acpi.c M src/arch/x86/bootblock_normal.c M src/cpu/amd/pi/00730F01/microcode_fam16h.c M src/cpu/intel/microcode/microcode.c M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/logo.c M src/drivers/intel/fsp2_0/logo.c M src/drivers/intel/gma/opregion.c M src/drivers/pc80/rtc/option.c M src/include/cbfs.h M src/lib/bootsplash.c M src/lib/cbfs.c M src/lib/coreboot_table.c M src/lib/spd_bin.c M src/mainboard/apple/macbookair4_2/early_init.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/cyan/spd/spd.c M src/mainboard/google/dragonegg/romstage_fsp_params.c M src/mainboard/google/eve/spd/spd.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/kahlee/variants/baseboard/mainboard.c M src/mainboard/google/kahlee/variants/treeya/mainboard.c M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/link/early_init.c M src/mainboard/google/poppy/romstage.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/rambi/romstage.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c M src/mainboard/intel/harcuvar/spd/spd.c M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/lenovo/s230u/early_init.c M src/mainboard/lenovo/t430s/variants/t431s/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/early_init.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/sifive/hifive-unleashed/fixup_fdt.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/security/intel/stm/StmPlatformSmm.c M src/security/vboot/ec_sync.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/common/mma.c M src/soc/intel/denverton_ns/chip.c M src/soc/mediatek/mt8183/spm.c M src/soc/mediatek/mt8183/sspm.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/sc7180/qclib.c M src/soc/qualcomm/sdm845/qclib.c M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/eltan/security/verified_boot/vboot_check.c M src/vendorcode/google/chromeos/sar.c M src/vendorcode/siemens/hwilib/hwilib.c 70 files changed, 112 insertions(+), 166 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/39304/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index b9e896f..d96edb1 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1308,9 +1308,7 @@ return fw; } - dsdt_file = cbfs_boot_map_with_leak( - CONFIG_CBFS_PREFIX "/dsdt.aml", - CBFS_TYPE_RAW, &dsdt_size); + dsdt_file = cbfs_map(CONFIG_CBFS_PREFIX "/dsdt.aml", &dsdt_size); if (!dsdt_file) { printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n"); return current; @@ -1323,8 +1321,7 @@ return current; } - slic_file = cbfs_boot_map_with_leak(CONFIG_CBFS_PREFIX "/slic", - CBFS_TYPE_RAW, &slic_size); + slic_file = cbfs_map(CONFIG_CBFS_PREFIX "/slic", &slic_size); if (slic_file && (slic_file->length > slic_size || slic_file->length < sizeof(acpi_header_t) diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index b6b31af..f92237e 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -30,7 +30,7 @@ const char *boot_candidate; size_t stages_len; - boot_candidate = cbfs_boot_map_with_leak("coreboot-stages", CBFS_TYPE_RAW, &stages_len); + boot_candidate = cbfs_map("coreboot-stages", &stages_len); if (!boot_candidate) boot_candidate = default_filenames; diff --git a/src/cpu/amd/pi/00730F01/microcode_fam16h.c b/src/cpu/amd/pi/00730F01/microcode_fam16h.c index 1f1dbd9..88546f5 100644 --- a/src/cpu/amd/pi/00730F01/microcode_fam16h.c +++ b/src/cpu/amd/pi/00730F01/microcode_fam16h.c @@ -120,9 +120,7 @@ "Skipping microcode patch!\n"); return; } - ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, - &ucode_len); + ucode = cbfs_map("cpu_microcode_blob.bin", &ucode_len); if (!ucode) { printk(BIOS_DEBUG, "cpu_microcode_blob.bin not found. " "Skipping updates.\n"); diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 90138be..ae17d71 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -137,9 +137,7 @@ unsigned int x86_model, x86_family; msr_t msr; - ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, - CBFS_TYPE_MICROCODE, - &microcode_len); + ucode_updates = cbfs_map(MICROCODE_CBFS_FILE, &microcode_len); if (ucode_updates == NULL) return NULL; diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index bce90d9..e9f1689 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -135,9 +135,7 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt) { GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( - "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM, NULL); + pVbiosImageInfo->ImagePtr = cbfs_map("pci"CONFIG_VGA_BIOS_ID".rom", NULL); /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 1678f84..7297ba4 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -42,8 +42,7 @@ const void *agesa, *image; size_t file_size; - agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME, - CBFS_TYPE_RAW, &file_size); + agesa = cbfs_map((const char *)CONFIG_AGESA_CBFS_NAME, &file_size); if (agesa == NULL) return; diff --git a/src/drivers/intel/fsp1_1/logo.c b/src/drivers/intel/fsp1_1/logo.c index b00406d..5dd8202 100644 --- a/src/drivers/intel/fsp1_1/logo.c +++ b/src/drivers/intel/fsp1_1/logo.c @@ -24,8 +24,8 @@ if (logo_entry) { logo_buffer = cbmem_entry_start(logo_entry); if (logo_buffer) { - *logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer, - 1 * MiB, CBFS_TYPE_RAW); + *logo_size = cbfs_load("logo.bmp", (void *)logo_buffer, + 1 * MiB); if (*logo_size) *logo_ptr = (UINT32)logo_buffer; } diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c index 1a9152f..3c95fef 100644 --- a/src/drivers/intel/fsp2_0/logo.c +++ b/src/drivers/intel/fsp2_0/logo.c @@ -24,8 +24,8 @@ if (logo_entry) { logo_buffer = cbmem_entry_start(logo_entry); if (logo_buffer) { - *logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer, - 1 * MiB, CBFS_TYPE_RAW); + *logo_size = cbfs_load("logo.bmp", (void *)logo_buffer, + 1 * MiB); if (*logo_size) *logo_ptr = (UINT32)logo_buffer; } diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 56449d0..8cb7fcd 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -46,8 +46,7 @@ const char *filename = mainboard_vbt_filename(); - size_t file_size = cbfs_boot_load_file(filename, - vbt_data, sizeof(vbt_data), CBFS_TYPE_RAW); + size_t file_size = cbfs_load(filename, vbt_data, sizeof(vbt_data)); if (file_size == 0) return NULL; diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index bb697df..4789b15 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -244,9 +244,7 @@ size_t length = 128; size_t i; - const unsigned char *cmos_default = - cbfs_boot_map_with_leak("cmos.default", - CBFS_COMPONENT_CMOS_DEFAULT, &length); + const unsigned char *cmos_default = cbfs_map("cmos.default", &length); if (!cmos_default) return; diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 82c92d7..cc61b16 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -31,19 +31,22 @@ void *cbfs_boot_load_stage_by_name(const char *name); /* Locate file by name and optional type. Return 0 on success. < 0 on error. */ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); -/* Map file into memory leaking the mapping. Only should be used when - * leaking mappings are a no-op. Returns NULL on error, else returns - * the mapping and sets the size of the file. */ -void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); +/* Map file into memory, returning a pointer to the mapping or NULL on error. + If |size| is not NULL, it will pass out the size of the mapped file. + NOTE: Since this may return a direct pointer to memory-mapped hardware, + compressed files are NOT transparently decompressed (unlike cbfs_load()). */ +void *cbfs_map(const char *name, size_t *size); +/* Removes a mapping previously allocated with cbfs_map(). Should try to unmap + mappings in strict LIFO order where possible, since mapping backends often + don't support more complicated cases. */ +int cbfs_unmap(void *mapping); /* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, const char *name, uint32_t *type); -/* Load an arbitrary type file from CBFS into a buffer. Returns amount of - * loaded bytes on success or 0 on error. File will get decompressed as - * necessary. Same decompression requirements as - * cbfs_load_and_decompress(). */ -size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, - uint32_t type); +/* Load a file from CBFS into a buffer. Returns amount of loaded bytes on + success or 0 on error. File will get decompressed as necessary. Same + decompression requirements as cbfs_load_and_decompress(). */ +size_t cbfs_load(const char *name, void *buf, size_t buf_size); /* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes * large |buffer|, decompressing it according to |compression| in the process. * Returns the decompressed file size, or 0 on error. diff --git a/src/lib/bootsplash.c b/src/lib/bootsplash.c index 8364afa..3f96907 100644 --- a/src/lib/bootsplash.c +++ b/src/lib/bootsplash.c @@ -29,8 +29,7 @@ printk(BIOS_INFO, "Setting up bootsplash in %dx%d@%d\n", x_resolution, y_resolution, fb_resolution); struct jpeg_decdata *decdata; - unsigned char *jpeg = - cbfs_boot_map_with_leak("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH, NULL); + unsigned char *jpeg = cbfs_map("bootsplash.jpg", NULL); if (!jpeg) { printk(BIOS_ERR, "Could not find bootsplash.jpg\n"); return; @@ -44,6 +43,7 @@ decdata = malloc(sizeof(*decdata)); int ret = jpeg_decode(jpeg, framebuffer, x_resolution, y_resolution, fb_resolution, decdata); + cbfs_unmap(jpeg); if (ret != 0) { printk(BIOS_ERR, "Bootsplash could not be decoded. jpeg_decode returned %d.\n", ret); diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 39db97a..bece4d0 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -79,12 +79,12 @@ return 0; } -void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) +void *cbfs_map(const char *name, size_t *size) { struct cbfsf fh; size_t fsize; - if (cbfs_boot_locate(&fh, name, &type)) + if (cbfs_boot_locate(&fh, name, NULL)) return NULL; fsize = region_device_sz(&fh.data); @@ -95,6 +95,13 @@ return rdev_mmap(&fh.data, 0, fsize); } +int cbfs_unmap(void *mapping) +{ + /* This works because munmap() only works on the root rdev and never + cares about which chained subregion something was mapped from. */ + return rdev_munmap(boot_device_ro(), mapping); +} + int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, const char *name, uint32_t *type) { @@ -187,16 +194,15 @@ tohex16(vendor, name + 3); tohex16(device, name + 8); - return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); + return cbfs_map(name, NULL); } void *cbfs_boot_load_stage_by_name(const char *name) { struct cbfsf fh; struct prog stage = PROG_INIT(PROG_UNKNOWN, name); - uint32_t type = CBFS_TYPE_STAGE; - if (cbfs_boot_locate(&fh, name, &type)) + if (cbfs_boot_locate(&fh, name, NULL)) return NULL; /* Chain data portion in the prog. */ @@ -208,14 +214,13 @@ return prog_entry(&stage); } -size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, - uint32_t type) +size_t cbfs_load(const char *name, void *buf, size_t buf_size) { struct cbfsf fh; uint32_t compression_algo; size_t decompressed_size; - if (cbfs_boot_locate(&fh, name, &type) < 0) + if (cbfs_boot_locate(&fh, name, NULL) < 0) return 0; if (cbfsf_decompression_info(&fh, &compression_algo, diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 91e0247..78ecb5a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -494,8 +494,7 @@ #if CONFIG(USE_OPTION_TABLE) { struct cmos_option_table *option_table = - cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + cbfs_map("cmos_layout.bin", NULL); if (option_table) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 9e625b5..41588d7 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -209,8 +209,7 @@ size_t spd_file_len = 0; size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); if (spd_file_len < min_len) @@ -220,6 +219,7 @@ memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); + cbfs_unmap(spd_file); u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); diff --git a/src/mainboard/apple/macbookair4_2/early_init.c b/src/mainboard/apple/macbookair4_2/early_init.c index 29a2977..69e26f0 100644 --- a/src/mainboard/apple/macbookair4_2/early_init.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -39,8 +39,7 @@ { void *spd_file; size_t spd_file_len = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (spd_file && spd_file_len >= 1024) { int i; for (i = 0; i < 4; i++) diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 2991d15..f08e0a4 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -101,7 +101,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 2991d15..f08e0a4 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -101,7 +101,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 4e05711..31f4cc1 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -140,9 +140,7 @@ search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 2991d15..f08e0a4 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -101,7 +101,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index bd76947..94f9346 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -106,7 +106,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index ffb90f9..6ff6d77 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -101,7 +101,7 @@ spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c index 1c38e45..8e8b44d 100644 --- a/src/mainboard/google/beltino/lan.c +++ b/src/mainboard/google/beltino/lan.c @@ -123,9 +123,7 @@ search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index eb4d15b..9bbb700 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -195,8 +195,7 @@ } } } else { - vpd_file = cbfs_boot_map_with_leak("vpd.bin", CBFS_TYPE_RAW, - &search_length); + vpd_file = cbfs_map("vpd.bin", &search_length); if (vpd_file) { search_address = (unsigned long)vpd_file; } else { diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 8dd4366..e08234a 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -49,8 +49,7 @@ int spd_index = 0; /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c index f1f5143..e6573ad 100644 --- a/src/mainboard/google/dragonegg/romstage_fsp_params.c +++ b/src/mainboard/google/dragonegg/romstage_fsp_params.c @@ -32,8 +32,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map(spd_bin, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index fca670c..a03d077 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -96,8 +96,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 324d3be..68d840d 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -93,8 +93,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 5e9e15f..25719bc 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -66,8 +66,7 @@ if (ramcode >= ARRAY_SIZE(sdram_configs) || !snprintf(config_file, sizeof(config_file), "%s-%d", sdram_configs[ramcode], get_sdram_target_mhz()) || - (cbfs_boot_load_file(config_file, &params, sizeof(params), - CBFS_TYPE_STRUCT) != sizeof(params))) + (cbfs_load(config_file, &params, sizeof(params)) != sizeof(params))) die("Cannot load SDRAM parameter file!"); return &params; diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index bd08b09..fde59a7 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -123,9 +123,7 @@ search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 69b9b40..2bada6e 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -103,9 +103,7 @@ if (manuf) return manuf; - if (cbfs_boot_load_file("oem.bin", oem_bin_data, - sizeof(oem_bin_data) - 1, - CBFS_TYPE_RAW)) + if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) manuf = &oem_bin_data[0]; else manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; diff --git a/src/mainboard/google/kahlee/variants/treeya/mainboard.c b/src/mainboard/google/kahlee/variants/treeya/mainboard.c index cd42b56..9639977 100644 --- a/src/mainboard/google/kahlee/variants/treeya/mainboard.c +++ b/src/mainboard/google/kahlee/variants/treeya/mainboard.c @@ -115,9 +115,7 @@ if (manuf) return manuf; - if (cbfs_boot_load_file("oem.bin", oem_bin_data, - sizeof(oem_bin_data) - 1, - CBFS_TYPE_RAW)) + if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) manuf = &oem_bin_data[0]; else manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 844496d..c64bc98 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -117,8 +117,7 @@ return NULL; snprintf(cbfs_name, sizeof(cbfs_name), "panel-%s", desc->name); - if (cbfs_boot_load_file(cbfs_name, buffer.raw, sizeof(buffer), - CBFS_TYPE_STRUCT)) + if (cbfs_load(cbfs_name, buffer.raw, sizeof(buffer))) desc->s = &buffer.s; else printk(BIOS_ERR, "Missing %s in CBFS.\n", cbfs_name); diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index b6277ea..8ce455d 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -36,8 +36,8 @@ uint32_t ramcode = ram_code(); if (ramcode >= ARRAY_SIZE(sdram_configs) || - cbfs_boot_load_file(sdram_configs[ramcode], &params, sizeof(params), - CBFS_TYPE_STRUCT) != sizeof(params)) + cbfs_load(sdram_configs[ramcode], &params, sizeof(params)) + != sizeof(params)) die("Cannot load SDRAM parameter file!"); return &params; diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 7d1c177..5fd56cf 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -81,8 +81,7 @@ int spd_index = get_gpios(gpio_vector); printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 9de1602..08d21f6 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -125,8 +125,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map(spd_bin, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 6d54e17..71cade7 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -167,9 +167,8 @@ if (oem_id == OEM_UNKNOWN) return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - oem_data_size = cbfs_boot_load_file("oem.bin", oem_bin_data, - sizeof(oem_bin_data), - CBFS_TYPE_RAW); + oem_data_size = cbfs_load("oem.bin", oem_bin_data, + sizeof(oem_bin_data)); while ((curr < oem_data_size) && ((oem_data_size - curr) >= sizeof(*oem_entry))) { diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index f74d77d..542d996 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -62,8 +62,7 @@ void *spd_file; size_t spd_fsize; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_fsize); + spd_file = cbfs_map("spd.bin", &spd_fsize); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c index 5b220e0..bd22fe9 100644 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -122,9 +122,7 @@ search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c index d6cd580..27e5c9f 100644 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -122,9 +122,7 @@ search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index c193d20..11e1d59 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -77,8 +77,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 9e9cf73..5ea13f4 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -76,8 +76,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 8adf4b2..c67ffef 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -79,8 +79,7 @@ uint32_t board_version = PEPPY_BOARD_VERSION_PROTO; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 651d8b1..cdc8f90 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -77,8 +77,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c index 29be074..9ef3174 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c @@ -55,8 +55,7 @@ { /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ size_t spd_file_len = 0; - void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + void *spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file || spd_file_len < sizeof(spd_raw_data)) die("SPD data for C1S0 not found."); diff --git a/src/mainboard/intel/harcuvar/spd/spd.c b/src/mainboard/intel/harcuvar/spd/spd.c index 61bf2e5..75a95c4 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.c +++ b/src/mainboard/intel/harcuvar/spd/spd.c @@ -30,8 +30,7 @@ spd_index = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index 2fe4596..bab5f53 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -82,8 +82,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index a0fc2ec..5222f99 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -84,8 +84,7 @@ spd_index, mainboard_spd_names[spd_index]); /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) die("SPD data not found."); diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 7da2c55..2db7fc6 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -44,8 +44,7 @@ { /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ size_t spd_file_len = 0; - void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + void *spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file || spd_file_len < sizeof(spd_raw_data)) die("SPD data for C1S0 not found."); diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index 859148a..a56d024 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -50,8 +50,7 @@ size_t spd_file_len; printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 0249c3b..add76b5 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -119,8 +119,7 @@ break; } - spd_data = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_data = cbfs_map("spd.bin", &spd_file_len); if (!spd_data) die("SPD data not found."); if (spd_file_len < (spd_index + 1) * 256) diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index 3d43181..6ef7c1c 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -86,7 +86,7 @@ struct device_tree *tree; /* load flat dt from cbfs */ - fdt_rom = cbfs_boot_map_with_leak("fallback/DTB", CBFS_TYPE_RAW, NULL); + fdt_rom = cbfs_map("fallback/DTB", NULL); if (fdt_rom == NULL) { printk(BIOS_ERR, "Unable to load fallback/DTB from CBFS\n"); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 8daa9aa..a0753aa 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -220,7 +220,7 @@ pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ - entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); + entry = cbfs_map("mrc.bin", NULL); if (entry) { int rv; rv = entry (pei_data); diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index 45db0e0..6eae9b0 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -49,8 +49,7 @@ memset((void *)mseg_base, 0, CONFIG_MSEG_SIZE); // clear the mseg - stm_image_size = cbfs_boot_load_file("stm.bin", mseg_base, - stm_buffer_size, CBFS_TYPE_RAW); + stm_image_size = cbfs_load("stm.bin", mseg_base, stm_buffer_size); printk(BIOS_DEBUG, "STM:loaded into mseg: 0x%p size: %u\n", mseg_base, stm_image_size); /* status is number of bytes loaded */ diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index e7b64b2..3d14e14 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -397,7 +397,7 @@ { size_t size; const char *filename = EC_HASH_FILENAME(select); - const uint8_t *file = cbfs_boot_map_with_leak(filename, CBFS_TYPE_RAW, &size); + const uint8_t *file = cbfs_map(filename, &size); if (file == NULL) return VB2_ERROR_UNKNOWN; diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index facd5f8..b671b55 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -150,9 +150,8 @@ GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo; pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( - "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM, NULL); + pVbiosImageInfo->ImagePtr = cbfs_map( + "pci"CONFIG_VGA_BIOS_ID".rom", NULL); printk(BIOS_DEBUG, "%s: IMGptr=%p\n", __func__, pVbiosImageInfo->ImagePtr); return pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING; diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 8abb328..18a7b3f 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -347,8 +347,7 @@ size_t size = 0; - void *ptr = cbfs_boot_map_with_leak("sff8104-linux.dtb", - CBFS_TYPE_RAW, &size); + void *ptr = cbfs_map("sff8104-linux.dtb", &size); if (ptr) memcpy(_sff8104, ptr, size); /* Point to devicetree in secure memory */ diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index c21a0c4..d6f26cd 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -142,7 +142,7 @@ } /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL) == NULL) { + if (cbfs_map("mrc.bin", NULL) == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; } diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index 2cd35ea..b5c8a78 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -126,7 +126,7 @@ printk(BIOS_DEBUG, "MMA: Entry %s\n", __func__); if (cbfs_locate_file_in_region(&metadata_fh, MMA_CBFS_REGION, - MMA_TEST_METADATA_FILENAME, &mma_type)) { + MMA_TEST_METADATA_FILENAME)) { printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", MMA_TEST_METADATA_FILENAME); return -1; @@ -167,7 +167,7 @@ test_filename, test_param_filename); if (cbfs_locate_file_in_region(&test_content_fh, MMA_CBFS_REGION, - test_filename, &efi_type)) { + test_filename)) { printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", test_filename); return -1; @@ -176,7 +176,7 @@ cbfs_file_data(&mma_cfg->test_content, &test_content_fh); if (cbfs_locate_file_in_region(&test_param_fh, MMA_CBFS_REGION, - test_param_filename, &mma_type)) { + test_param_filename)) { printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", test_param_filename); return -1; diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index c21a2a7..2d9ec23 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -106,8 +106,7 @@ const struct microcode *microcode_file; size_t microcode_len; - microcode_file = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, &microcode_len); + microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len); if ((microcode_file != NULL) && (microcode_len != 0)) { /* Update CPU Microcode patch base address/size */ diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 020da93..b275422 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -245,8 +245,7 @@ stopwatch_init(&sw); - size_t file_size = cbfs_boot_load_file(file_name, spm_bin, - sizeof(spm_bin), CBFS_TYPE_RAW); + size_t file_size = cbfs_load(file_name, spm_bin, sizeof(spm_bin)); if (file_size == 0) { printk(BIOS_ERR, "SPM binary %s not found\n", file_name); diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c index 857d3dc..2e1065b 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/mt8183/sspm.c @@ -26,10 +26,7 @@ void sspm_init(void) { const char *file_name = "sspm.bin"; - size_t fw_size = cbfs_boot_load_file(file_name, - sspm_bin, - sizeof(sspm_bin), - CBFS_TYPE_RAW); + size_t fw_size = cbfs_load(file_name, sspm_bin, sizeof(sspm_bin)); if (fw_size == 0) die("SSPM file :sspm.bin not found."); diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index 9d608fa..ceecdf2 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -36,8 +36,7 @@ void *blob_dest; size_t blob_size; - blob_mbn = cbfs_boot_map_with_leak(file_name, CBFS_TYPE_RAW, - &blob_size); + blob_mbn = cbfs_map(file_name, &blob_size); if (!blob_mbn) return NULL; diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index 2da868b..0d783eb 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -32,8 +32,7 @@ void *blob_dest; size_t blob_size; - blob_mbn = cbfs_boot_map_with_leak(file_name, CBFS_TYPE_RAW, - &blob_size); + blob_mbn = cbfs_map(file_name, &blob_size); if (!blob_mbn) return NULL; diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c index 9c05452..653a90f 100644 --- a/src/soc/qualcomm/sc7180/qclib.c +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -25,15 +25,15 @@ ssize_t ssize; /* Attempt to load PMICCFG Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", - _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic)); if (!size) return -1; qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); /* Attempt to load DCB Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", - _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + size = cbfs_load(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb)); if (!size) return -1; qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c index ae7251a..eb0fa20 100644 --- a/src/soc/qualcomm/sdm845/qclib.c +++ b/src/soc/qualcomm/sdm845/qclib.c @@ -24,15 +24,15 @@ ssize_t ssize; /* Attempt to load PMICCFG Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", - _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic)); if (!size) return -1; qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); /* Attempt to load DCB Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", - _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + size = cbfs_load(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb)); if (!size) return -1; qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index 4429c1f..70a6332 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -248,7 +248,7 @@ size_t size; printk(BIOS_DEBUG, "%s: Measure %s\n", __func__, name); - base = cbfs_boot_map_with_leak(name, type, &size); + base = cbfs_map(name, &size); if (base == NULL) { printk(BIOS_DEBUG, "%s: CBFS locate fail: %s\n", __func__, name); diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 9d99e02..69d8ade 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -46,7 +46,7 @@ sd = vb2_get_sd(ctx); - buffer = cbfs_boot_map_with_leak(RSA_PUBLICKEY_FILE_NAME, CBFS_TYPE_RAW, &size); + buffer = cbfs_map(RSA_PUBLICKEY_FILE_NAME, &size); if (!buffer || !size) { printk(BIOS_ERR, "ERROR: Public key not found!\n"); goto fail; @@ -84,7 +84,7 @@ pre->flags = VB2_FIRMWARE_PREAMBLE_DISALLOW_HWCRYPTO; /* Fill body_signature (vb2_structure). RSA2048 key is used */ - cbfs_boot_map_with_leak("oemmanifest.bin", CBFS_TYPE_RAW, &size); + cbfs_map("oemmanifest.bin", &size); if (size != ((CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + (2048/8))) { printk(BIOS_ERR, "ERROR: Incorrect manifest size!\n"); goto fail; @@ -195,7 +195,7 @@ void *start; size_t size; - start = cbfs_boot_map_with_leak(name, type & ~VERIFIED_BOOT_COPY_BLOCK, &size); + start = cbfs_map(name, &size); if (start && size) { /* Speed up processing by copying the file content to memory first */ if (!ENV_ROMSTAGE_OR_BEFORE && (type & VERIFIED_BOOT_COPY_BLOCK)) { diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 01de60c..d597d3e 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -29,8 +29,7 @@ const char *filename = get_wifi_sar_cbfs_filename(); if (filename == NULL) filename = WIFI_SAR_CBFS_FILENAME; - return cbfs_boot_load_file(filename, buf, - buffer_size, CBFS_TYPE_RAW); + return cbfs_load(filename, buf, buffer_size); } /* Retrieve the wifi SAR limits data from VPD and decode it diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index a4b8e54..e155404 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -482,7 +482,7 @@ return CB_SUCCESS; } - ptr = cbfs_boot_map_with_leak(hwi_filename, CBFS_TYPE_RAW, &filesize); + ptr = cbfs_map(hwi_filename, &filesize); if (!ptr) { printk(BIOS_ERR,"HWILIB: Missing file \"%s\" in cbfs.\n", hwi_filename); -- To view, visit https://review.coreboot.org/c/coreboot/+/39304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Gerrit-Change-Number: 39304 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

6 22

Change in coreboot[master]: mb/intel/adlrvp: Refactor lpddr4_mem_config structure
by Subrata Banik (Code Review) 07 Dec '20

07 Dec '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48077 ) Change subject: mb/intel/adlrvp: Refactor lpddr4_mem_config structure ...................................................................... mb/intel/adlrvp: Refactor lpddr4_mem_config structure List of changes: 1. Initialize dq_map array in a single line 2. Make dqs_map array also in a single line TEST=Able to build and boot ADLRVP LP4 SKU. Change-Id: I64f2b38492934c8ede301f4b252c8700060ed4ac Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/memory.c 1 file changed, 9 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/48077/1 diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index cab4ef9..c25b245 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -22,29 +22,19 @@ static const struct mb_cfg lpddr4_mem_config = { /* DQ byte map */ .dq_map = { - { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ - 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ - { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ - 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ - { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ - 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ - { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ - 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ - { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ - 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ - { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ - 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ - { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ - 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ - { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ - 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */ + { 0, 2, 3, 1, 6, 7, 5, 4, 10, 8, 11, 9, 14, 12, 13, 15 }, + { 12, 8, 14, 10, 11, 13, 15, 9, 5, 0, 7, 3, 6, 2, 1, 4 }, + { 3, 0, 2, 1, 6, 5, 4, 7, 12, 13, 14, 15, 10, 9, 8, 11 }, + { 2, 6, 7, 1, 3, 4, 0, 5, 9, 13, 8, 15, 14, 11, 12, 10 }, + { 3, 0, 1, 2, 7, 4, 6, 5, 10, 8, 11, 9, 14, 13, 12, 15 }, + { 10, 12, 14, 8, 9, 13, 15, 11, 3, 7, 6, 2, 0, 4, 5, 1 }, + { 12, 15, 14, 13, 9, 10, 11, 8, 7, 4, 6, 5, 0, 1, 3, 2 }, + { 0, 2, 4, 3, 1, 6, 7, 5, 13, 9, 10, 11, 8, 12, 14, 15 }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, - { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } }, .dq_pins_interleaved = false, -- To view, visit https://review.coreboot.org/c/coreboot/+/48077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64f2b38492934c8ede301f4b252c8700060ed4ac Gerrit-Change-Number: 48077 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020