coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/elkhartlake: Fix EHL mainboard build fail errors
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47804 ) Change subject: soc/intel/elkhartlake: Fix EHL mainboard build fail errors ...................................................................... soc/intel/elkhartlake: Fix EHL mainboard build fail errors When EHL initial mainboard patch is uploaded, there are some build errors caused by EHL soc codes. Here are the fixes: 1. include gpio_op.asl to resolve undefined variables in scs.asl 2. remove unused variables in fsp_params.c 3. rearrage sequences of #includes to fix build dependency of soc/gpio_defs.h in intelblocks/gpio.h 4. add the __weak to mainboard_memory_init_params function Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3 --- M src/soc/intel/elkhartlake/acpi/gpio.asl M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/include/soc/gpio.h M src/soc/intel/elkhartlake/romstage/fsp_params.c 4 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/47804/1 diff --git a/src/soc/intel/elkhartlake/acpi/gpio.asl b/src/soc/intel/elkhartlake/acpi/gpio.asl index ac0d1df..27cb503 100644 --- a/src/soc/intel/elkhartlake/acpi/gpio.asl +++ b/src/soc/intel/elkhartlake/acpi/gpio.asl @@ -3,6 +3,7 @@ #include <intelblocks/gpio.h> #include <soc/gpio_defs.h> #include <soc/intel/common/acpi/gpio.asl> +#include <soc/intel/common/block/acpi/acpi/gpio_op.asl> #include <soc/irq.h> #include <soc/pcr_ids.h> diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 3d740fb..83a3699 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -44,17 +44,13 @@ static void parse_devicetree(FSP_S_CONFIG *params) { - const struct soc_intel_elkhartlake_config *config = config_of_soc(); /* TODO: Update with UPD override as FSP matures */ } /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - unsigned int i; - struct device *dev; FSP_S_CONFIG *params = &supd->FspsConfig; - struct soc_intel_elkhartlake_config *config = config_of_soc(); /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params); diff --git a/src/soc/intel/elkhartlake/include/soc/gpio.h b/src/soc/intel/elkhartlake/include/soc/gpio.h index 6cca742..367df82 100644 --- a/src/soc/intel/elkhartlake/include/soc/gpio.h +++ b/src/soc/intel/elkhartlake/include/soc/gpio.h @@ -3,8 +3,8 @@ #ifndef _SOC_ELKHARTLAKE_GPIO_H_ #define _SOC_ELKHARTLAKE_GPIO_H_ -#include <intelblocks/gpio.h> #include <soc/gpio_defs.h> +#include <intelblocks/gpio.h> #define CROS_GPIO_NAME "INT34C8" #define CROS_GPIO_COMM0_NAME "INT34C8:00" diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index 3961dfc..0fa8451 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -25,7 +25,7 @@ mainboard_memory_init_params(mupd); } -void mainboard_memory_init_params(FSPM_UPD *mupd) +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) { /* TODO: Update later together with UPD updates */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/47804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3 Gerrit-Change-Number: 47804 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: cpu/x86/64bit/exit32.inc: Don't invalidate cache in CAR
by Patrick Rudolph (Code Review) 10 Dec '20

10 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48178 ) Change subject: cpu/x86/64bit/exit32.inc: Don't invalidate cache in CAR ...................................................................... cpu/x86/64bit/exit32.inc: Don't invalidate cache in CAR Change-Id: I4a4e988d38b548e1c88ffcc5f5ada2e91ff6ba91 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/exit32.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/48178/1 diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 6722cfd..d35eb13 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -24,8 +24,9 @@ drop_longmode: /* Ensure cache is clean. */ +#if defined(__RAMSTAGE__) wbinvd - +#endif /* Set 32-bit code segment and ss */ mov $CODE_SEG, %rcx /* SetCodeSelector32 will drop us to protected mode on return */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a4e988d38b548e1c88ffcc5f5ada2e91ff6ba91 Gerrit-Change-Number: 48178 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPM.
by Yidi Lin (Code Review) 10 Dec '20

10 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46392 ) Change subject: soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPM. ...................................................................... soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPM. Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/mcupm.h M src/soc/mediatek/mt8192/include/soc/memlayout.ld A src/soc/mediatek/mt8192/mcupm.c M src/soc/mediatek/mt8192/soc.c 6 files changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46392/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 9bb9cfd..59d105c 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c +ramstage-y += mcupm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c @@ -52,6 +53,11 @@ spm_firmware.bin-type := raw spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += mcupm.bin +mcupm.bin-file := $(MT8192_BLOB_DIR)/mcupm.bin +mcupm.bin-type := raw +mcupm.bin-compression := $(CBFS_COMPRESS_FLAG) + DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram $(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf $(DRAM_CBFS)-type := stage diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 9760c88..9864e5b 100755 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -5,6 +5,8 @@ enum { MCUSYS_BASE = 0x0C530000, + MCUPM_SRAM_BASE = 0x0C540000, + MCUPM_CFG_BASE = 0x0C560000, IO_PHYS = 0x10000000, }; diff --git a/src/soc/mediatek/mt8192/include/soc/mcupm.h b/src/soc/mediatek/mt8192/include/soc/mcupm.h new file mode 100644 index 0000000..dcb8c4a --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mcupm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_MCUPM_H +#define SOC_MEDIATEK_MT8192_MCUPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_mcupm_regs { + u32 sw_rstn; +}; +static struct mt8192_mcupm_regs *const mt8192_mcupm = (void *)MCUPM_CFG_BASE; +void mcupm_init(void); +#endif /* SOC_MEDIATEK_MT8192_MCUPM_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index df9d376..3bef5b1 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -37,7 +37,7 @@ DRAM_START(0x40000000) POSTRAM_CBFS_CACHE(0x40000000, 2M) - RAMSTAGE(0x40200000, 256K) + RAMSTAGE(0x40200000, 512K) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/mcupm.c b/src/soc/mediatek/mt8192/mcupm.c new file mode 100644 index 0000000..88efc85 --- /dev/null +++ b/src/soc/mediatek/mt8192/mcupm.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/barrier.h> +#include <cbfs.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/mcupm.h> +#include <string.h> + +#define BUF_SIZE (128 * KiB) +static uint8_t mcupm_bin[BUF_SIZE] __aligned(8); + +void mcupm_init(void) +{ + const char *file_name = "mcupm.bin"; + size_t fw_size = cbfs_boot_load_file(file_name, + mcupm_bin, + sizeof(mcupm_bin), + CBFS_TYPE_RAW); + + if (fw_size == 0) { + die("MCUPM file :mcupm.bin not found."); + } + + write32(&mt8192_mcupm->sw_rstn, 0x0); + write32((void *)(0x0C55FAA0), 0x0); + memcpy((void *)MCUPM_SRAM_BASE, mcupm_bin, fw_size); + /* Memory barrier to ensure that all fw code is loaded + before we release the reset pin. */ + mb(); + write32(&mt8192_mcupm->sw_rstn, 0x1); +} diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 6978406..6deb833 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -4,6 +4,7 @@ #include <soc/emi.h> #include <soc/mmu_operations.h> #include <symbols.h> +#include <soc/mcupm.h> static void soc_read_resources(struct device *dev) { @@ -13,6 +14,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + mcupm_init(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277 Gerrit-Change-Number: 46392 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 28

Change in coreboot[master]: mediatek/mt8192: add spmfw loader
by Yidi Lin (Code Review) 10 Dec '20

10 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46389 ) Change subject: mediatek/mt8192: add spmfw loader ...................................................................... mediatek/mt8192: add spmfw loader To support mt8192 power saving during suspend to RAM, this patch loads spmfw to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal. BUG=b:159079649 TEST=Asurada boots up to shell Signed-off-by: Roger Lu <roger.lu(a)mediatek.com> Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371 --- M src/mainboard/google/asurada/mainboard.c M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/spm.h A src/soc/mediatek/mt8192/spm.c 5 files changed, 1,551 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 76a71c7..7b3ef22 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -6,6 +6,7 @@ #include <device/mmio.h> #include <lib.h> #include <soc/gpio_common.h> +#include <soc/spm.h> #include <soc/usb.h> #include "gpio.h" @@ -77,6 +78,9 @@ setup_usb_host(); register_reset_to_bl31(); + + if (spm_init()) + printk(BIOS_ERR, "spm init fail, system suspend may stuck\n"); } static void mainboard_enable(struct device *dev) diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index cfd148c..0bba19e 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -23,7 +23,7 @@ static void mtcmos_power_on(const struct power_domain_data *pd) { - write32(&mtk_spm->poweron_config_set, + write32(&mtk_spm->poweron_config_en, (SPM_PROJECT_CODE << 16) | (1U << 0)); setbits32(pd->pwr_con, PWR_ON); diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 891d38a..d417ae2 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -33,6 +33,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += spm.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c @@ -42,6 +43,11 @@ MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 +cbfs-files-y += spm_firmware.bin +spm_firmware.bin-file := $(MT8192_BLOB_DIR)/spm_firmware.bin +spm_firmware.bin-type := raw +spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG) + DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram $(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf $(DRAM_CBFS)-type := stage diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index 73ef798..53b86e5 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -4,10 +4,309 @@ #define SOC_MEDIATEK_MT8192_SPM_H #include <soc/addressmap.h> +#include <stdint.h> #include <types.h> /* SPM READ/WRITE CFG */ -#define SPM_PROJECT_CODE 0xb16 +#define SPM_PROJECT_CODE (0xb16) +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ + +/* SPM_CLK_CON (0x10006000+0x00C) */ +#define REG_SYSCLK1_SRC_MD2_SRCCLKENA (1U << 28) /* 1b */ + +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_CK_EN_LSB (1U << 2) /* 1b */ +#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ + +/* PCM_CON1 (0x10006000+0x01C) */ +#define RG_IM_SLAVE_LSB (1U << 0) /* 1b */ +#define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */ +#define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */ +#define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */ +#define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */ +#define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ +#define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ +#define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ + +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */ +#define SPM_WAKEUP_EVENT_MASK_BIT0 (1U << 0) /* 1b */ +#define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B (1U << 24) /* 1b */ + +/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */ +#define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0) /* 1b */ + +/* SPM_DVFS_MISC (0x10006000+0x4AC) */ +#define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */ +#define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */ + +/* SPM_SW_FLAG_0 (0x10006000+0x600) */ +#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3) /* 1b */ +#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4) /* 1b */ +#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) /* 1b */ + +/* SYS_TIMER_CON (0x10006000+0x98C) */ +#define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */ + +/* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */ +#define MD32PCM_CFGREG_SW_RSTN_RESET (1U << 0) /* 1b */ + +/************************************** + * Config and Parameter + **************************************/ +#define POWER_ON_VAL1_DEF (0x80015860) +#define SPM_WAKEUP_EVENT_MASK_DEF (0xefffffff) +#define SPM_ACK_CHK_3_SEL_HW_S1 (0x00350098) +#define SPM_ACK_CHK_3_HW_S1_CNT (0x1) +#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG (0x800) +#define SPM_ACK_CHK_3_CON_EN (0x110) +#define SPM_ACK_CHK_3_CON_CLR_ALL (0x2) +#define SPM_BUS_PROTECT_MASK_B_DEF (0xffffffff) +#define SPM_BUS_PROTECT2_MASK_B_DEF (0xffffffff) +#define MD32PCM_DMA0_CON_VAL (0x0003820e) +#define MD32PCM_DMA0_START_VAL (0x00008000) +#define MD32PCM_CFGREG_SW_RSTN_RUN (0x1) +#define SPM_DVFS_LEVEL_DEF (0x00000001) +#define SPM_DVS_DFS_LEVEL_DEF (0x00010001) +#define SPM_RESOURCE_ACK_CON0_DEF (0x00000000) +#define SPM_RESOURCE_ACK_CON1_DEF (0x00000000) +#define SPM_RESOURCE_ACK_CON2_DEF (0xcccc4e4e) +#define SPM_RESOURCE_ACK_CON3_DEF (0x00000000) +#define ARMPLL_CLK_SEL_DEF (0x3ff) +#define DDR_EN_DBC_CON0_DEF (0x154) +#define SPM_SYSCLK_SETTLE (0x60fe) +#define SPM_INIT_DONE_US (20) +#define PCM_WDT_TIMEOUT (30 * 32768) +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +/************************************** + * Define and Declare + **************************************/ +/* SPM_IRQ_MASK */ +#define ISRM_TWAM (1U << 2) +#define ISRM_PCM_RETURN (1U << 3) +#define ISRM_RET_IRQ_AUX (0x3fe00) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM (1U << 2) +#define ISRS_PCM_RETURN (1U << 3) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +/* SPM_SWINT */ +#define PCM_SW_INT_ALL (0x3ff) + +struct pwr_ctrl { + u32 pcm_flags; + u32 pcm_flags_cust; + u32 pcm_flags_cust_set; + u32 pcm_flags_cust_clr; + u32 pcm_flags1; + u32 pcm_flags1_cust; + u32 pcm_flags1_cust_set; + u32 pcm_flags1_cust_clr; + u32 timer_val; + u32 timer_val_cust; + u32 timer_val_ramp_en; + u32 timer_val_ramp_en_sec; + u32 wake_src; + u32 wake_src_cust; + u32 wakelock_timer_val; + u8 wdt_disable; + + /* Auto-gen Start */ + + /* SPM_CLK_CON */ + u8 reg_srcclken0_ctl; + u8 reg_srcclken1_ctl; + u8 reg_spm_lock_infra_dcm; + u8 reg_srcclken_mask; + u8 reg_md1_c32rm_en; + u8 reg_md2_c32rm_en; + u8 reg_clksq0_sel_ctrl; + u8 reg_clksq1_sel_ctrl; + u8 reg_srcclken0_en; + u8 reg_srcclken1_en; + u32 reg_sysclk0_src_mask_b; + u32 reg_sysclk1_src_mask_b; + + /* SPM_AP_STANDBY_CON */ + u8 reg_wfi_op; + u8 reg_wfi_type; + u8 reg_mp0_cputop_idle_mask; + u8 reg_mp1_cputop_idle_mask; + u8 reg_mcusys_idle_mask; + u8 reg_md_apsrc_1_sel; + u8 reg_md_apsrc_0_sel; + u8 reg_conn_apsrc_sel; + + /* SPM_SRC6_MASK */ + u8 reg_dpmaif_srcclkena_mask_b; + u8 reg_dpmaif_infra_req_mask_b; + u8 reg_dpmaif_apsrc_req_mask_b; + u8 reg_dpmaif_vrf18_req_mask_b; + u8 reg_dpmaif_ddr_en_mask_b; + + /* SPM_SRC_REQ */ + u8 reg_spm_apsrc_req; + u8 reg_spm_f26m_req; + u8 reg_spm_infra_req; + u8 reg_spm_vrf18_req; + u8 reg_spm_ddr_en_req; + u8 reg_spm_dvfs_req; + u8 reg_spm_sw_mailbox_req; + u8 reg_spm_sspm_mailbox_req; + u8 reg_spm_adsp_mailbox_req; + u8 reg_spm_scp_mailbox_req; + + /* SPM_SRC_MASK */ + u8 reg_md_srcclkena_0_mask_b; + u8 reg_md_srcclkena2infra_req_0_mask_b; + u8 reg_md_apsrc2infra_req_0_mask_b; + u8 reg_md_apsrc_req_0_mask_b; + u8 reg_md_vrf18_req_0_mask_b; + u8 reg_md_ddr_en_0_mask_b; + u8 reg_md_srcclkena_1_mask_b; + u8 reg_md_srcclkena2infra_req_1_mask_b; + u8 reg_md_apsrc2infra_req_1_mask_b; + u8 reg_md_apsrc_req_1_mask_b; + u8 reg_md_vrf18_req_1_mask_b; + u8 reg_md_ddr_en_1_mask_b; + u8 reg_conn_srcclkena_mask_b; + u8 reg_conn_srcclkenb_mask_b; + u8 reg_conn_infra_req_mask_b; + u8 reg_conn_apsrc_req_mask_b; + u8 reg_conn_vrf18_req_mask_b; + u8 reg_conn_ddr_en_mask_b; + u8 reg_conn_vfe28_mask_b; + u8 reg_srcclkeni0_srcclkena_mask_b; + u8 reg_srcclkeni0_infra_req_mask_b; + u8 reg_srcclkeni1_srcclkena_mask_b; + u8 reg_srcclkeni1_infra_req_mask_b; + u8 reg_srcclkeni2_srcclkena_mask_b; + u8 reg_srcclkeni2_infra_req_mask_b; + u8 reg_infrasys_apsrc_req_mask_b; + u8 reg_infrasys_ddr_en_mask_b; + u8 reg_md32_srcclkena_mask_b; + u8 reg_md32_infra_req_mask_b; + u8 reg_md32_apsrc_req_mask_b; + u8 reg_md32_vrf18_req_mask_b; + u8 reg_md32_ddr_en_mask_b; + + /* SPM_SRC2_MASK */ + u8 reg_scp_srcclkena_mask_b; + u8 reg_scp_infra_req_mask_b; + u8 reg_scp_apsrc_req_mask_b; + u8 reg_scp_vrf18_req_mask_b; + u8 reg_scp_ddr_en_mask_b; + u8 reg_audio_dsp_srcclkena_mask_b; + u8 reg_audio_dsp_infra_req_mask_b; + u8 reg_audio_dsp_apsrc_req_mask_b; + u8 reg_audio_dsp_vrf18_req_mask_b; + u8 reg_audio_dsp_ddr_en_mask_b; + u8 reg_ufs_srcclkena_mask_b; + u8 reg_ufs_infra_req_mask_b; + u8 reg_ufs_apsrc_req_mask_b; + u8 reg_ufs_vrf18_req_mask_b; + u8 reg_ufs_ddr_en_mask_b; + u8 reg_disp0_apsrc_req_mask_b; + u8 reg_disp0_ddr_en_mask_b; + u8 reg_disp1_apsrc_req_mask_b; + u8 reg_disp1_ddr_en_mask_b; + u8 reg_gce_infra_req_mask_b; + u8 reg_gce_apsrc_req_mask_b; + u8 reg_gce_vrf18_req_mask_b; + u8 reg_gce_ddr_en_mask_b; + u8 reg_apu_srcclkena_mask_b; + u8 reg_apu_infra_req_mask_b; + u8 reg_apu_apsrc_req_mask_b; + u8 reg_apu_vrf18_req_mask_b; + u8 reg_apu_ddr_en_mask_b; + u8 reg_cg_check_srcclkena_mask_b; + u8 reg_cg_check_apsrc_req_mask_b; + u8 reg_cg_check_vrf18_req_mask_b; + u8 reg_cg_check_ddr_en_mask_b; + + /* SPM_SRC3_MASK */ + u8 reg_dvfsrc_event_trigger_mask_b; + u8 reg_sw2spm_int0_mask_b; + u8 reg_sw2spm_int1_mask_b; + u8 reg_sw2spm_int2_mask_b; + u8 reg_sw2spm_int3_mask_b; + u8 reg_sc_adsp2spm_wakeup_mask_b; + u8 reg_sc_sspm2spm_wakeup_mask_b; + u8 reg_sc_scp2spm_wakeup_mask_b; + u8 reg_csyspwrreq_mask; + u8 reg_spm_srcclkena_reserved_mask_b; + u8 reg_spm_infra_req_reserved_mask_b; + u8 reg_spm_apsrc_req_reserved_mask_b; + u8 reg_spm_vrf18_req_reserved_mask_b; + u8 reg_spm_ddr_en_reserved_mask_b; + u8 reg_mcupm_srcclkena_mask_b; + u8 reg_mcupm_infra_req_mask_b; + u8 reg_mcupm_apsrc_req_mask_b; + u8 reg_mcupm_vrf18_req_mask_b; + u8 reg_mcupm_ddr_en_mask_b; + u8 reg_msdc0_srcclkena_mask_b; + u8 reg_msdc0_infra_req_mask_b; + u8 reg_msdc0_apsrc_req_mask_b; + u8 reg_msdc0_vrf18_req_mask_b; + u8 reg_msdc0_ddr_en_mask_b; + u8 reg_msdc1_srcclkena_mask_b; + u8 reg_msdc1_infra_req_mask_b; + u8 reg_msdc1_apsrc_req_mask_b; + u8 reg_msdc1_vrf18_req_mask_b; + u8 reg_msdc1_ddr_en_mask_b; + + /* SPM_SRC4_MASK */ + u32 ccif_event_mask_b; + u8 reg_bak_psri_srcclkena_mask_b; + u8 reg_bak_psri_infra_req_mask_b; + u8 reg_bak_psri_apsrc_req_mask_b; + u8 reg_bak_psri_vrf18_req_mask_b; + u8 reg_bak_psri_ddr_en_mask_b; + u8 reg_dramc0_md32_infra_req_mask_b; + u8 reg_dramc0_md32_vrf18_req_mask_b; + u8 reg_dramc1_md32_infra_req_mask_b; + u8 reg_dramc1_md32_vrf18_req_mask_b; + u8 reg_conn_srcclkenb2pwrap_mask_b; + u8 reg_dramc0_md32_wakeup_mask; + u8 reg_dramc1_md32_wakeup_mask; + + /* SPM_SRC5_MASK */ + u32 reg_mcusys_merge_apsrc_req_mask_b; + u32 reg_mcusys_merge_ddr_en_mask_b; + u8 reg_msdc2_srcclkena_mask_b; + u8 reg_msdc2_infra_req_mask_b; + u8 reg_msdc2_apsrc_req_mask_b; + u8 reg_msdc2_vrf18_req_mask_b; + u8 reg_msdc2_ddr_en_mask_b; + u8 reg_pcie_srcclkena_mask_b; + u8 reg_pcie_infra_req_mask_b; + u8 reg_pcie_apsrc_req_mask_b; + u8 reg_pcie_vrf18_req_mask_b; + u8 reg_pcie_ddr_en_mask_b; + + /* SPM_WAKEUP_EVENT_MASK */ + u32 reg_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + u32 reg_ext_wakeup_event_mask; + + /* Auto-gen End */ +}; enum { DISP_PWR_STA_MASK = 0x1 << 20, @@ -19,7 +318,7 @@ }; struct mtk_spm_regs { - u32 poweron_config_set; + u32 poweron_config_en; u32 spm_power_on_val0; u32 spm_power_on_val1; u32 spm_clk_con; @@ -34,14 +333,14 @@ u32 pcm_timer_val; u32 pcm_wdt_val; u32 spm_src6_mask; - u32 reserved1[1]; - u32 spm_sw_rst_con; /* 0x0040 */ + u32 reserved0; + u32 spm_sw_rst_con; u32 spm_sw_rst_con_set; u32 spm_sw_rst_con_clr; u32 vs1_psr_mask_b; u32 vs2_psr_mask_b; - u32 reserved2[12]; - u32 md32_clk_con; /* 0x0084 */ + u32 reserved1[12]; + u32 md32_clk_con; u32 spm_sram_rsv_con; u32 spm_swint; u32 spm_swint_set; @@ -77,27 +376,27 @@ u32 pcm_reg6_data; u32 pcm_reg7_data; u32 pcm_reg13_data; - u32 src_req_sta_0; - u32 src_req_sta_1; - u32 src_req_sta_2; + u32 src_req_sta0; + u32 src_req_sta1; + u32 src_req_sta2; u32 pcm_timer_out; u32 pcm_wdt_out; u32 spm_irq_sta; - u32 src_req_sta_4; + u32 src_req_sta4; u32 md32pcm_wakeup_sta; u32 md32pcm_event_sta; u32 spm_wakeup_sta; u32 spm_wakeup_ext_sta; u32 spm_wakeup_misc; u32 mm_dvfs_halt; - u32 reserved3[2]; - u32 bus_protect_rdy; /* 0x0150 */ + u32 reserved2[2]; + u32 bus_protect_rdy; u32 bus_protect1_rdy; u32 bus_protect2_rdy; u32 bus_protect3_rdy; u32 subsys_idle_sta; u32 pcm_sta; - u32 src_req_sta_3; + u32 src_req_sta3; u32 pwr_status; u32 pwr_status_2nd; u32 cpu_pwr_status; @@ -109,15 +408,15 @@ u32 spm_ddren_event_count_sta; u32 md32pcm_sta; u32 md32pcm_pc; - u32 reserved4[3]; - u32 dvfsrc_event_sta; /* 0x01a4 */ + u32 reserved3[3]; + u32 dvfsrc_event_sta; u32 bus_protect4_rdy; u32 bus_protect5_rdy; u32 bus_protect6_rdy; u32 bus_protect7_rdy; u32 bus_protect8_rdy; - u32 reserved5[5]; - u32 spm_twam_last_sta0; /* 0x01d0 */ + u32 reserved4[5]; + u32 spm_twam_last_sta0; u32 spm_twam_last_sta1; u32 spm_twam_last_sta2; u32 spm_twam_last_sta3; @@ -139,8 +438,8 @@ u32 spm_cpu5_pwr_con; u32 spm_cpu6_pwr_con; u32 spm_cpu7_pwr_con; - u32 reserved6[1]; - u32 armpll_clk_con; /* 0x022c */ + u32 reserved5; + u32 armpll_clk_con; u32 mcusys_idle_sta; u32 gic_wakeup_sta; u32 cpu_spare_con; @@ -150,8 +449,8 @@ u32 ext_int_wakeup_req; u32 ext_int_wakeup_req_set; u32 ext_int_wakeup_req_clr; - u32 reserved7[3]; - u32 mp0_cpu0_irq_mask; /* 0x0260 */ + u32 reserved6[3]; + u32 mp0_cpu0_irq_mask; u32 mp0_cpu1_irq_mask; u32 mp0_cpu2_irq_mask; u32 mp0_cpu3_irq_mask; @@ -169,8 +468,8 @@ u32 mp0_cpu7_wfi_en; u32 root_cputop_addr; u32 root_core_addr; - u32 reserved8[10]; - u32 spm2sw_mailbox_0; /* 0x02d0 */ + u32 reserved7[10]; + u32 spm2sw_mailbox_0; u32 spm2sw_mailbox_1; u32 spm2sw_mailbox_2; u32 spm2sw_mailbox_3; @@ -227,22 +526,147 @@ u32 debugtop_sram_con; u32 dp_tx_pwr_con; u32 dpmaif_sram_con; - u32 dpy_shu2_sram_con; + u32 dpy_shu2_con; u32 dramc_mcu2_sram_con; u32 dramc_mcu_sram_con; u32 mcupm_pwr_con; u32 dpy2_pwr_con; u32 peri_pwr_con; + u32 reserved8[13]; + u32 spm_mem_ck_sel; + u32 spm_bus_protect_mask_b; + u32 spm_bus_protect1_mask_b; + u32 spm_bus_protect2_mask_b; + u32 spm_bus_protect3_mask_b; + u32 spm_bus_protect4_mask_b; + u32 spm_emi_bw_mode; + u32 ap2md_peer_wakeup; + u32 ulposc_con; + u32 spm2mm_con; + u32 spm_bus_protect5_mask_b; + u32 spm2mcupm_con; + u32 ap_mdsrc_req; + u32 spm2emi_enter_ulpm; + u32 spm2md_dvfs_con; + u32 md2spm_dvfs_con; + u32 spm_bus_protect6_mask_b; + u32 spm_bus_protect7_mask_b; + u32 spm_bus_protect8_mask_b; + u32 spm_pll_con; + u32 cpu_dvfs_req; + u32 spm_dram_mcu_sw_con0; + u32 spm_dram_mcu_sw_con1; + u32 spm_dram_mcu_sw_con2; + u32 spm_dram_mcu_sw_con3; + u32 spm_dram_mcu_sw_con4; + u32 spm_dram_mcu_sta_0; + u32 spm_dram_mcu_sta_1; + u32 spm_dram_mcu_sta_2; + u32 spm_dram_mcu_sw_sel_0; + u32 relay_dvfs_level; + u32 reserved9; + u32 dramc_dpy_clk_sw_con_0; + u32 dramc_dpy_clk_sw_con_1; + u32 dramc_dpy_clk_sw_con_2; + u32 dramc_dpy_clk_sw_con_3; + u32 dramc_dpy_clk_sw_sel_0; + u32 dramc_dpy_clk_sw_sel_1; + u32 dramc_dpy_clk_sw_sel_2; + u32 dramc_dpy_clk_sw_sel_3; + u32 dramc_dpy_clk_spm_con; + u32 spm_dvfs_level; + u32 spm_cirq_con; + u32 spm_dvfs_misc; + u32 spm_vs1_vs2_rc_con; + u32 rg_module_sw_cg_0_mask_req_0; + u32 rg_module_sw_cg_0_mask_req_1; + u32 rg_module_sw_cg_0_mask_req_2; + u32 rg_module_sw_cg_1_mask_req_0; + u32 rg_module_sw_cg_1_mask_req_1; + u32 rg_module_sw_cg_1_mask_req_2; + u32 rg_module_sw_cg_2_mask_req_0; + u32 rg_module_sw_cg_2_mask_req_1; + u32 rg_module_sw_cg_2_mask_req_2; + u32 rg_module_sw_cg_3_mask_req_0; + u32 rg_module_sw_cg_3_mask_req_1; + u32 rg_module_sw_cg_3_mask_req_2; + u32 pwr_status_mask_req_0; + u32 pwr_status_mask_req_1; + u32 pwr_status_mask_req_2; + u32 spm_cg_check_con; + u32 spm_src_rdy_sta; + u32 spm_dvs_dfs_level; + u32 spm_force_dvfs; + u32 reserved10[64]; + u32 spm_sw_flag_0; + u32 spm_sw_debug_0; + u32 spm_sw_flag_1; + u32 reserved11[8]; + u32 spm_sw_rsv_7; + u32 spm_sw_rsv_8; + u32 reserved12[203]; + u32 spm_ack_chk_con_3; + u32 spm_ack_chk_pc_3; + u32 spm_ack_chk_sel_3; + u32 spm_ack_chk_timer_3; + u32 reserved13[7]; + u32 sys_timer_con; + u32 reserved14[28]; + u32 md32pcm_cfgreg_sw_rstn; + u32 reserved15[127]; + u32 md32pcm_dma0_src; + u32 md32pcm_dma0_dst; + u32 md32pcm_dma0_wppt; + u32 md32pcm_dma0_wpto; + u32 md32pcm_dma0_count; + u32 md32pcm_dma0_con; + u32 md32pcm_dma0_start; + u32 reserved16[2]; + u32 md32pcm_dma0_rlct; }; - -check_member(mtk_spm_regs, md32_clk_con, 0x0084); -check_member(mtk_spm_regs, bus_protect_rdy, 0x0150); -check_member(mtk_spm_regs, dvfsrc_event_sta, 0x01a4); -check_member(mtk_spm_regs, spm_twam_last_sta0, 0x01d0); -check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x0260); +check_member(mtk_spm_regs, poweron_config_en, 0x0); +check_member(mtk_spm_regs, vs2_psr_mask_b, 0x50); +check_member(mtk_spm_regs, md32_clk_con, 0x84); +check_member(mtk_spm_regs, mm_dvfs_halt, 0x144); +check_member(mtk_spm_regs, bus_protect_rdy, 0x150); +check_member(mtk_spm_regs, md32pcm_pc, 0x194); +check_member(mtk_spm_regs, dvfsrc_event_sta, 0x1a4); +check_member(mtk_spm_regs, bus_protect8_rdy, 0x1b8); +check_member(mtk_spm_regs, spm_twam_last_sta0, 0x1d0); +check_member(mtk_spm_regs, ext_int_wakeup_req_clr, 0x250); +check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x260); +check_member(mtk_spm_regs, root_core_addr, 0x2a4); check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x02d0); -check_member(mtk_spm_regs, peri_pwr_con, 0x03c8); +check_member(mtk_spm_regs, peri_pwr_con, 0x3c8); +check_member(mtk_spm_regs, spm_mem_ck_sel, 0x400); +check_member(mtk_spm_regs, spm_force_dvfs, 0x4fc); +check_member(mtk_spm_regs, spm_sw_flag_0, 0x600); +check_member(mtk_spm_regs, spm_sw_flag_1, 0x608); +check_member(mtk_spm_regs, spm_sw_rsv_7, 0x62c); +check_member(mtk_spm_regs, spm_sw_rsv_8, 0x630); +check_member(mtk_spm_regs, spm_ack_chk_con_3, 0x960); +check_member(mtk_spm_regs, spm_ack_chk_timer_3, 0x96c); +check_member(mtk_spm_regs, sys_timer_con, 0x98c); +check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xa00); +check_member(mtk_spm_regs, md32pcm_dma0_src, 0xc00); +check_member(mtk_spm_regs, md32pcm_dma0_dst, 0xc04); +check_member(mtk_spm_regs, md32pcm_dma0_wppt, 0xc08); +check_member(mtk_spm_regs, md32pcm_dma0_wpto, 0xc0c); +check_member(mtk_spm_regs, md32pcm_dma0_count, 0xc10); +check_member(mtk_spm_regs, md32pcm_dma0_con, 0xc14); +check_member(mtk_spm_regs, md32pcm_dma0_start, 0xc18); +check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24); static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; +struct spm_desc { + const char *version; + u32 pmem_words; + u32 total_words; + u32 pmem_start; + u32 dmem_start; +}; + +int spm_init(void); + #endif /* SOC_MEDIATEK_MT8192_SPM_H */ diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c new file mode 100644 index 0000000..578a637 --- /dev/null +++ b/src/soc/mediatek/mt8192/spm.c @@ -0,0 +1,1085 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/spm.h> +#include <timer.h> + +static const u32 spm_firmware_binary[] = { + 0x3200001e, 0x6a00001e, 0x6e00001e, 0x6800001e, 0x6200001e, 0x6000001e, + 0x5e00001e, 0x5c00001e, 0x6000001e, 0x5800001e, 0x5600001e, 0x5400001e, + 0x5200001e, 0x5000001e, 0x4e00001e, 0x4c00001e, 0xd402001e, 0xee01001e, + 0x3a03001e, 0x0002001e, 0x3609001e, 0xfa01001e, 0xf601001e, 0xf201001e, + 0xee01001e, 0x000f0f98, 0x300d0e00, 0x000fee00, 0x380d0100, 0x000f1160, + 0x380d0200, 0x001c22d8, 0x01041218, 0x1c0423e1, 0x000c3262, 0x801c3303, + 0xf0064014, 0x00090104, 0x831d2201, 0x801c40f8, 0xd0066010, 0x00090101, + 0x831d3301, 0x150460f8, 0x000d0140, 0x18041101, 0x03931020, 0x001f0493, + 0x1393b912, 0x0400001f, 0x0000001e, 0xc0051198, 0x3fa02000, 0x00008005, + 0x0000a005, 0x0000a005, 0x0000a005, 0xe1a70292, 0x0300f2a7, 0x82ac018c, + 0x84ad03ad, 0x86ae05ae, 0x02ace2a5, 0x018b0300, 0x000802a8, 0x02ac2201, + 0xf2a5e1a5, 0xa005ee97, 0x00000000, 0x01200000, 0x31060013, 0x0621500f, + 0x3f200040, 0x010d0900, 0x07a8a80f, 0xa80d6188, 0x250f77a8, 0x250d0625, + 0x87b46625, 0x2fa086b4, 0x06ac87b4, 0x7f0cbc13, 0x0621500f, 0x3f200040, + 0x07a8a80f, 0x010d0900, 0x8a0d6188, 0x8a0f778a, 0x250f088a, 0xa80d0625, + 0x87b488a8, 0x57520200, 0x2fa086b4, 0x07ac88b4, 0x01000200, 0x31060013, + 0x0621500f, 0x3f200040, 0x0710200f, 0x01100900, 0x720d6188, 0xf3017744, + 0xf70696c5, 0xf89f7190, 0x6150f006, 0x06ff080f, 0x66ffbb0d, 0x8150f006, + 0xc7b3f501, 0x81ecfc06, 0xf80ff001, 0xf10606b5, 0x2fa07150, 0x8110f006, + 0x008008ac, 0x01000200, 0x13060011, 0x0721500f, 0x3f200040, 0x01100900, + 0x0810200f, 0x1e0d7188, 0xfe0f8804, 0x3c0d07ff, 0xf0017758, 0xf706a200, + 0x000f8190, 0xf006063c, 0x380d7150, 0xf00f663c, 0xf006073c, 0x180d2150, + 0xfc06773c, 0xf00121ec, 0x06b51800, 0x7150f106, 0xf0062fa0, 0x08ac8110, + 0x81890300, 0xc8890300, 0x0f0f07a8, 0xff0d01ff, 0xf00f16ff, 0x718a0100, + 0x0700300f, 0x774c680d, 0x61a871ac, 0x71280b45, 0x618b2fa0, 0x008061b6, + 0x01800000, 0x08002fa0, 0x00070600, 0x00806165, 0x01800000, 0x800cc0f3, + 0x11bb1100, 0x01800000, 0x06000800, 0x0700300f, 0x778c640d, 0x61640007, + 0x000c61a8, 0x9f1c11f0, 0x3fa030fa, 0x00803fa0, 0xa0c921a8, 0x02202fa0, + 0x21ac1144, 0x80c921a8, 0x31a821ac, 0x31b408c9, 0x2fa031a8, 0x31b680c9, + 0x31681e04, 0x0600300f, 0x668c6908, 0x2fa008c9, 0x50ac51ac, 0x08c921a8, + 0x21a821b4, 0x21b480c9, 0x20c921a8, 0x21a821b4, 0x21b490c9, 0x2fa021a8, + 0x21b698c9, 0x0f0d21a8, 0x21b41100, 0x08c921a8, 0x21a821b4, 0x21b420c9, + 0x80c921a8, 0x21a821b4, 0x21b490c9, 0x2fa021a8, 0x21b698c9, 0x81860300, + 0x000c01a8, 0x31bc1104, 0x3f200040, 0x0100300f, 0x1120640d, 0x9dc906a8, + 0x02202fa0, 0x06b66633, 0x28c921a8, 0x21a821b4, 0x21b4b0c9, 0x2fa021a8, + 0x21b6c8c9, 0x0100300f, 0x11346008, 0x0600f000, 0x07160b0f, 0x7708000d, + 0x6110f006, 0x8734fb4f, 0x71ecff06, 0x6110f006, 0x87b42fa0, 0x008007ac, + 0x0100300f, 0x11346008, 0x0600f000, 0x07160b0f, 0x7708000d, 0x6110f006, + 0x8734fb4f, 0x71ecff06, 0x6110f006, 0x87b42fa0, 0x008007ac, 0x0100300f, + 0x1150680d, 0x0700100f, 0x87c908a8, 0x00000fc9, 0xf1060210, 0x040081d0, + 0x87b50801, 0x86890300, 0x21d4f206, 0x56a808ac, 0x6600100c, 0x0700300f, + 0x06a846bc, 0x06ac1dc9, 0x01004000, 0x0600300f, 0x66b0600d, 0x12650007, + 0x78be58a8, 0x00008005, 0x831c58a8, 0x00a000fb, 0x12640007, 0x0100300f, + 0x1134660d, 0x890406a8, 0x831c66fc, 0x2fa0c0fa, 0x71b06008, 0x008000ac, + 0xe1a70292, 0xf6270b4c, 0x01140000, 0x40f328f2, 0xe1a5f6a5, 0xa005ee97, + 0x00800000, 0x0000a005, 0x0000a005, 0x0000a005, 0x0000a005, 0x0000a005, + 0x0100300f, 0x0300100f, 0x18086a08, 0x37003f0d, 0x101ac014, 0x06001000, + 0x00a08049, 0x71ac3044, 0x28584006, 0x4006e2b4, 0xe2b4285c, 0x06100000, + 0x31803f08, 0x87b435f3, 0x87b475f3, 0x87b4b5f3, 0x87b4f5f3, 0x76440007, + 0x000787b4, 0x87b47645, 0x76460007, 0x000787b4, 0x87b47647, 0x76480007, + 0x000787b4, 0x87b47649, 0x764a0007, 0x2fa087b4, 0x66510007, 0x008006ac, + 0x0000a4b9, 0x31a80114, 0x31c01120, 0x31a831ac, 0x11bd8904, 0x119c8904, + 0x312c0040, 0x890431a8, 0x831c11fe, 0x31a820fa, 0x11bc8904, 0x89042fa0, + 0x31ac119d, 0x90f268f3, 0x831c68f3, 0x3fa0c0fe, 0x01100000, 0x0697010f, + 0x01600007, 0x07ff010f, 0x68721b4c, 0x00072fa0, 0x28f27166, 0x300f0192, + 0x6b0d0800, 0x424c8800, 0xfd0fffa7, 0x74a801ff, 0x11ebff0d, 0x0499418a, + 0x1810f206, 0x01540900, 0x0400f5b4, 0xf4b40500, 0x0416000f, 0x1200f1b4, + 0xf5b401a8, 0xf1b4f4b4, 0x03ff1f0f, 0x31f8ff0d, 0xff06f0b4, 0xf80608d8, + 0x4b061800, 0x0300180c, 0x03004388, 0x03008287, 0xf94f078a, 0x030021ac, + 0x10ac0688, 0x01140000, 0x0b4c60ac, 0x0007502c, 0x00070163, 0x28f20162, + 0x18004606, 0x11998904, 0x02800000, 0xaeff1f17, 0x18007606, 0x01800000, + 0x9172fb4f, 0x170b0000, 0x61650007, 0x68004b06, 0x4b0668f2, 0x00076804, + 0x4b066164, 0x00076820, 0x7b066171, 0xffa57828, 0xfe972fa0, 0x00800080, + 0xd6a70b92, 0x76401504, 0xc4a7b3a7, 0x63401504, 0x54401504, 0x300f66a7, + 0x6d0d0600, 0x91a76600, 0x74a7f8a7, 0xe7a7a2a7, 0x83a75fa7, 0x9ec957a8, + 0x0100020f, 0x7600fd06, 0x0ec957a8, 0x1114000d, 0x7600f106, 0x718b57a8, + 0x08adde0f, 0x87adde0d, 0x16fcf906, 0x4f0657ac, 0x40801630, 0x0400300f, + 0x300fa1bc, 0x680d0100, 0x06a81150, 0x66938904, 0x06360040, 0xfafe1f1f, + 0x0600500f, 0x41006c08, 0x6600600d, 0x0700100f, 0x78003a0d, 0x000086b4, + 0x08b506b9, 0x08140000, 0x380087b7, 0x06b5e720, 0x06000800, 0x87b488b4, + 0x66a506ac, 0x83a574a5, 0x67201804, 0x45201804, 0x36201804, 0x91a55fa5, + 0xe7a5a2a5, 0xd6a5f8a5, 0xb3a5c4a5, 0xa0055e97, 0x00800000, 0xf8a70592, + 0x0800300f, 0x6a08d6a7, 0xe04b8620, 0xe7a7b1a7, 0x56a950ac, 0x06a806ac, + 0x6608c6b8, 0x01a88734, 0x864c680d, 0x420661ac, 0x0ba11718, 0x119b8904, + 0x81346608, 0x8650680d, 0x420600ac, 0x40c9111c, 0x87306d08, 0x880c0000, + 0x68ac51ac, 0xd6a5b1a5, 0xf8a5e7a5, 0xa005be97, 0x00800000, 0x03000192, + 0xffa78889, 0x200c71a8, 0x91ba1100, 0x0100300f, 0x11346008, 0x0600f000, + 0x062c0040, 0x02800000, 0x01200000, 0x06000100, 0x0540000f, 0x12650007, + 0x62640007, 0x52640007, 0x00208249, 0xb6fe1f17, 0xc3300000, 0x0700300f, + 0x7700660d, 0x52650007, 0x50c961a8, 0x61aa61b6, 0xffa571ac, 0xfe972fa0, + 0x00800080, 0x38f00049, 0xffa704f0, 0x00c971a8, 0xe3050000, 0x71a871b4, + 0xff0188c9, 0x1f17f700, 0x71b495fe, 0x178a71a8, 0xffa577b6, 0xfe972fa0, + 0x00800080, 0x37f00049, 0x61a8ffa7, 0xd1b94080, 0xc014ffa5, 0x00800812, + 0x00a0204c, 0x880466a8, 0x11866601, 0x049366ac, 0x78fe1f17, 0xc3090000, + 0x000d61a8, 0x61b41106, 0x80c961a8, 0xffa561b6, 0xfe972fa0, 0x00200040, + 0xfe972fa0, 0x00800080, 0x37f00049, 0x61a8ffa7, 0x80144080, 0xffa5204e, + 0x0810c014, 0x41980080, 0x880466a8, 0x11866601, 0x000066ac, 0xc0f30180, + 0x1130000c, 0x200c8414, 0xc3090000, 0x00a0a14d, 0x48fe1f17, 0x00208249, + 0x000d61a8, 0x61b41106, 0x80c961a8, 0xffa561b6, 0xfe972fa0, 0x00200040, + 0xfe972fa0, 0x00800080, 0xffa70192, 0x000c21a8, 0x84141120, 0xffa5200e, + 0xfe972fa0, 0x00200040, 0x21a89b49, 0x000048c9, 0x61b40680, 0x000cc5f3, + 0x00001130, 0x841cc309, 0x439b2006, 0x1afe1f17, 0x00208249, 0x30c961a8, + 0x61a861b4, 0x61b6a8c9, 0x2fa0ffa5, 0x0080fe97, 0x006d8014, 0x07140000, + 0x0700300f, 0x7780690d, 0x112061a8, 0x61ac61c0, 0x890461a8, 0x890411bd, + 0x61ac119c, 0x17844d06, 0x1102000c, 0xfd0881bb, 0x300f7184, 0x680d0800, + 0x00a08850, 0x890466a8, 0x76bc66fe, 0x890476a8, 0xc349629c, 0x52b60020, + 0x000c06a8, 0x831c6602, 0x00a0c0e6, 0x890461a8, 0x004011bc, 0x89042f20, + 0x61b6119d, 0xaef246f3, 0x418a21a8, 0x51fe7f1d, 0x46f32fa0, 0x07620007, + 0x4670ac49, 0x0200300f, 0x2204670d, 0x07003000, 0x718a11a8, 0x20fc8315, + 0x0100300f, 0x12006708, 0x124c2498, 0x670d13ac, 0x1f161304, 0x100fabff, + 0x00800700, 0x300f0192, 0x600d0100, 0x93bb11dc, 0x8949ffa7, 0x049908f0, + 0x21a8824c, 0x080f18c9, 0x21ac0700, 0x96ff1f17, 0x46920000, 0x13744706, + 0x770668c9, 0xffa51374, 0xfe972fa0, 0x00200040, 0x05f08949, 0x0870824c, + 0xcc6421a8, 0x040f0020, 0x21ac0700, 0x7eff1f17, 0x46920000, 0x13744706, + 0x770670c9, 0xffa51374, 0xfe972fa0, 0x00800080, 0x300f0192, 0x600d0b00, + 0xf000b934, 0x0b0f0100, 0x000d0616, 0xffa76a08, 0x1910f006, 0xa904f006, + 0xa9ecff06, 0x19084106, 0x51b84080, 0x2fa0ffa5, 0x0080fe97, 0x0d800000, + 0x300f019a, 0x6a0d0600, 0x00076624, 0x56a81d61, 0x000066b9, 0x00070710, + 0x300f1d62, 0x680d0100, 0x06a81150, 0x04003dc9, 0xf1068800, 0xf20661dc, + 0x08ac71d4, 0x2fa0ffa5, 0x0080fe97, 0x8c890300, 0x1c004006, 0x1140000c, + 0x20c88114, 0xb7a86408, 0x1c004006, 0x1100200c, 0x1f1741be, 0x139859fc, + 0x1c004006, 0x1100200c, 0x4006a1be, 0x080c1c00, 0x51be1100, 0x74ff1f17, + 0x00a08149, 0x1c004006, 0x1100200c, 0x4006a1bc, 0x400c1c00, 0x81151100, + 0x67082006, 0x00a0bb08, 0x1c004006, 0x1100200c, 0x030061b9, 0x01a88186, + 0x1100040c, 0x059301bb, 0x44100000, 0x3aff1f17, 0x00a0294c, 0x0100300f, + 0x1150680d, 0x890406a8, 0x06b66691, 0x0200300f, 0x224c680d, 0x11a81398, + 0x00208464, 0x04100000, 0xe8fb1f17, 0x12e0f106, 0x1c004006, 0x11bc8904, + 0xf50f0000, 0x96fb1f17, 0x1c007006, 0x3204f306, 0x890483f3, 0x83f211b6, + 0x400615ac, 0x200c1c00, 0x80151100, 0x0000206a, 0x20000880, 0x02000100, + 0x00070200, 0x04931864, 0xccfc1f17, 0x00a0a14c, 0x0700300f, 0x7720610d, + 0x28640007, 0x61287b4e, 0x87870300, 0x61ac1298, 0x1d430007, 0x20c9618a, + 0x0710000f, 0x0000c7f2, 0x00070104, 0x04002d61, 0x00070280, 0x00077d61, + 0x00071865, 0x00072865, 0x0b451d43, 0x000d0020, 0xc7f26130, 0xf006f19f, + 0xf0061910, 0x7006a904, 0xffa5a900, 0xfe972fa0, 0x00200040, 0xf1050000, + 0x44100000, 0x1b007006, 0xc4fe1f17, 0x05f0514c, 0x00000593, 0x1f174410, + 0xb398bdfe, 0x00000593, 0x1f174410, 0x9398b7fe, 0xf1040000, 0x70060593, + 0x00001b00, 0x1f174410, 0xa398adfe, 0x00000593, 0x1f174410, 0xb398a7fe, + 0x00000593, 0x1f174410, 0x7398a1fe, 0x00000593, 0x1f174410, 0x93989bfe, + 0x31080000, 0x1b48f106, 0x1b004006, 0x11958904, 0x48ff1f16, 0x1b007006, + 0x04f0084c, 0x0020444c, 0x17a8f306, 0x52fc1f17, 0xe3040000, 0x8d610007, + 0x78c961a8, 0x12ff1f16, 0x008061ac, 0x300f0192, 0x60080d00, 0xf000d134, + 0x0b0f0600, 0x000d0716, 0xffa77908, 0x6110f006, 0x8a890300, 0x09ac89b4, + 0x1a004006, 0x1100200c, 0x20848015, 0x41880300, 0x1f170493, 0x03a82bfc, + 0x0100300f, 0x113c610d, 0x890406a8, 0x831466f3, 0x0000c0fa, 0x00000780, + 0x000f0604, 0x00070110, 0x86f26764, 0x16fc1f17, 0x43100000, 0x02000200, + 0x00071198, 0x784e2765, 0xeef386f2, 0x20c9618a, 0x0600300f, 0x6620610d, + 0xc506c6f2, 0x03001618, 0x0300028a, 0x11ac8887, 0x78a811a8, 0x03008189, + 0x20000888, 0x71ac0200, 0x71a853a8, 0x51ac3188, 0x27650007, 0x1a004006, + 0x1100200c, 0x030061b9, 0x01a88186, 0x1100040c, 0x059301bb, 0x44100000, + 0x14fe1f17, 0x00a0214c, 0x0100300f, 0x1150680d, 0x890406a8, 0x06b66692, + 0x1a004006, 0x1100200c, 0x4006a1bc, 0x400c1a00, 0x80151100, 0x670820c6, + 0x00a0dc08, 0x00208249, 0xc4fb1f17, 0x43100000, 0x1a004006, 0x1100200c, + 0x4006a1be, 0x080c1a00, 0x51be1100, 0x04fe1f17, 0x00a0094c, 0x1a004006, + 0x1100200c, 0x1f1741be, 0x0393d3fa, 0x1a004006, 0x1140000c, 0x000021bb, + 0x434c0180, 0x64080470, 0xa8f2d7a8, 0x07a8f306, 0x9cfb1f17, 0xe3040000, + 0x890461a8, 0x61ac1190, 0x01800000, 0x0370034d, 0x0400300f, 0x444c680d, + 0xa872f94f, 0x806431a8, 0x1f170020, 0x31ac7ffa, 0x1a004006, 0x119c8904, + 0x30fa1f17, 0x1af0ff06, 0x14e0c106, 0x580c218c, 0x000d1100, 0xf8061106, + 0x7e061400, 0x7e062408, 0x7e069418, 0xffa5941c, 0xfe972fa0, 0x00200040, + 0xfb050000, 0x70060593, 0x0000bc00, 0x1f174410, 0x839895fd, 0xf1040000, + 0x70060593, 0x00001c00, 0x1f174410, 0x83988bfd, 0xbc007006, 0x05708249, + 0x50fb1f17, 0x43100000, 0x44100000, 0x7efd1f17, 0x00a0694c, 0x00000593, + 0x1f174410, 0xc39877fd, 0xf1040000, 0x70060593, 0x00001c00, 0x1f174410, + 0x63986dfd, 0x00000593, 0x1f174410, 0xd39867fd, 0x3b080000, 0x00000593, + 0x1f174410, 0xc3985ffd, 0xbc48f106, 0x1c004006, 0x11968904, 0x62ff1f16, + 0x1c007006, 0x37f00049, 0x43708249, 0x61a8ffa7, 0x1f1710c9, 0x61b417fb, + 0x8c6461a8, 0x1f170020, 0x61b411fb, 0xa0c961a8, 0x61a861b4, 0x61b488c9, + 0x00c961a8, 0x61a861b4, 0x1f17c0c9, 0x61b403fb, 0xe46461a8, 0x1f170020, + 0x61b4fdfa, 0xe86461a8, 0x1f170020, 0x61b4f7fa, 0xd8c961a8, 0xffa561b6, + 0xf0fa1f16, 0x0080fe97, 0x37f00049, 0x43708249, 0x61a8ffa7, 0x1f1718c9, + 0x61b4e5fa, 0x886461a8, 0x1f170020, 0x61b4dffa, 0x88c961a8, 0x61a861b4, + 0x61b4a0c9, 0x00c961a8, 0xffa561b6, 0xfe972fa0, 0x00800080, 0x80150192, + 0xffa76822, 0x0100300f, 0x11a4640d, 0x801501a8, 0x500f2112, 0x08000600, + 0x61880103, 0x06ac1698, 0x61108014, 0x0100800f, 0x3104001c, 0x86f91f1f, + 0x0700800f, 0x00153193, 0x00003705, 0x11980680, 0x0700010f, 0x16700007, + 0x76640007, 0x164c0007, 0x11f08904, 0x20f8831c, 0x76650007, 0x680c8015, + 0x2fa0ffa5, 0x0080fe97, 0x640c8015, 0x2fa0ffa5, 0x0080fe97, 0x1f16ffa5, + 0xfe9759f9, 0x300f0792, 0x600d0b00, 0xf000ba34, 0x0b0f0100, 0x000d0616, + 0x9fa76c08, 0x1a10f006, 0xca04f006, 0xcaecff06, 0xda704106, 0x8a704406, + 0xd804001c, 0xad3e0040, 0xb1a46408, 0x08ac00ac, 0x2fa09fa5, 0x00809e97, + 0x3cf91f1f, 0x0500300f, 0x55f8640d, 0xf94c5793, 0xcf064128, 0x21206780, + 0x00816620, 0xf6a766ac, 0x67844d06, 0x66542120, 0x0011a013, 0x02006289, + 0x00190600, 0x00a06d0b, 0x06000200, 0x001bd993, 0xa01b8609, 0x00a0a00f, + 0x06200000, 0x69e20904, 0x000de011, 0xe0190693, 0x16982007, 0x692cf94c, + 0x77844d06, 0x77542120, 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0x0100300f, + 0x114c680d, 0x890406a8, 0x06b66691, 0x0100300f, 0x114c680d, 0x5dc906a8, + 0x61e0f106, 0xddc906a8, 0xffa506ac, 0xfe972fa0, 0x00800080, 0x300f0192, + 0x60080100, 0xf0001134, 0x0b0f0600, 0x000d0716, 0xffa77508, 0x6110f006, + 0x05ac85b4, 0x11f44006, 0x1140000c, 0xffa561b8, 0xfe972fa0, 0x00200040, + 0x0100300f, 0x11f4640d, 0x88860300, 0x8dc906a8, 0x71a806b6, 0xd1ba4080, + 0x0100500f, 0x1798f698, 0x12701008, 0x87ac06af, 0x890411a8, 0x11ac11b6, + 0x06800000, 0xedf3f19c, 0x20c9618a, 0x06800000, 0x0200300f, 0x224c680d, + 0x11a8c5f2, 0x11eb8904, 0x00a041be, 0x90ff1f1f, 0x000c71a8, 0x71bb1102, + 0x0700500f, 0x7304cf0d, 0x08f31f17, 0x00200a4c, 0x0600300f, 0x6650680d, + 0x744cc30d, 0x04f31f17, 0x7340c30d, 0x886451a8, 0x51b60020, 0x11a8394c, + 0x00209c64, 0x87890300, 0x00f31f17, 0x112cfa4f, 0x890461a8, 0x1f1711be, + 0x61b6b1f2, 0x12e0c106, 0x580c418c, 0x000d1100, 0xf8061158, 0x7e061200, + 0x7e064208, 0x7e065218, 0xffa5521c, 0xfe972fa0, 0x00800080, 0x03000192, + 0xffa78189, 0x890401a8, 0x51bb11f1, 0x0700300f, 0x00208249, 0xdef31f17, + 0xe3040000, 0x38f51f17, 0x7374630d, 0x0100300f, 0x114c680d, 0x890406a8, + 0x06b66693, 0x0100300f, 0x114c680d, 0x65c906a8, 0x61e0f106, 0xe5c906a8, + 0xffa506ac, 0xfe972fa0, 0x00800080, 0x03000192, 0xffa78189, 0x890401a8, + 0x31bb11f6, 0x0200300f, 0x12f51f17, 0x23b8630d, 0x0ef51f17, 0x23bc630d, + 0x0100300f, 0x114c680d, 0x890406a8, 0x06b66695, 0x0100300f, 0x114c680d, + 0x75c906a8, 0x61e0f106, 0xf5c906a8, 0xffa506ac, 0xfe972fa0, 0x00800080, + 0x300f0592, 0x60080b00, 0xf000b134, 0x0b0f0600, 0x000d0716, 0xbfa77c08, + 0x6110f006, 0x0cac8cb4, 0x11f44006, 0x1104000c, 0xbfa561b8, 0xbe972fa0, + 0x00200040, 0x0100300f, 0x11f4640d, 0x85c906a8, 0x030006b6, 0xd1a78189, + 0x800c01a8, 0xd1b81100, 0xf6fffc01, 0x0701500f, 0x7714c00d, 0x618a61a8, + 0x61a861b5, 0x66b6168a, 0x0100500f, 0x12c01008, 0xbaf41f17, 0xb3b0630d, + 0x0500040f, 0x15acd1a5, 0x01280040, 0x1102000c, 0x2078801c, 0x81860300, + 0x890401a8, 0xd1bc11ff, 0x4af21f17, 0xb3c0630d, 0x0100300f, 0x110c660d, + 0x890406a8, 0x06b6669f, 0x0200300f, 0x224c680d, 0xfa4f3398, 0x8c641128, + 0x1f170020, 0x11ac2bf2, 0x1693d1a5, 0x890401a8, 0x1f1711bd, 0x51b6dbf1, + 0x12e0c106, 0x580c418c, 0x000d1100, 0xf8061106, 0x7e061200, 0x7e064208, + 0x7e06c218, 0xbfa5c21c, 0xbe972fa0, 0x00200040, 0x0200300f, 0x224c680d, + 0x890411a8, 0x31be11ec, 0x22ff1f1f, 0x890411a8, 0x31be11ee, 0x48ff1f1f, + 0x08100000, 0x0113190f, 0x8ff3864c, 0x22b58904, 0x1398320d, 0xb1306d08, + 0xf50f0000, 0x8f728549, 0x5120fb06, 0xc1a7004d, 0xfda78449, 0xe1278449, + 0x0700800f, 0x0680000f, 0x0420000f, 0xd0fa1f17, 0x00a00a4c, 0xf0a7004d, + 0x0700400f, 0xe1270040, 0x05080000, 0x06a00000, 0x0440000f, 0xc0fa1f17, + 0x03000400, 0xe4f11f17, 0xb3a4630d, 0x01ff000f, 0x16f20f0d, 0xdcf11f17, + 0xb324630d, 0x7b06c1a5, 0x01a86144, 0xc6259464, 0x72ff1f16, 0x008051ac, + 0x0100400f, 0x05700449, 0x1c01000d, 0x81890300, 0x8fa7714c, 0xf1270040, + 0x0100300f, 0x19b06008, 0xe0f41f17, 0x44100000, 0x099cf706, 0x19304e06, + 0xe9278040, 0x11771e04, 0x0b00f00f, 0x1f0f1b8b, 0x990d0dff, 0xf006ddd0, + 0xf006b904, 0xf1a5c904, 0xc6880300, 0xe00f01a8, 0x530d0a00, 0xfd06aa10, + 0xd9a719e0, 0x0904f006, 0x0904f006, 0x0904f006, 0x70069d88, 0x40060900, + 0x00811d00, 0xd7001708, 0x512c3d44, 0x17104b06, 0xc6860300, 0x4b0651ac, + 0x03001740, 0x51ac8688, 0x030061a8, 0x51acc687, 0x17704406, 0x46890300, + 0x440651ac, 0x03001790, 0x51ac0689, 0x17a44406, 0x46860300, 0x4b0651ac, + 0x030017c0, 0x51ac0686, 0x17b84606, 0x46870300, 0x4b0651ac, 0x030017b0, + 0xf84f0687, 0xfe0651ac, 0xf1a51a30, 0x01a8caa7, 0x11f38904, 0x500fa1bc, + 0x1b0d0100, 0x06a811c8, 0x6605000d, 0x06360040, 0x01a8f1a5, 0x1100010c, + 0x000081ba, 0x01000180, 0x00070600, 0x00a06165, 0x01a8f1a5, 0x1100020c, + 0x510fa1b9, 0x0b000600, 0x3044c103, 0x000000a0, 0x000fe710, 0xcd0d0626, + 0xf1066600, 0xf1067100, 0xf1067100, 0x0b447100, 0xf106072c, 0xf1067600, + 0x57ac7600, 0x0100300f, 0x162c6a08, 0x01d20500, 0x020fb6a7, 0xf2060716, + 0x7f0d16d4, 0xf1a577d8, 0x01a857ac, 0x11f78904, 0x000f61ba, 0x57a80116, + 0x51ac718b, 0x0100300f, 0x11306a0d, 0x0694010f, 0xa1270040, 0x01100000, + 0x03400000, 0x20f71f17, 0x61650007, 0x01100000, 0x890480f3, 0x011511f2, + 0xd1a5010b, 0x011501a8, 0xc1a50107, 0x890401a8, 0x011511e8, 0x00000101, + 0x80f30110, 0x11f38904, 0x20988115, 0xa1250040, 0x01100000, 0x80730040, + 0x11f48904, 0x20548115, 0x01800000, 0x01100000, 0x890480f3, 0x801511f5, + 0xa1a520c2, 0x01100000, 0x890480f3, 0xd1bb11f6, 0xa1250040, 0x01800000, + 0x06800400, 0x00008005, 0x61640007, 0x01a8f1a5, 0x11fc8904, 0x0000c1ba, + 0x784e0180, 0x618ae8f3, 0x000020c9, 0x1f170680, 0xc5f25bf5, 0xb4ff1f1e, + 0x91a701a8, 0x1120000c, 0x20688015, 0x040c91a5, 0x80151100, 0x91a52056, + 0x1180000c, 0x20448015, 0x000c91a5, 0x51bc1108, 0x00200040, 0xf2fd1f1f, + 0x01100000, 0x08100000, 0x890480f3, 0x300f11b6, 0x97a50600, 0x6d0887f2, + 0x00006630, 0x000cf10f, 0x51ac7702, 0xe078831c, 0xf4f31f1f, 0xb8ff1f1e, + 0xfefc1f1f, 0xe6210040, 0xc0f01f1f, 0xe2210040, 0xfafa1f1f, 0xde210040, + 0x080c01a8, 0x96bc1600, 0x0600300f, 0x6660660d, 0x6d8056a8, 0xc064801d, + 0x1600100c, 0x300fa6bc, 0x660d0600, 0x56a86660, 0x6602000c, 0xc244801c, + 0x1100400c, 0x300fc1bc, 0x610d0100, 0x01a8116c, 0x1100080c, 0x00a041be, + 0x7efd1f1f, 0x01100000, 0x07100000, 0x890480f3, 0x300f11b5, 0x86f20600, + 0x66306d08, 0xf10f0000, 0x6eff1f16, 0x512c0040, 0x3efd1f1f, 0xec210040, + 0x8afc1f1f, 0xe8210040, 0x8904c0f3, 0x31bc11f0, 0x8ef61f1f, 0x01100000, + 0x07100000, 0x890480f3, 0x300f11b4, 0x86f20600, 0x66306d08, 0xf10f0000, + 0x46ff1f16, 0x512c0040, 0x020c01a8, 0x80151600, 0x000cc04e, 0xf6bb1610, + 0x1640000c, 0x000c86bf, 0x31bc1104, 0xb2fb1f1f, 0x01100000, 0x07100000, + 0x890480f3, 0x300f11b3, 0x86f20600, 0x66306d08, 0xf10f0000, 0x1aff1f16, + 0x512c0040, 0x56f81f1f, 0xec210040, 0x5cf91f1f, 0xe8210040, 0x20f01f1f, + 0xe4210040, 0x01a8f1a5, 0x11fd8904, 0x00a041be, 0x8cfb1f1f, 0x01a8f1a5, + 0x11f28904, 0x300fe1ba, 0x00a00100, 0x96f21f17, 0x13c0630d, 0x01a8e1a5, + 0x16928904, 0x06ace1a5, 0x01a8f1a5, 0x11f18904, 0x300fe1ba, 0x00a00100, + 0x54f21f17, 0x1374630d, 0x01a8e1a5, 0x16948904, 0x06ace1a5, 0x01a8f1a5, + 0x11fe8904, 0x00a041be, 0x18f81f1f, 0x01a8f1a5, 0x11fb8904, 0x00a041be, + 0xe2ef1f1f, 0x01a8f1a5, 0x11ff8904, 0x00a041be, 0x12f91f1f, 0x01a8c1a5, + 0x11ff8904, 0x4c0f61b8, 0x0b4c0156, 0x06ac0020, 0x01564c0f, 0x0600a000, + 0x0700800f, 0x080a800f, 0x87af06af, 0x082f0040, 0xb2f51f17, 0x03800000, + 0x0794010f, 0x01100000, 0x86000400, 0x71640007, 0x07100000, 0xf206b1a5, + 0xf00671d4, 0x00006130, 0xadf30610, 0x66b38904, 0x0000aef2, 0x06acf60f, + 0x06100000, 0x8904adf3, 0xaef266b6, 0xf60f0000, 0x000006ac, 0xadf30610, + 0x66b58904, 0x0000aef2, 0x06acf60f, 0x01a8f1a5, 0x11f38904, 0x500fc1bc, + 0x1b0d0100, 0x06a811cc, 0x86b715c9, 0x866406a8, 0x06b600a0, 0x0100300f, + 0x1140610d, 0x61fcc406, 0x4a0686b4, 0xf30661e0, 0xfa0661ec, 0x7c060100, + 0x06a80184, 0x06ac0dc9, 0x01a8f1a5, 0x1100020c, 0x20c8801c, 0x0100510f, + 0x113cb00d, 0x040c01a8, 0x71ba1181, 0x0600510f, 0xc1030b00, 0x00ac6188, + 0x0100510f, 0x113cb10d, 0x040c01a8, 0x71ba1181, 0x0600510f, 0xc1130b00, + 0x00ac6188, 0x0100510f, 0x113cb20d, 0x040c01a8, 0x71ba1181, 0x0600510f, + 0xc1230b00, 0x00ac6188, 0x0100510f, 0x113cb30d, 0x040c01a8, 0x71ba1181, + 0x0600510f, 0xc1330b00, 0x00ac6188, 0x0127510f, 0x113c800d, 0x040c01a8, + 0x71ba1181, 0x0627510f, 0xc1030800, 0x00ac6188, 0x0127510f, 0x113c810d, + 0x040c01a8, 0x71ba1181, 0x0627510f, 0xc1130800, 0x00ac6188, 0x0127510f, + 0x113c820d, 0x040c01a8, 0x71ba1181, 0x0627510f, 0xc1230800, 0x00ac6188, + 0x00000593, 0x1f174410, 0xf398f9f1, 0x1f168fa5, 0x8e97ebf0, 0x801d43bc, + 0x00a06112, 0x01800000, 0x0600020f, 0x68720040, 0x81890300, 0x040c01a8, + 0x31be1100, 0x3f200040, 0x6608801d, 0x3f200040, 0x6708801d, 0x3f200040, + 0x00002fa0, 0x80f20180, 0x0100300f, 0x11746408, 0xf6af0000, 0x07cccc0f, + 0x77cccc0d, 0xf0062fa0, 0x07ac6128, 0x09800000, 0x00a00049, 0x0700300f, + 0x77a0640d, 0x19400007, 0x8904ffa7, 0x61a81afe, 0xc6ff1f17, 0x13082120, + 0x0800040f, 0x0200100f, 0x0400080f, 0x200fcab8, 0x00070500, 0x00078962, + 0x00072962, 0x0ba14961, 0x59610007, 0x89610007, 0x29610007, 0x49620007, + 0x59620007, 0x1c0d61a8, 0x05001100, 0x61b606bc, 0x619d8904, 0xff017188, + 0x07a8b67f, 0xff0f768a, 0x86b407ef, 0x76fff70d, 0x768a07a8, 0xffa506b6, + 0xfe972fa0, 0x00800080, 0xcfa70492, 0x78ef1f1f, 0xb6ff1f1f, 0xa6ff1f1f, + 0x81890300, 0x0300f1a7, 0xe1a78186, 0x01800000, 0x06200000, 0x61640007, + 0x01100000, 0x0694010f, 0x61650007, 0x01160b0f, 0x0600300f, 0x110c000d, + 0x66446008, 0x400651ac, 0x831576dc, 0x010fe0fa, 0x300f0794, 0x60080600, + 0x51ac6648, 0x01100000, 0x71640007, 0x16b84506, 0x61acf7a5, 0x16c04506, + 0x51b4e6a5, 0x66a8d6a7, 0x0100f80f, 0x1f17618b, 0x61acbded, 0x01a8f1a5, + 0x1100040c, 0x00a041be, 0x48fc1f1f, 0x01a8f1a5, 0x1100040c, 0xf1a581b8, + 0x000c01a8, 0x31be1120, 0x66ee1f1f, 0x01a8d1a5, 0x1140000c, 0x20688314, + 0x0600800f, 0x07800000, 0xcfa58049, 0x67670007, 0x3f20e74b, 0x01000100, + 0x01000201, 0x02010201, 0x01000402, 0x02010402, 0x04020402, 0x01000803, + 0x02010803, 0x04020803, 0x01001004, 0x02011004, 0x04021004, 0x08031004, + 0x01002005, 0x02012005, 0x04022005, 0x08032005, 0x01004006, 0x02014006, + 0x04024006, 0x08034006 +}; + +static struct spm_desc spm_firmware = { + .version = "pcm_suspend_v1.43_no_GPU_WAYEN", + .pmem_words = 0x9bf, + .total_words = 0x9d4, + .pmem_start = 0x10000000, + .dmem_start = 0x10003800 +}; + +static struct pwr_ctrl spm_init_ctrl = { + /* Auto-gen Start */ + + .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS | + SPM_FLAG_RUN_COMMON_SCENARIO, + + /* SPM_AP_STANDBY_CON */ + .reg_wfi_op = 0, + .reg_wfi_type = 0, + .reg_mp0_cputop_idle_mask = 0, + .reg_mp1_cputop_idle_mask = 0, + .reg_mcusys_idle_mask = 0, + .reg_md_apsrc_1_sel = 0, + .reg_md_apsrc_0_sel = 0, + .reg_conn_apsrc_sel = 0, + + /* SPM_SRC6_MASK */ + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dpmaif_ddr_en_mask_b = 1, + + /* SPM_SRC_REQ */ + .reg_spm_apsrc_req = 0, + .reg_spm_f26m_req = 0, + .reg_spm_infra_req = 0, + .reg_spm_vrf18_req = 0, + .reg_spm_ddr_en_req = 1, + .reg_spm_dvfs_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_scp_mailbox_req = 0, + + /* SPM_SRC_MASK */ + .reg_md_srcclkena_0_mask_b = 1, + .reg_md_srcclkena2infra_req_0_mask_b = 0, + .reg_md_apsrc2infra_req_0_mask_b = 1, + .reg_md_apsrc_req_0_mask_b = 1, + .reg_md_vrf18_req_0_mask_b = 1, + .reg_md_ddr_en_0_mask_b = 1, + .reg_md_srcclkena_1_mask_b = 0, + .reg_md_srcclkena2infra_req_1_mask_b = 0, + .reg_md_apsrc2infra_req_1_mask_b = 0, + .reg_md_apsrc_req_1_mask_b = 0, + .reg_md_vrf18_req_1_mask_b = 0, + .reg_md_ddr_en_1_mask_b = 0, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 0, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_conn_ddr_en_mask_b = 1, + .reg_conn_vfe28_mask_b = 0, + .reg_srcclkeni0_srcclkena_mask_b = 1, + .reg_srcclkeni0_infra_req_mask_b = 1, + .reg_srcclkeni1_srcclkena_mask_b = 0, + .reg_srcclkeni1_infra_req_mask_b = 0, + .reg_srcclkeni2_srcclkena_mask_b = 0, + .reg_srcclkeni2_infra_req_mask_b = 0, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddr_en_mask_b = 1, + .reg_md32_srcclkena_mask_b = 1, + .reg_md32_infra_req_mask_b = 1, + .reg_md32_apsrc_req_mask_b = 1, + .reg_md32_vrf18_req_mask_b = 1, + .reg_md32_ddr_en_mask_b = 1, + + /* SPM_SRC2_MASK */ + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_vrf18_req_mask_b = 1, + .reg_scp_ddr_en_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_audio_dsp_ddr_en_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_ufs_ddr_en_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddr_en_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddr_en_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gce_ddr_en_mask_b = 1, + .reg_apu_srcclkena_mask_b = 1, + .reg_apu_infra_req_mask_b = 1, + .reg_apu_apsrc_req_mask_b = 1, + .reg_apu_vrf18_req_mask_b = 1, + .reg_apu_ddr_en_mask_b = 1, + .reg_cg_check_srcclkena_mask_b = 0, + .reg_cg_check_apsrc_req_mask_b = 0, + .reg_cg_check_vrf18_req_mask_b = 0, + .reg_cg_check_ddr_en_mask_b = 0, + + /* SPM_SRC3_MASK */ + .reg_dvfsrc_event_trigger_mask_b = 1, + .reg_sw2spm_int0_mask_b = 0, + .reg_sw2spm_int1_mask_b = 0, + .reg_sw2spm_int2_mask_b = 0, + .reg_sw2spm_int3_mask_b = 0, + .reg_sc_adsp2spm_wakeup_mask_b = 0, + .reg_sc_sspm2spm_wakeup_mask_b = 0, + .reg_sc_scp2spm_wakeup_mask_b = 0, + .reg_csyspwrreq_mask = 1, + .reg_spm_srcclkena_reserved_mask_b = 0, + .reg_spm_infra_req_reserved_mask_b = 0, + .reg_spm_apsrc_req_reserved_mask_b = 0, + .reg_spm_vrf18_req_reserved_mask_b = 0, + .reg_spm_ddr_en_reserved_mask_b = 0, + .reg_mcupm_srcclkena_mask_b = 1, + .reg_mcupm_infra_req_mask_b = 1, + .reg_mcupm_apsrc_req_mask_b = 1, + .reg_mcupm_vrf18_req_mask_b = 1, + .reg_mcupm_ddr_en_mask_b = 1, + .reg_msdc0_srcclkena_mask_b = 1, + .reg_msdc0_infra_req_mask_b = 1, + .reg_msdc0_apsrc_req_mask_b = 1, + .reg_msdc0_vrf18_req_mask_b = 1, + .reg_msdc0_ddr_en_mask_b = 1, + .reg_msdc1_srcclkena_mask_b = 1, + .reg_msdc1_infra_req_mask_b = 1, + .reg_msdc1_apsrc_req_mask_b = 1, + .reg_msdc1_vrf18_req_mask_b = 1, + .reg_msdc1_ddr_en_mask_b = 1, + + /* SPM_SRC4_MASK */ + .ccif_event_mask_b = 0xFFF, + .reg_bak_psri_srcclkena_mask_b = 0, + .reg_bak_psri_infra_req_mask_b = 0, + .reg_bak_psri_apsrc_req_mask_b = 0, + .reg_bak_psri_vrf18_req_mask_b = 0, + .reg_bak_psri_ddr_en_mask_b = 0, + .reg_dramc0_md32_infra_req_mask_b = 1, + .reg_dramc0_md32_vrf18_req_mask_b = 0, + .reg_dramc1_md32_infra_req_mask_b = 1, + .reg_dramc1_md32_vrf18_req_mask_b = 0, + .reg_conn_srcclkenb2pwrap_mask_b = 0, + .reg_dramc0_md32_wakeup_mask = 1, + .reg_dramc1_md32_wakeup_mask = 1, + + /* SPM_SRC5_MASK */ + .reg_mcusys_merge_apsrc_req_mask_b = 0x11, + .reg_mcusys_merge_ddr_en_mask_b = 0x11, + .reg_msdc2_srcclkena_mask_b = 1, + .reg_msdc2_infra_req_mask_b = 1, + .reg_msdc2_apsrc_req_mask_b = 1, + .reg_msdc2_vrf18_req_mask_b = 1, + .reg_msdc2_ddr_en_mask_b = 1, + .reg_pcie_srcclkena_mask_b = 1, + .reg_pcie_infra_req_mask_b = 1, + .reg_pcie_apsrc_req_mask_b = 1, + .reg_pcie_vrf18_req_mask_b = 1, + .reg_pcie_ddr_en_mask_b = 1, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0xEFFFFFFF, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /* Auto-gen End */ +}; + +static void spm_set_power_control(struct pwr_ctrl *pwrctrl) +{ + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + write32(&mtk_spm->spm_ap_standby_con, + ((pwrctrl->reg_wfi_op & 0x1) << 0) | + ((pwrctrl->reg_wfi_type & 0x1) << 1) | + ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | + ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | + ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | + ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | + ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | + ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); + + /* SPM_SRC6_MASK */ + write32(&mtk_spm->spm_src6_mask, + ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4)); + + /* SPM_SRC_REQ */ + write32(&mtk_spm->spm_src_req, + ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | + ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | + ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | + ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | + ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) | + ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | + ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | + ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | + ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | + ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); + + /* SPM_SRC_MASK */ + write32(&mtk_spm->spm_src_mask, + ((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) | + ((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) | + ((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) | + ((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) | + ((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) | + ((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) | + ((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) | + ((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) | + ((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) | + ((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) | + ((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) | + ((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) | + ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) | + ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) | + ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) | + ((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) | + ((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) | + ((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) | + ((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31)); + + /* SPM_SRC2_MASK */ + write32(&mtk_spm->spm_src2_mask, + ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) | + ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) | + ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) | + ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) | + ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) | + ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) | + ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) | + ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) | + ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31)); + + /* SPM_SRC3_MASK */ + write32(&mtk_spm->spm_src3_mask, + ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) | + ((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) | + ((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) | + ((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) | + ((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) | + ((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) | + ((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) | + ((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) | + ((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) | + ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) | + ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) | + ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) | + ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) | + ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) | + ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) | + ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) | + ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) | + ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) | + ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31)); + + /* SPM_SRC4_MASK */ + write32(&mtk_spm->spm_src4_mask, + ((pwrctrl->ccif_event_mask_b & 0xffff) << 0) | + ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) | + ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) | + ((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) | + ((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) | + ((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27)); + + /* SPM_SRC5_MASK */ + write32(&mtk_spm->spm_src5_mask, + ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) | + ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) | + ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) | + ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) | + ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27)); + + /* SPM_WAKEUP_EVENT_MASK */ + write32(&mtk_spm->spm_wakeup_event_mask, + ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + write32(&mtk_spm->spm_wakeup_event_ext_mask, + ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); + + /* Auto-gen End */ +} + +static void spm_register_init(void) +{ + u32 reg; + + /* enable register control */ + write32(&mtk_spm->poweron_config_en, SPM_REGWR_CFG_KEY | + BCLK_CG_EN_LSB); + + /* init power control register */ + write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* reset PCM */ + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB | + REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB | + REG_MD32_APB_INTERNAL_EN_LSB); + + /* initial SPM CLK control register */ + write32(&mtk_spm->spm_clk_con, read32(&mtk_spm->spm_clk_con) | + REG_SYSCLK1_SRC_MD2_SRCCLKENA); + + /* clean wakeup event raw status */ + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + /* clean ISR status */ + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + /* init r7 with POWER_ON_VAL1 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* DDR EN de-bounce length to 5us */ + write32(&mtk_spm->ddr_en_dbc_con0, DDR_EN_DBC_CON0_DEF); + write32(&mtk_spm->ddr_en_dbc_con1, REG_ALL_DDR_EN_DBC_EN_LSB); + + /* Configure ARMPLL Control Mode for MCDI */ + write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF); + + /* Init for SPM Resource ACK */ + write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF); + write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF); + write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF); + write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF); + + /* Init VCORE DVFS Status */ + write32(&mtk_spm->spm_dvfs_misc, (read32(&mtk_spm->spm_dvfs_misc) & + ~(SPM_DVFS_FORCE_ENABLE_LSB)) | (SPM_DVFSRC_ENABLE_LSB)); + write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF); + write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF); + + write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1); + write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT); + + /* apm_hw_s1_state_monitor_pause */ + reg = read32(&mtk_spm->spm_ack_chk_con_3); + reg |= (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL); + reg &= ~(SPM_ACK_CHK_3_CON_EN); + write32(&mtk_spm->spm_ack_chk_con_3, reg); +} + +static void spm_set_sysclk_settle(void) +{ + u32 settle; + + write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE); + settle = read32(&mtk_spm->spm_clk_settle); +} + +static void spm_code_swapping(void) +{ + u32 mask; + + mask = read32(&mtk_spm->spm_wakeup_event_mask); + write32(&mtk_spm->spm_wakeup_event_mask, + (mask & ~SPM_WAKEUP_EVENT_MASK_BIT0)); + write32(&mtk_spm->spm_cpu_wakeup_event, 1); + write32(&mtk_spm->spm_cpu_wakeup_event, 0); + write32(&mtk_spm->spm_wakeup_event_mask, mask); +} + +static void spm_reset_and_init_pcm(void) +{ + bool first_load_fw = true; + u32 con1; + + /* check the SPM FW is run or not */ + if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) & + MD32PCM_CFGREG_SW_RSTN_RUN) + first_load_fw = false; + + if (!first_load_fw) { + spm_code_swapping(); + /* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM`*/ + write32(&mtk_spm->spm_power_on_val0, + read32(&mtk_spm->pcm_reg0_data)); + } + + /* disable r0 and r7 to control power */ + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* disable pcm timer after leaving FW */ + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | + (read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB)); + + /* reset PCM */ + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */ + con1 = read32(&mtk_spm->pcm_con1) & (RG_PCM_WDT_WAKE_LSB); + write32(&mtk_spm->pcm_con1, con1 | SPM_REGWR_CFG_KEY | + REG_EVENT_LOCK_EN_LSB | REG_SPM_SRAM_ISOINT_B_LSB | + RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB); +} + +static void spm_kick_im_to_fetch(void) +{ + uintptr_t ptr; + u32 pmem_words; + u32 total_words; + u32 pmem_start; + u32 dmem_start; + u32 con0; + + ptr = (uintptr_t) spm_firmware_binary + 0x40000000; + pmem_words = spm_firmware.pmem_words; + total_words = spm_firmware.total_words; + pmem_start = spm_firmware.pmem_start; + dmem_start = spm_firmware.dmem_start; + + /* tell IM where is PCM code (use slave mode if code existed) */ + if (read32(&mtk_spm->md32pcm_dma0_src) != ptr || + read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start || + read32(&mtk_spm->md32pcm_dma0_wppt) != pmem_words || + read32(&mtk_spm->md32pcm_dma0_wpto) != dmem_start || + read32(&mtk_spm->md32pcm_dma0_count) != total_words || + read32(&mtk_spm->md32pcm_dma0_con) != MD32PCM_DMA0_CON_VAL) { + write32(&mtk_spm->md32pcm_dma0_src, ptr); + write32(&mtk_spm->md32pcm_dma0_dst, pmem_start); + write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words); + write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start); + write32(&mtk_spm->md32pcm_dma0_count, total_words); + write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL); + write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL); + } else { + write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) | + SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB); + } + + /* kick IM to fetch (only toggle IM_KICK) */ + con0 = read32(&mtk_spm->pcm_con0); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); +} + +static void spm_init_pcm_register(void) +{ + /* init r0 with POWER_ON_VAL0 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val0)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* init r7 with POWER_ON_VAL1 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +static void spm_set_wakeup_event(struct pwr_ctrl *pwrctrl) +{ + u32 val, mask, isr; + + /* toggle event counter clear */ + write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) | + SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); + + /* toggle for reset SYS TIMER start point */ + write32(&mtk_spm->sys_timer_con, read32(&mtk_spm->sys_timer_con) | + SYS_TIMER_START_EN_LSB); + + if (pwrctrl->timer_val_cust == 0) + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; + else + val = pwrctrl->timer_val_cust; + + write32(&mtk_spm->pcm_timer_val, val); + + /* disable pcm timer */ + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | + (read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB)); + + /* unmask AP wakeup source */ + if (pwrctrl->wake_src_cust == 0) + mask = pwrctrl->wake_src; + else + mask = pwrctrl->wake_src_cust; + + if (pwrctrl->reg_csyspwrreq_mask) + mask &= ~SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B; + + write32(&mtk_spm->spm_wakeup_event_mask, ~mask); + + /* unmask SPM ISR (keep TWAM setting) */ + isr = read32(&mtk_spm->spm_irq_mask); + write32(&mtk_spm->spm_irq_mask, isr | ISRM_RET_IRQ_AUX); + + /* toggle event counter clear */ + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | + (read32(&mtk_spm->pcm_con1) & ~SPM_EVENT_COUNTER_CLR_LSB)); + + /* toggle for reset SYS TIMER start point */ + write32(&mtk_spm->sys_timer_con, read32(&mtk_spm->sys_timer_con) & + ~SYS_TIMER_START_EN_LSB); +} + +static void spm_set_pcm_flags(struct pwr_ctrl *pwrctrl) +{ + /* set PCM flags and data */ + if (pwrctrl->pcm_flags_cust_clr != 0) + pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; + if (pwrctrl->pcm_flags_cust_set != 0) + pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set; + if (pwrctrl->pcm_flags1_cust_clr != 0) + pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; + if (pwrctrl->pcm_flags1_cust_set != 0) + pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; + + write32(&mtk_spm->spm_sw_flag_0, pwrctrl->pcm_flags); + write32(&mtk_spm->spm_sw_flag_1, pwrctrl->pcm_flags1); + write32(&mtk_spm->spm_sw_rsv_7, pwrctrl->pcm_flags); + write32(&mtk_spm->spm_sw_rsv_8, pwrctrl->pcm_flags1); +} + +static void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) +{ + u32 con0, rstn; + + /* Waiting for loading SPMFW done*/ + while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) + ; + + /* Init register to match PCM expectation */ + write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); + write32(&mtk_spm->spm_bus_protect2_mask_b, + SPM_BUS_PROTECT2_MASK_B_DEF); + write32(&mtk_spm->pcm_reg_data_ini, 0); + + spm_set_pcm_flags(pwrctrl); + + /* Kick PCM to run (only toggle PCM_KICK) */ + con0 = read32(&mtk_spm->pcm_con0); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* Reset md32pcm */ + rstn = read32(&mtk_spm->md32pcm_cfgreg_sw_rstn); + write32(&mtk_spm->md32pcm_cfgreg_sw_rstn, + rstn | MD32PCM_CFGREG_SW_RSTN_RESET); + + /* Waiting for SPM init done */ + udelay(SPM_INIT_DONE_US); +} + +int spm_init(void) +{ + struct stopwatch sw; + + stopwatch_init(&sw); + + spm_register_init(); + spm_set_power_control(&spm_init_ctrl); + spm_set_sysclk_settle(); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(); + spm_init_pcm_register(); + spm_set_wakeup_event(&spm_init_ctrl); + spm_kick_pcm_to_run(&spm_init_ctrl); + + printk(BIOS_INFO, "SPM: %s done in %ld msecs, %s, spm pc = 0x%x\n", + __func__, stopwatch_duration_msecs(&sw), spm_firmware.version, + read32(&mtk_spm->md32pcm_pc)); + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371 Gerrit-Change-Number: 46389 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 77

Change in coreboot[master]: soc/mediatek/common: A common API for loading the blob file
by Yidi Lin (Code Review) 10 Dec '20

10 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46930 ) Change subject: soc/mediatek/common: A common API for loading the blob file ...................................................................... soc/mediatek/common: A common API for loading the blob file load_blob_file is added for loading the blog file to the specified memory address. This function also measures the load time and the blob size. Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: Ie94001bbda25fe015f43172e92a1006e059de223 --- A src/soc/mediatek/common/include/soc/mtlib_common.h A src/soc/mediatek/common/mtlib.c M src/soc/mediatek/mt8192/Makefile.inc 3 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46930/1 diff --git a/src/soc/mediatek/common/include/soc/mtlib_common.h b/src/soc/mediatek/common/include/soc/mtlib_common.h new file mode 100644 index 0000000..3210468 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mtlib_common.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MTLIB_COMMON_H +#define SOC_MEDIATEK_MTLIB_COMMON_H + +int load_blob_file(const char *name, unsigned long addr); + +#endif /* SOC_MEDIATEK_MTLIB_COMMON_H */ diff --git a/src/soc/mediatek/common/mtlib.c b/src/soc/mediatek/common/mtlib.c new file mode 100644 index 0000000..cdb748b --- /dev/null +++ b/src/soc/mediatek/common/mtlib.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <console/console.h> +#include <soc/mtlib_common.h> +#include <timer.h> + +#define BUF_SIZE (128 * KiB) +static u8 blob_data[BUF_SIZE] __aligned(8); + +int load_blob_file(const char *name, unsigned long addr) +{ + struct stopwatch sw; + size_t blob_bytes; + + stopwatch_init(&sw); + + blob_bytes = cbfs_boot_load_file(name, blob_data, sizeof(blob_data), CBFS_TYPE_RAW); + if (blob_bytes == 0) { + printk(BIOS_ERR, "binary %s not found\n", name); + return CB_ERR; + } + + memcpy((void *)addr, blob_data, blob_bytes); + printk(BIOS_DEBUG, "%s: Load %s in %ld msecs, size %ld bytes\n", + __func__, name, stopwatch_duration_msecs(&sw), blob_bytes); + + return CB_SUCCESS; +} diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 6890910..bebb0c4 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -52,6 +52,7 @@ ramstage-y += devapc.c ramstage-y += ufs.c ramstage-y += mcupm.c +ramstage-y += ../common/mtlib.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie94001bbda25fe015f43172e92a1006e059de223 Gerrit-Change-Number: 46930 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

4 41

Change in coreboot[master]: mb/google/hatch: Drop use of SPD cache for puff-based variants
by Matt DeVillier (Code Review) 10 Dec '20

10 Dec '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47899 ) Change subject: mb/google/hatch: Drop use of SPD cache for puff-based variants ...................................................................... mb/google/hatch: Drop use of SPD cache for puff-based variants Commit 74109923 [mb/google/puff: add a region to cache SPD data] implemented a mechanism to cache SODIMM SPD data in a FMAP region, but it's actually slower than simply letting FSP (vs coreboot) read the SPD data via smbus, so drop it. This has the side effect of removing the requirement for a RW_SPD_CACHE FMAP region, without which these boards would not boot at all - allowing the default FMAP to be used for non-ChromeOS builds. Test: build/boot WYVERN variant, check boot times via cbmem: w/SPD caching: ~722 ms w/FSP reading: ~627 ms Change-Id: I4e4db9ba9fdb0fa9fafb2645819b111d381b5756 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/hatch/romstage_spd_smbus.c 1 file changed, 5 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47899/1 diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index e697379..1db9c54 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -1,72 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> -#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> -#include <spd_bin.h> -#include <spd_cache.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; variant_memory_params(&memcfg); - /* Read spd block to get memory config */ - struct spd_block blk = { - .addr_map = { 0x50, 0x52, }, - }; - - uint8_t *spd_cache; - size_t spd_cache_sz; - bool need_update_cache = false; - bool dimm_changed = true; - - /* load spd cache from RW_SPD_CACHE */ - if (load_spd_cache(&spd_cache, &spd_cache_sz) == CB_SUCCESS) { - if (!spd_cache_is_valid(spd_cache, spd_cache_sz)) { - printk(BIOS_WARNING, "Invalid SPD cache\n"); - } else { - dimm_changed = check_if_dimm_changed(spd_cache, &blk); - if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != NULL) { - /* Set mrc_cache as invalid */ - printk(BIOS_INFO, "Set mrc_cache as invalid\n"); - memupd->FspmArchUpd.NvsBufferPtr = NULL; - } - } - need_update_cache = true; - } - - if (!dimm_changed) { - spd_fill_from_cache(spd_cache, &blk); - } else { - /* Access memory info through SMBUS. */ - get_spd_smbus(&blk); - - if (need_update_cache && update_spd_cache(&blk) == CB_ERR) - printk(BIOS_WARNING, "update SPD cache failed\n"); - } - - if (blk.spd_array[0] == NULL) { - memcfg.spd[0].read_type = NOT_EXISTING; - } else { - memcfg.spd[0].read_type = READ_SPD_MEMPTR; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; - } - + /* DDR4 SODIMMs located at CH0D0, CH1D0 */ + memcfg.spd[0].read_type = READ_SMBUS; + memcfg.spd[0].spd_spec.spd_smbus_address = 0xa0; memcfg.spd[1].read_type = NOT_EXISTING; - - if (blk.spd_array[1] == NULL) { - memcfg.spd[2].read_type = NOT_EXISTING; - } else { - memcfg.spd[2].read_type = READ_SPD_MEMPTR; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1]; - } - + memcfg.spd[2].read_type = READ_SMBUS; + memcfg.spd[2].spd_spec.spd_smbus_address = 0xa4; memcfg.spd[3].read_type = NOT_EXISTING; - dump_spd_info(&blk); /* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */ memcfg.vref_ca_config = 2; -- To view, visit https://review.coreboot.org/c/coreboot/+/47899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e4db9ba9fdb0fa9fafb2645819b111d381b5756 Gerrit-Change-Number: 47899 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpad
by Tim Chen (Code Review) 09 Dec '20

09 Dec '20

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47441 to review the following change. Change subject: mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpad ...................................................................... mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpad Add Elan and Synaptics touchpad settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/metaknight/overridetree.cb 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/47441/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 73ef0b8..8eb9570 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -43,7 +43,25 @@ }" device domain 0 on - device pci 15.0 on end + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end # I2C 0 device pci 15.2 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/47441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c Gerrit-Change-Number: 47441 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/google/dedede/var/metaknight: Add audio related settings
by Tim Chen (Code Review) 09 Dec '20

09 Dec '20

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47438 to review the following change. Change subject: mb/google/dedede/var/metaknight: Add audio related settings ...................................................................... mb/google/dedede/var/metaknight: Add audio related settings Add HDA,speaker codec and speaker amp settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: I9b1057eac94b568914f17fcccee58a0e403ccec0 Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/metaknight/overridetree.cb 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47438/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 25bc866..73ef0b8 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -80,5 +80,31 @@ end end # I2C 2 device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/47438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b1057eac94b568914f17fcccee58a0e403ccec0 Gerrit-Change-Number: 47438 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [WIP] mb/google/volteer: Use device aliases
by Duncan Laurie (Code Review) 09 Dec '20

09 Dec '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44039 ) Change subject: [WIP] mb/google/volteer: Use device aliases ...................................................................... [WIP] mb/google/volteer: Use device aliases Use the device aliases provided by tigerlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for volteer. Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb 2 files changed, 36 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44039/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 53bbe5a..80e2041 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -47,7 +47,6 @@ register "HeciEnabled" = "1" # FSP configuration - register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 @@ -286,10 +285,8 @@ }" device domain 0 on - #From EDS(575683) - device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y - device pci 02.0 on end # Graphics - device pci 04.0 on + device ref igpu on end + device ref dptf on # Default DPTF Policy for all Volteer boards if not overridden chip drivers/intel/dptf ## Active Policy @@ -379,81 +376,35 @@ device generic 0 on end end end # DPTF 0x9A03 - device pci 05.0 off end # IPU 0x9A19 - device pci 06.0 off end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 - device pci 08.0 on end # GNA 0x9A11 - device pci 09.0 off end # NPK 0x9A33 - device pci 0a.0 off end # Crash-log SRAM 0x9A0D - device pci 0d.0 on end # USB xHCI 0x9A13 - device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D - device pci 0e.0 off end # VMD 0x9A0B - - # From PCH EDS(576591) - device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 - device pci 10.6 off end # THC0 0xA0D0 - device pci 10.7 off end # THC1 0xA0D1 - - device pci 12.0 off end # SensorHUB 0xA0FC - device pci 12.6 off end # GSPI2 0x34FB - - device pci 13.0 off end # GSPI3 0xA0FD - - device pci 14.0 on end # USB3.1 xHCI 0xA0ED - device pci 14.1 off end # USB3.1 xDCI 0xA0EE - device pci 14.2 on end # Shared RAM 0xA0EF + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref gna on end + device ref north_xhci on end + device ref tbt_dma0 on end + device ref cnvi_bt on end + device ref south_xhci on end + device ref shared_ram on end chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + device ref cnvi_wifi on end end - device pci 15.0 on end # I2C #0 0xA0E8 - device pci 15.1 on end # I2C1 0xA0E9 - device pci 15.2 on end # I2C2 0xA0EA - device pci 15.3 on end # I2C3 0xA0EB - - device pci 16.0 on end # HECI1 0xA0E0 - device pci 16.1 off end # HECI2 0xA0E1 - device pci 16.2 off end # CSME 0xA0E2 - device pci 16.3 off end # CSME 0xA0E3 - device pci 16.4 off end # HECI3 0xA0E4 - device pci 16.5 off end # HECI4 0xA0E5 - - device pci 17.0 on end # SATA 0xA0D3 - - device pci 19.0 on end # I2C4 0xA0C5 - device pci 19.1 on end # I2C5 0xA0C6 - device pci 19.2 off end # UART2 0xA0C7 - - device pci 1c.0 on end # RP1 0xA0B8 - device pci 1c.1 off end # RP2 0xA0B9 - device pci 1c.2 off end # RP3 0xA0BA - device pci 1c.3 off end # RP4 0xA0BB - device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 off end # WWAN RP6 0xA0BD - device pci 1c.6 on end # RP7 0xA0BE - device pci 1c.7 on end # SD Card RP8 0xA0BF - - device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 on end # RP11 0xA0B2 - device pci 1d.3 off end # RP12 0xA0B3 - - device pci 1e.0 on end # UART0 0xA0A8 - device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 on + device ref heci1 on end + device ref sata on end + device ref pcie_rp1 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp11 on end + device ref uart0 on end + device ref gspi0 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" device spi 0 on end end - end # GSPI0 0xA0AA - device pci 1e.3 on + end + device ref gspi1 on chip drivers/spi/acpi register "name" = ""CRFP"" register "hid" = "ACPI_DT_NAMESPACE_HID" @@ -462,18 +413,12 @@ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" device spi 0 on end end # FPMCU - end # GSPI1 0xA0AB - device pci 1f.0 on + end + device ref pch_espi on chip ec/google/chromeec device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F - device pci 1f.1 off end # P2SB 0xA0A0 - device pci 1f.2 hidden end # PMC 0xA0A1 - device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF - device pci 1f.4 off end # SMBus 0xA0A3 - device pci 1f.5 on end # SPI 0xA0A4 - device pci 1f.6 off end # GbE 0x15E1/0x15E2 - device pci 1f.7 off end # TH 0xA0A6 + end + device ref hda on end end end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index c7350cb..8c95956 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -44,7 +44,7 @@ }, }" device domain 0 on - device pci 15.0 on + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -81,7 +81,7 @@ end end end - device pci 15.1 on + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -124,8 +124,8 @@ register "key.label" = ""pen_eject"" device generic 0 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -156,8 +156,8 @@ register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -166,8 +166,8 @@ register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on + end + device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" @@ -197,7 +197,7 @@ end end end - device pci 1f.2 hidden + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -230,6 +230,6 @@ end end end - end # PMC + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/44039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662 Gerrit-Change-Number: 44039 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/deltaur: Restrict RW_DIAG to lower 16MiB
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48190 ) Change subject: mb/google/deltaur: Restrict RW_DIAG to lower 16MiB ...................................................................... mb/google/deltaur: Restrict RW_DIAG to lower 16MiB This change restricts RW_DIAG region to lower 16MiB to ensure that the extended BIOS checker for FMAP does not complain about 16MiB boundary crossing. I haven't updated any other regions to occupy the newly freed space but it is fine since this board is dead and should be dropped from coreboot soon. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3 --- M src/mainboard/google/deltaur/chromeos.fmd 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/48190/1 diff --git a/src/mainboard/google/deltaur/chromeos.fmd b/src/mainboard/google/deltaur/chromeos.fmd index bbec112..a84a448 100644 --- a/src/mainboard/google/deltaur/chromeos.fmd +++ b/src/mainboard/google/deltaur/chromeos.fmd @@ -6,9 +6,9 @@ SI_PDR(PRESERVE)@0x602000 0x4000 } SI_BIOS@0x606000 0x19fa000 { - RW_DIAG@0x0 0x10ca000 { - RW_LEGACY(CBFS)@0x0 0x10ba000 - DIAG_NVRAM@0x10ba000 0x10000 + RW_DIAG@0x0 0x9fa000 { + RW_LEGACY(CBFS)@0x0 0x9ea000 + DIAG_NVRAM@0x9ea000 0x10000 } RW_SECTION_A@0x10ca000 0x280000 { VBLOCK_A@0x0 0x10000 -- To view, visit https://review.coreboot.org/c/coreboot/+/48190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3 Gerrit-Change-Number: 48190 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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