coreboot-gerrit November 2020

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Change in coreboot[master]: mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48189 ) Change subject: mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB ...................................................................... mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB This change restricts SI_ME region to live below the 16MiB boundary to ensure that no regions cross the 16MiB boundary as the extended BIOS window checker for FMAP complains about it. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9 --- M src/mainboard/intel/tglrvp/chromeos.fmd 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/48189/1 diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd index bfbd304..1e2e792 100644 --- a/src/mainboard/intel/tglrvp/chromeos.fmd +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -1,8 +1,8 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1081000 { + SI_ALL@0x0 0x1000000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x1000000 + SI_ME@0x81000 } SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/48189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9 Gerrit-Change-Number: 48189 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/fast_spi: Add Lockdown of extended BIOS region
by Srinidhi N Kaushik (Code Review) 08 Dec '20

08 Dec '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48068 ) Change subject: soc/intel/common/fast_spi: Add Lockdown of extended BIOS region ...................................................................... soc/intel/common/fast_spi: Add Lockdown of extended BIOS region This change adds support to Lock down the configuration of extended BIOS region. This is done as part of fast_spi_lockdown_cfg() so that it is consistent with the other lockdown. Change includes: 1. New helper function fast_spi_lock_ext_bios_cfg() added that will basically set EXT_BIOS_LOCK. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I730fc12a9c5ca8bb4a1f946cad45944dda8e0518 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h M src/soc/intel/common/pch/lockdown/lockdown.c 4 files changed, 21 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48068/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index e4d23a6..d4e6230 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -64,7 +64,7 @@ /* * Set FAST_SPIBAR BIOS Control register based on input bit field. */ -static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit) +static void fast_spi_set_bios_control_reg(uint32_t bios_cntl_bit) { #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_SPI; @@ -74,9 +74,9 @@ uint8_t bc_cntl; assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0); - bc_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); + bc_cntl = pci_read_config32(dev, SPIBAR_BIOS_CONTROL); bc_cntl |= bios_cntl_bit; - pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bc_cntl); + pci_write_config32(dev, SPIBAR_BIOS_CONTROL, bc_cntl); } /* @@ -108,6 +108,16 @@ } /* + * Set FAST_SPIBAR BIOS Control EXT BIOS LE bit. + */ +void fast_spi_set_ext_bios_lock_enable(void) +{ + fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE); + + fast_spi_read_post_write(SPIBAR_BIOS_CONTROL); +} + +/* * Set FAST_SPIBAR BIOS Control EISS bit. */ void fast_spi_set_eiss(void) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index f1c0f1e..9784797 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -14,6 +14,7 @@ /* Bit definitions for BIOS_CONTROL */ #define SPIBAR_BIOS_CONTROL_WPD (1 << 0) #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1) +#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE (1 << 28) #define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) #define SPIBAR_BIOS_CONTROL_EISS (1 << 5) diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 58bf25b..729690a 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -23,6 +23,10 @@ */ void fast_spi_set_lock_enable(void); /* + * Set FAST_SPIBAR BIOS Control Ext Bios LE bit. + */ +void fast_spi_set_ext_bios_lock_enable(void); +/* * Set FAST_SPIBAR BIOS Control EISS bit. */ void fast_spi_set_eiss(void); diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 906f8b0..b10306e 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -63,6 +63,9 @@ /* BIOS Lock */ fast_spi_set_lock_enable(); + + /* EXT BIOS Lock */ + fast_spi_set_ext_bios_lock_enable(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I730fc12a9c5ca8bb4a1f946cad45944dda8e0518 Gerrit-Change-Number: 48068 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/fast_spi: Add support for configuring MTRRs
by Srinidhi N Kaushik (Code Review) 08 Dec '20

08 Dec '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47991 ) Change subject: soc/intel/common/fast_spi: Add support for configuring MTRRs ...................................................................... soc/intel/common/fast_spi: Add support for configuring MTRRs This change enables caching for extended BIOS region. Currently, caching is enabled for the standard BIOS region upto a maximum of 16MiB using fast_spi_cache_bios_region, used the same function to add the support for caching for extended BIOS region as well. Changes include: 1. Add a new helper function fast_spi_cache_ext_bios_region() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 2. Make a call to fast_spi_cache_ext_bios_region() from fast_spi_cache_bios_region (). 3. If the extended window is used, then it enables caching for this window similar to how it is done for the standard window. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I9711f110a35a167efe3a4c912cf46c63c0812779 --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/47991/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index a3ec0d7..d5c6218 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -213,6 +213,40 @@ return bios_start; } +static void fast_spi_cache_ext_bios_window(void) +{ + + size_t ext_bios_size; + uint32_t alignment; + uintptr_t ext_bios_base; + const int type = MTRR_TYPE_WRPROT; + + if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)) + return; + + fast_spi_get_ext_bios_window(&ext_bios_base, &ext_bios_size); + + /* Enable extended bios only if Size of Bios region is greater than 16MiB */ + if (ext_bios_size == 0 || ext_bios_base == 0) + return; + + /* Round to power of two */ + alignment = 1UL << (log2_ceil(ext_bios_size)); + ext_bios_size = ALIGN_UP(ext_bios_size, alignment); + ext_bios_base = ALIGN_DOWN(ext_bios_base, ext_bios_size); + + if (ENV_PAYLOAD_LOADER) { + mtrr_use_temp_range(ext_bios_base, ext_bios_size, type); + } else { + int mtrr = get_free_var_mtrr(); + + if (mtrr == -1) + return; + + set_var_mtrr(mtrr, ext_bios_base, ext_bios_size, type); + } +} + void fast_spi_cache_bios_region(void) { size_t bios_size; @@ -246,6 +280,9 @@ set_var_mtrr(mtrr, base, bios_size, type); } + + /* Check if caching is needed for extended bios region if supported */ + fast_spi_cache_ext_bios_window(); } /* Enable extended bios support -- To view, visit https://review.coreboot.org/c/coreboot/+/47991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9711f110a35a167efe3a4c912cf46c63c0812779 Gerrit-Change-Number: 47991 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/tigerlake: Add SPI DMI Destination ID
by Srinidhi N Kaushik (Code Review) 08 Dec '20

08 Dec '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47989 ) Change subject: src/soc/intel/tigerlake: Add SPI DMI Destination ID ...................................................................... src/soc/intel/tigerlake: Add SPI DMI Destination ID This change adds the SPI-DMI Destination ID for tigerlake soc. This is needed for enabling support for extended BIOS region. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I0b6a8af0c1e79fa668ef2f84b93f3bbece59eb6a --- M src/soc/intel/tigerlake/include/soc/pcr_ids.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/47989/1 diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h index 7388593..319558a 100644 --- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h +++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h @@ -31,4 +31,9 @@ #define PID_ESPI 0xc7 #define PID_SERIALIO 0xcb +/* + * SPI - DMI Destination ID + */ +#define SPI_DMI_DESTINATION_ID 0x23a8 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b6a8af0c1e79fa668ef2f84b93f3bbece59eb6a Gerrit-Change-Number: 47989 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/common/fast_spi: Add extended decode window support
by Srinidhi N Kaushik (Code Review) 08 Dec '20

08 Dec '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47990 ) Change subject: soc/intel/common/fast_spi: Add extended decode window support ...................................................................... soc/intel/common/fast_spi: Add extended decode window support This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init(). Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h 2 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47990/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 4190253..a3ec0d7 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -7,9 +7,11 @@ #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <fast_spi_def.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <lib.h> #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #include <spi_flash.h> #include <spi-generic.h> @@ -246,6 +248,43 @@ } } +/* Enable extended bios support + * Checks BIOS region in the flashmap, if its more than 16Mib, enables extended BIOS + * region support. + */ +static void fast_spi_enable_ext_bios(void) +{ +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif + + size_t ext_bios_size; + uintptr_t ext_bios_base; + + if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)) + return; + + fast_spi_get_ext_bios_window(&ext_bios_base, &ext_bios_size); + + /* Enable extended biod only if Size of Bios region is greater than 16MiB */ + if (ext_bios_size == 0 || ext_bios_base == 0) + return; + + /* Program EXT_BIOS_BAR1 with obtained ext_bios_base */ + pci_write_config32(dev, SPI_CFG_BAR1, ext_bios_base | PCI_BASE_ADDRESS_SPACE_MEMORY); + + /* Program obtained ext_bios_size in SPI_BAR_CONTROL */ + pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(16 * MiB)); + /* Program EXT_BIOS EN */ + pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE); + + /* Confgiure DMI Source decode for Extended BIOS Region */ + dmi_enable_gpmr(ext_bios_base, ext_bios_size, SPI_DMI_DESTINATION_ID); + +} + /* * Program temporary BAR for SPI in case any of the stages before ramstage need * to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI @@ -270,6 +309,9 @@ pci_write_config32(dev, PCI_BASE_ADDRESS_0, spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY); + /* Enable extended bios support */ + fast_spi_enable_ext_bios(); + /* Enable Bus Master and MMIO Space */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index bafe131..0dd4ca6 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -8,6 +8,9 @@ #define SPIDVID_OFFSET 0x0 #define SPIBAR_BIOS_CONTROL 0xdc +/* Extended Bios Support Registers */ +#define SPI_CFG_BAR1 0xe0 /* SPI BAR1 MMIO */ + /* Bit definitions for BIOS_CONTROL */ #define SPIBAR_BIOS_CONTROL_WPD (1 << 0) #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1) @@ -15,6 +18,8 @@ #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) #define SPIBAR_BIOS_CONTROL_EISS (1 << 5) #define SPIBAR_BIOS_CONTROL_BILD (1 << 7) +#define SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE BIT(27) +#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff)) /* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 Gerrit-Change-Number: 47990 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/dmi: Add DMI driver support
by Srinidhi N Kaushik (Code Review) 08 Dec '20

08 Dec '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47988 ) Change subject: soc/intel/common/dmi: Add DMI driver support ...................................................................... soc/intel/common/dmi: Add DMI driver support This is change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding of extended BIOS region in DMI. This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers. It can ensure that the PCR base address is configured and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 2. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 --- A src/soc/intel/common/block/dmi/Kconfig A src/soc/intel/common/block/dmi/Makefile.inc A src/soc/intel/common/block/dmi/dmi.c A src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/Kconfig 5 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47988/1 diff --git a/src/soc/intel/common/block/dmi/Kconfig b/src/soc/intel/common/block/dmi/Kconfig new file mode 100644 index 0000000..2cc4646 --- /dev/null +++ b/src/soc/intel/common/block/dmi/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_DMI + bool + select SOC_INTEL_COMMON_BLOCK_PCR + help + Intel Processor common DMI support diff --git a/src/soc/intel/common/block/dmi/Makefile.inc b/src/soc/intel/common/block/dmi/Makefile.inc new file mode 100644 index 0000000..99a1c18 --- /dev/null +++ b/src/soc/intel/common/block/dmi/Makefile.inc @@ -0,0 +1,10 @@ +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y) + +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c + +endif diff --git a/src/soc/intel/common/block/dmi/dmi.c b/src/soc/intel/common/block/dmi/dmi.c new file mode 100644 index 0000000..eac86e8 --- /dev/null +++ b/src/soc/intel/common/block/dmi/dmi.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <intelblocks/dmi.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> + +#define MAX_GPMR_REGS 2 /* 3 GPMR registers */ +#define GPMR_OFFSET(x) (0x277c + (x)*8) +#define GPMR_DID_OFFSET(x) (0x2780 + (x)*8) +#define DMI_PCR_GPMR_BASE_SHIFT 16 +#define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 +#define DMI_PCR_GPMR_BASE_MASK 0xffff +#define DMI_PCR_GPMR_EN BIT(31) + +/* GPMR Register read given offset */ +static uint32_t gpmr_read32(uint16_t offset) +{ + return pcr_read32(PID_DMI, offset); +} + +/* GPMR Register write given offset and val */ +static void gpmr_write32(uint16_t offset, uint32_t val) +{ + return pcr_write32(PID_DMI, offset, val); +} + +/* Check for available free gpmr */ +static uint32_t get_available_gpmr(void) +{ + int i; + uint32_t val; + + for (i = 0; i <= MAX_GPMR_REGS; i++) { + val = gpmr_read32(GPMR_DID_OFFSET(i)); + if (!(val & DMI_PCR_GPMR_EN)) + return i; + } + printk(BIOS_ERR, "get_available_gpmr: No available free gpmr found \n"); + return -1; +} + +/* Configure GPMR for the given base and size of extended BIOS Region */ +void dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) +{ + uint32_t gpmr_num; + + /* Get available free GPMR */ + gpmr_num = get_available_gpmr(); + + /* Program Range for the given decode window */ + gpmr_write32(GPMR_OFFSET(gpmr_num), + (size & DMI_PCR_GPMR_LIMIT_MASK) | + ((base >> DMI_PCR_GPMR_BASE_SHIFT) & DMI_PCR_GPMR_BASE_MASK)); + + /* Program source decode enable bit and the Destination ID */ + gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | DMI_PCR_GPMR_EN); +} diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h new file mode 100644 index 0000000..629d1a6 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_DMI_H +#define SOC_INTEL_COMMON_BLOCK_DMI_H + +#include <types.h> + +/* + * Takes base, size and destination ID and configures the GPMR + * for accessing the region. + */ +void dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id); + +#endif /* SOC_INTEL_COMMON_BLOCK_DMI_H */ diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index cca65d6..b00fc8b 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -19,6 +19,7 @@ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP + select SOC_INTEL_COMMON_BLOCK_DMI select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG -- To view, visit https://review.coreboot.org/c/coreboot/+/47988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 Gerrit-Change-Number: 47988 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

5 28

Change in coreboot[master]: coreboot tables: Add SPI flash memory map windows to coreboot tables
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48185 ) Change subject: coreboot tables: Add SPI flash memory map windows to coreboot tables ...................................................................... coreboot tables: Add SPI flash memory map windows to coreboot tables This change adds details about the memory map windows to translate addresses between SPI flash space and host address space to coreboot tables. This is useful for payloads to setup the translation using the decode windows already known to coreboot. Until now, there was a single decode window at the top of 4G used by all x86 platforms. However, going forward, platforms might support more decode windows and hence in order to avoid duplication in payloads this information is filled in coreboot tables. `lb_spi_flash()` is updated to fill in the details about these windows by making a call to `spi_flash_get_mmap_windows()` which is implemented by the driver providing the boot media mapping device. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I00ae33d9b53fecd0a8eadd22531fdff8bde9ee94 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/arch/x86/mmap_boot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/spi/spi_flash.c M src/include/spi_flash.h M src/soc/intel/apollolake/mmap_boot.c M src/soc/intel/common/block/fast_spi/mmap_boot.c 9 files changed, 101 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/48185/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 64db83b..e042a90 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -261,12 +261,25 @@ uint32_t index; }; +/* Memory map windows to translate addresses between SPI flash space and host address space. */ +struct flash_mmap_window { + uint32_t flash_base; + uint32_t host_base; + uint32_t size; +}; + struct cb_spi_flash { uint32_t tag; uint32_t size; uint32_t flash_size; uint32_t sector_size; uint32_t erase_cmd; + /* + * Number of mmap windows used by the platform to decode addresses between SPI flash + * space and host address space. This determines the number of entries in mmap_table. + */ + uint32_t mmap_count; + struct flash_mmap_window mmap_table[0]; }; struct cb_boot_media_params { diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index dd739ab..5a24e14 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -40,6 +40,9 @@ /* Up to 10 MAC addresses */ #define SYSINFO_MAX_MACS 10 +/* Maximum of 2 MMAP windows for decoding SPI flash. */ +#define SYSINFO_MAX_MMAP_WINDOWS 2 + #include <coreboot_tables.h> /* @@ -126,6 +129,8 @@ uint32_t size; uint32_t sector_size; uint32_t erase_cmd; + uint32_t mmap_window_count; + struct flash_mmap_window mmap_table[SYSINFO_MAX_MMAP_WINDOWS]; } spi_flash; uint64_t fmap_offset; uint64_t cbfs_offset; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index b7d2a53..7e23afe 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -211,6 +211,13 @@ info->spi_flash.size = flash->flash_size; info->spi_flash.sector_size = flash->sector_size; info->spi_flash.erase_cmd = flash->erase_cmd; + + if (flash->mmap_count == 0) + return; + + info->spi_flash.mmap_window_count = MIN(flash->mmap_count, SYSINFO_MAX_MMAP_WINDOWS); + memcpy(info->spi_flash.mmap_table, flash->mmap_table, + info->spi_flash.mmap_window_count * sizeof(struct flash_mmap_window)); } static void cb_parse_boot_media_params(unsigned char *ptr, diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index 66ba0e1..f0ccc86 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -2,6 +2,7 @@ #include <boot_device.h> #include <endian.h> +#include <spi_flash.h> /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE)) @@ -13,3 +14,12 @@ { return &boot_dev.rdev; } + +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table) +{ + table->flash_base = 0; + table->host_base = (uint32_t)(uintptr_t)rom_base; + table->size = CONFIG_ROM_SIZE; + + return 1; +} diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 3e74e6b..c740975 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -349,12 +349,26 @@ uint32_t index; }; +/* Memory map windows to translate addresses between SPI flash space and host address space. */ +struct flash_mmap_window { + uint32_t flash_base; + uint32_t host_base; + uint32_t size; +}; + struct lb_spi_flash { uint32_t tag; uint32_t size; uint32_t flash_size; uint32_t sector_size; uint32_t erase_cmd; + /* + * Number of mmap windows used by the platform to decode addresses between SPI flash + * space and host address space. This determines the number of entries in mmap_table. + */ + + uint32_t mmap_count; + struct flash_mmap_window mmap_table[0]; }; struct lb_boot_media_params { diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index f2610a1..2406a90 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -663,6 +663,14 @@ flash->sector_size = 64 * KiB; flash->erase_cmd = CMD_BLOCK_ERASE; } + + if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { + flash->mmap_count = 0; + } else { + struct flash_mmap_window *table = (struct flash_mmap_window *)(flash + 1); + flash->mmap_count = spi_flash_get_mmap_windows(table); + flash->size += flash->mmap_count * sizeof(*table); + } } int spi_flash_ctrlr_protect_region(const struct spi_flash *flash, diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 1061e99..a7f707e 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -225,4 +225,12 @@ int (*func)(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin)); +/* + * Fill in the memory mapped windows used by the SPI flash device. This is useful for payloads + * to identify SPI flash to host space mapping. + * + * Returns number of windows added to the table. + */ +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table); + #endif /* _SPI_FLASH_H_ */ diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 4ced6ba..b103e7c 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <fmap.h> #include <intelblocks/fast_spi.h> +#include <spi_flash.h> /* * BIOS region on the flash is mapped right below 4GiB in the address @@ -98,3 +99,14 @@ return &real_dev.rdev; } + +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table) +{ + bios_mmap_init(); + + table->flash_base = region_offset(&real_dev_window.sub_region); + table->host_base = (uintptr_t)rdev_mmap_full(&shadow_dev.rdev); + table->size = region_sz(&real_dev_window.sub_region); + + return 1; +} diff --git a/src/soc/intel/common/block/fast_spi/mmap_boot.c b/src/soc/intel/common/block/fast_spi/mmap_boot.c index a415cbd..9d0cc04 100644 --- a/src/soc/intel/common/block/fast_spi/mmap_boot.c +++ b/src/soc/intel/common/block/fast_spi/mmap_boot.c @@ -4,6 +4,7 @@ #include <commonlib/region.h> #include <fmap.h> #include <intelblocks/fast_spi.h> +#include <spi_flash.h> enum window_type { /* Fixed decode window of max 16MiB size just below 4G boundary */ @@ -151,3 +152,26 @@ *base = (uintptr_t)rdev_mmap_full(rd); } } + +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table) +{ + int i; + uint32_t count = 0; + + bios_mmap_init(); + + for (i = 0; i < TOTAL_DECODE_WINDOWS; i++) { + + if (region_sz(&real_dev_windows[i].sub_region) == 0) + continue; + + count++; + table->flash_base = region_offset(&real_dev_windows[i].sub_region); + table->host_base = (uintptr_t)rdev_mmap_full(&shadow_devs[i].rdev); + table->size = region_sz(&real_dev_windows[i].sub_region); + + table++; + } + + return count; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ae33d9b53fecd0a8eadd22531fdff8bde9ee94 Gerrit-Change-Number: 48185 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/common/systemagent: Reserve window used for extended BIOS d...
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48184 ) Change subject: soc/intel/common/systemagent: Reserve window used for extended BIOS decoding ...................................................................... soc/intel/common/systemagent: Reserve window used for extended BIOS decoding This change reserves the window used for extended BIOS decoding as a fixed MMIO resource using read_resources callback in systemagent driver. This ensures that the resource allocator does not allocate from this window. Additionally, this window is also marked as fixed memory region in _CRS for PNP0C02 device. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I42b5a0ebda2627f72b825551c566cd22dbc5cca7 --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/systemagent/systemagent.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/48184/1 diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index b4b7465..5780f4c 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -276,6 +276,11 @@ /* FLASH range */ Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) +#if CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW) + /* Extended BIOS window */ + Memory32Fixed (ReadOnly, CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE) +#endif + /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 4c5731f..6b039e1 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -287,6 +287,11 @@ if (CONFIG(SA_ENABLE_IMR)) /* Add the isolated memory ranges (IMRs). */ sa_add_imr_resources(dev, &index); + + /* Reserve the window used for extended BIOS decoding. */ + if (CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)) + mmio_resource(dev, index++, CONFIG_EXT_BIOS_WIN_BASE / KiB, + CONFIG_EXT_BIOS_WIN_SIZE / KiB); } void enable_power_aware_intr(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/48184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42b5a0ebda2627f72b825551c566cd22dbc5cca7 Gerrit-Change-Number: 48184 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: fast spi multiple bios region windows
by Furquan Shaikh (Code Review) 08 Dec '20

08 Dec '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47659 ) Change subject: fast spi multiple bios region windows ...................................................................... fast spi multiple bios region windows Change-Id: I1b564aed9809cf14b40a3b8e907622266fc782e2 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/fast_spi/Kconfig M src/soc/intel/common/block/fast_spi/Makefile.inc A src/soc/intel/common/block/fast_spi/mmap_boot.c M src/soc/intel/tigerlake/Kconfig 4 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47659/1 diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig index 9369272..8724ca4 100644 --- a/src/soc/intel/common/block/fast_spi/Kconfig +++ b/src/soc/intel/common/block/fast_spi/Kconfig @@ -11,3 +11,13 @@ default y help Disable the write status SPI opcode in Intel Fast SPI block. + +config FAST_SPI_SUPPORTS_MULTIPLE_BIOS_WINDOWS + bool + depends on SOC_INTEL_COMMON_BLOCK_FAST_SPI + help + SoC has support for multiple BIOS region windows. + +config X86_TOP4G_BOOTMEDIA_MAP + bool + default n if FAST_SPI_SUPPORTS_MULTIPLE_BIOS_WINDOWS diff --git a/src/soc/intel/common/block/fast_spi/Makefile.inc b/src/soc/intel/common/block/fast_spi/Makefile.inc index e5b50aa..aa69b72 100644 --- a/src/soc/intel/common/block/fast_spi/Makefile.inc +++ b/src/soc/intel/common/block/fast_spi/Makefile.inc @@ -19,3 +19,10 @@ endif CPPFLAGS_common += -I$(src)/soc/intel/common/block/fast_spi + +bootblock-$(CONFIG_FAST_SPI_SUPPORTS_MULTIPLE_BIOS_WINDOWS) += mmap_boot.c +romstage-$(CONFIG_FAST_SPI_SUPPORTS_MULTIPLE_BIOS_WINDOWS) += mmap_boot.c +verstage-$(CONFIG_FAST_SPI_SUPPORTS_MULTIPLE_BIOS_WINDOWS) += mmap_boot.c +ramstage-$(CONFIG_FAST_SPI_SUPPORTS_MULTIPLE_BIOS_WINDOWS) += mmap_boot.c +postcar-$(CONFIG_FAST_SPI_SUPPORTS_MULTIPLE_BIOS_WINDOWS) += mmap_boot.c +smm-$(CONFIG_FAST_SPI_SUPPORTS_MULTIPLE_BIOS_WINDOWS) += mmap_boot.c \ No newline at end of file diff --git a/src/soc/intel/common/block/fast_spi/mmap_boot.c b/src/soc/intel/common/block/fast_spi/mmap_boot.c new file mode 100644 index 0000000..4bc8531 --- /dev/null +++ b/src/soc/intel/common/block/fast_spi/mmap_boot.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boot_device.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <fmap.h> +#include <intelblocks/fast_spi.h> + +static size_t bios_size; + +static struct xlate_region_device real_dev; +static struct mem_region_device shadow_devs[2]; +static struct xlate_window real_dev_windows[2]; + +static void bios_mmap_init(void) +{ + size_t size, start; + uintptr_t std_window_base; + size_t std_window_size; + uintptr_t ext_window_base; + size_t ext_window_size; + size_t window_count = 0; + + if (bios_size != 0) + return; + + start = fast_spi_get_bios_region(&size); + + std_window_size = MIN(16 * MiB, size); + std_window_base = 4ULL * GiB - std_window_size; + + mem_region_device_ro_init(&shadow_devs[0], (void *)std_window_base, std_window_size); + real_dev_windows[0].access_dev = &shadow_devs[0].rdev; + real_dev_windows[0].sub_region.offset = start + size - std_window_size; + real_dev_windows[0].sub_region.size = std_window_size; + window_count++; + + ext_window_size = size - std_window_size; + ext_window_base = 0xF8000000; + + if (ext_window_size) { + mem_region_device_ro_init(&shadow_devs[1], (void *)ext_window_base, ext_window_size); + real_dev_windows[1].access_dev = &shadow_devs[1].rdev; + real_dev_windows[1].sub_region.offset = start; + real_dev_windows[1].sub_region.size = ext_window_size; + window_count++; + } + + xlate_region_device_ro_init(&real_dev, window_count, real_dev_windows, CONFIG_ROM_SIZE); + bios_size = size; +} + +const struct region_device *boot_device_ro(void) +{ + bios_mmap_init(); + + return &real_dev.rdev; +} diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 507f871..5a338bd 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -15,6 +15,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select DRIVERS_USB_ACPI + select FAST_SPI_SUPPORTS_MULTIPLE_BIOS_WINDOWS select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b564aed9809cf14b40a3b8e907622266fc782e2 Gerrit-Change-Number: 47659 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 36

Change in coreboot[master]: mb/google/volteer/variant/lindar: Add PMC.MUX.CONx device configurati...
by Stanley Wu (Code Review) 08 Dec '20

08 Dec '20

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47434 ) Change subject: mb/google/volteer/variant/lindar: Add PMC.MUX.CONx device configuration for lindar ...................................................................... mb/google/volteer/variant/lindar: Add PMC.MUX.CONx device configuration for lindar This patch adds the PMC MUX and CONx devices for lindar. Device specific method contains the port and orientation details used to configure the mux. BUG=b:172533907 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS. Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c --- M src/mainboard/google/volteer/variants/lindar/overridetree.cb 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47434/1 diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 87ca0a3..182077c 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -71,6 +71,35 @@ device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end device ref north_xhci on chip drivers/usb/acpi device ref tcss_root_hub on -- To view, visit https://review.coreboot.org/c/coreboot/+/47434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c Gerrit-Change-Number: 47434 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020