coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/kukui: Fix no firmware beep issue
by Tao Xia (Code Review) 12 Dec '20

12 Dec '20

Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47586 ) Change subject: mb/google/kukui: Fix no firmware beep issue ...................................................................... mb/google/kukui: Fix no firmware beep issue There are no two beeps during the developer screen after changing from the normal mode to the developer mode. The RT1015 amplifier works with I2C mode on Kakadu. So the SCL6/SDA6 should be configured as I2C function instead of GPIO function. And the RT1015 amplifier initialization should be done through I2C6 interface. BUG=b:171763469 BRANCH=kukui TEST=There are two beeps during the developer screen after changing from the normal mode to the developer mode. Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: If07674d94a0b63ac3174d16d11bf371e0bd8c8cf --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/kukui/mainboard.c 3 files changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/47586/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index cff94da..358d445 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -17,6 +17,12 @@ select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_VBNV_FLASH +config RT1015_I2C_MODE + bool + default n + help + The platform that uses rt1015 I2C mode should select this option to enable it. + config BOARD_SPECIFIC_OPTIONS def_bool y select RTC @@ -37,6 +43,7 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE || BOARD_GOOGLE_KAKADU + select RT1015_I2C_MODE if BOARD_GOOGLE_KAKADU config MAINBOARD_DIR string diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index c5810d1..6fce1c3 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -25,7 +25,20 @@ {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"}, {GPIO_EN_SPK_AMP.id, ACTIVE_HIGH, -1, "speaker enable"}, }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); + + struct lb_gpio chromeos_gpios_1[] = { + {GPIO_WP.id, ACTIVE_LOW, + !get_write_protect_state(), "write protect"}, + {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, + {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"}, + {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + }; + + if (CONFIG(RT1015_I2C_MODE)) + lb_add_gpios(gpios, chromeos_gpios_1, ARRAY_SIZE(chromeos_gpios_1)); + else + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); + } int get_write_protect_state(void) diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 268b7ca..746b3af 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -18,6 +18,7 @@ #include <soc/mtcmos.h> #include <soc/spm.h> #include <soc/usb.h> +#include <soc/i2c.h> #include <string.h> #include "gpio.h" @@ -54,6 +55,9 @@ gpio_set_mode(GPIO(CAM_PDN1), PAD_CAM_PDN1_FUNC_I2S2_BCK); gpio_set_mode(GPIO(CAM_PDN0), PAD_CAM_PDN0_FUNC_I2S2_MCK); gpio_set_mode(GPIO(EINT3), PAD_EINT3_FUNC_I2S3_DO); + + if (CONFIG(RT1015_I2C_MODE)) + mtk_i2c_bus_init(6); } static void configure_ec(void) @@ -91,7 +95,7 @@ gpio_output(GPIO_PPVARN_LCD_EN, 1); gpio_output(GPIO_PP1800_LCM_EN, 1); gpio_output(GPIO_PP3300_LCM_EN, 1); - mdelay(6); + mdelay(15); gpio_output(GPIO_LCM_RST_1V8, 1); mdelay(6); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If07674d94a0b63ac3174d16d11bf371e0bd8c8cf Gerrit-Change-Number: 47586 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

3 20

Change in coreboot[master]: drivers/ipmi: Handle the condition when (dev->chip_info == NULL)
by Bill XIE (Code Review) 12 Dec '20

12 Dec '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47387 ) Change subject: drivers/ipmi: Handle the condition when (dev->chip_info == NULL) ...................................................................... drivers/ipmi: Handle the condition when (dev->chip_info == NULL) Some former commits (e.g. Ieb41771c75aae902191bba5d220796e6c343f8e0) blindly assume that dev->chip_info is capable to be dereferenced, making at least compilers complain about potential null pointer dereference. They might cause crash if truly (dev->chip_info == NULL). Their code should be adjusted to be runnable even if dev->chip_info is NULL. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I1d694b12f6c42961c104fe839d4ee46c0f111197 --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 14 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/47387/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 362f17a..3af44ef 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -77,8 +77,9 @@ struct ipmi_devid_rsp rsp; uint32_t man_id = 0, prod_id = 0; struct drivers_ipmi_config *conf = NULL; - struct ipmi_selftest_rsp selftestrsp; + struct ipmi_selftest_rsp selftestrsp = {{ 0, 0, 0 }, 0, 0}; uint8_t retry_count; + uint16_t bmc_boot_timeout = 0; if (!dev->enabled) return; @@ -90,8 +91,9 @@ /* Get IPMI version for ACPI and SMBIOS */ if (conf && conf->wait_for_bmc && conf->bmc_boot_timeout) { + bmc_boot_timeout = conf->bmc_boot_timeout; struct stopwatch sw; - stopwatch_init_msecs_expire(&sw, conf->bmc_boot_timeout * 1000); + stopwatch_init_msecs_expire(&sw, bmc_boot_timeout * 1000); printk(BIOS_INFO, "IPMI: Waiting for BMC...\n"); while (!stopwatch_expired(&sw)) { @@ -108,7 +110,7 @@ } printk(BIOS_INFO, "Get BMC self test result..."); - for (retry_count = 0; retry_count < conf->bmc_boot_timeout; retry_count++) { + for (retry_count = 0; retry_count < bmc_boot_timeout; retry_count++) { if (!ipmi_get_bmc_self_test_result(dev, &selftestrsp)) break; @@ -175,6 +177,7 @@ struct acpi_rsdp *rsdp) { struct drivers_ipmi_config *conf = NULL; + uint32_t uid = 0; struct acpi_spmi *spmi; s8 gpe_interrupt = -1; u32 apic_interrupt = 0; @@ -214,11 +217,12 @@ apic_interrupt = conf->apic_interrupt; } - /* Use command to get UID from ipmi_ssdt */ + if (uid_cnt > 0) + uid = uid_cnt - 1; acpi_create_ipmi(dev, spmi, (ipmi_revision_major << 8) | (ipmi_revision_minor << 4), &addr, IPMI_INTERFACE_KCS, gpe_interrupt, apic_interrupt, - conf->uid); + uid); acpi_add_table(rsdp, spmi); @@ -241,15 +245,12 @@ if (dev->chip_info) conf = dev->chip_info; - /* Use command to pass UID to ipmi_write_acpi_tables */ - conf->uid = uid_cnt++; - /* write SPMI device */ acpigen_write_scope(scope); acpigen_write_device("SPMI"); acpigen_write_name_string("_HID", "IPI0001"); acpigen_write_name_unicode("_STR", "IPMI_KCS"); - acpigen_write_name_byte("_UID", conf->uid); + acpigen_write_name_byte("_UID", uid_cnt); acpigen_write_STA(0xf); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); @@ -261,8 +262,12 @@ // FIXME: is that correct? if (conf->have_apic) acpigen_write_irq(1 << conf->apic_interrupt); + + conf->uid = uid_cnt; } + uid_cnt++; + acpigen_write_resourcetemplate_footer(); acpigen_write_method("_IFT", 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/47387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d694b12f6c42961c104fe839d4ee46c0f111197 Gerrit-Change-Number: 47387 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

4 12

Change in em100[master]: Update xz to upstream revision 090e6a0
by Stefan Reinauer (Code Review) 11 Dec '20

11 Dec '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47898 ) Change subject: Update xz to upstream revision 090e6a0 ...................................................................... Update xz to upstream revision 090e6a0 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I700e7f93d713d3c181125dd751ff84d74fd2efe2 --- M xz/README M xz/xz.h M xz/xz_crc32.c M xz/xz_crc64.c M xz/xz_dec_bcj.c M xz/xz_dec_lzma2.c M xz/xz_lzma2.h M xz/xz_stream.h 8 files changed, 28 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/98/47898/1 diff --git a/xz/README b/xz/README index 6cbf1f0..172e771 100644 --- a/xz/README +++ b/xz/README @@ -1 +1 @@ -These files are unmodified versions of xz-embedded 40d291b. +These files are unmodified versions of xz-embedded 090e6a0. diff --git a/xz/xz.h b/xz/xz.h index 0a4b38d..d24b94a 100644 --- a/xz/xz.h +++ b/xz/xz.h @@ -2,7 +2,7 @@ * XZ decompressor * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. @@ -32,7 +32,7 @@ * enum xz_mode - Operation mode * * @XZ_SINGLE: Single-call mode. This uses less RAM than - * than multi-call modes, because the LZMA2 + * multi-call modes, because the LZMA2 * dictionary doesn't need to be allocated as * part of the decoder state. All required data * structures are allocated at initialization, diff --git a/xz/xz_crc32.c b/xz/xz_crc32.c index 34532d1..5627b00 100644 --- a/xz/xz_crc32.c +++ b/xz/xz_crc32.c @@ -2,7 +2,7 @@ * CRC32 using the polynomial from IEEE-802.3 * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. diff --git a/xz/xz_crc64.c b/xz/xz_crc64.c index ca1caee..215e04d 100644 --- a/xz/xz_crc64.c +++ b/xz/xz_crc64.c @@ -4,7 +4,7 @@ * This file is similar to xz_crc32.c. See the comments there. * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. diff --git a/xz/xz_dec_bcj.c b/xz/xz_dec_bcj.c index a768e6d..72ddac6 100644 --- a/xz/xz_dec_bcj.c +++ b/xz/xz_dec_bcj.c @@ -2,7 +2,7 @@ * Branch/Call/Jump (BCJ) filter decoders * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. diff --git a/xz/xz_dec_lzma2.c b/xz/xz_dec_lzma2.c index 156f26f..2deb544 100644 --- a/xz/xz_dec_lzma2.c +++ b/xz/xz_dec_lzma2.c @@ -2,7 +2,7 @@ * LZMA2 decoder * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. @@ -387,7 +387,14 @@ *left -= copy_size; - memcpy(dict->buf + dict->pos, b->in + b->in_pos, copy_size); + /* + * If doing in-place decompression in single-call mode and the + * uncompressed size of the file is larger than the caller + * thought (i.e. it is invalid input!), the buffers below may + * overlap and cause undefined behavior with memcpy(). + * With valid inputs memcpy() would be fine here. + */ + memmove(dict->buf + dict->pos, b->in + b->in_pos, copy_size); dict->pos += copy_size; if (dict->full < dict->pos) @@ -397,7 +404,11 @@ if (dict->pos == dict->end) dict->pos = 0; - memcpy(b->out + b->out_pos, b->in + b->in_pos, + /* + * Like above but for multi-call mode: use memmove() + * to avoid undefined behavior with invalid input. + */ + memmove(b->out + b->out_pos, b->in + b->in_pos, copy_size); } @@ -421,6 +432,12 @@ if (dict->pos == dict->end) dict->pos = 0; + /* + * These buffers cannot overlap even if doing in-place + * decompression because in multi-call mode dict->buf + * has been allocated by us in this file; it's not + * provided by the caller like in single-call mode. + */ memcpy(b->out + b->out_pos, dict->buf + dict->start, copy_size); } diff --git a/xz/xz_lzma2.h b/xz/xz_lzma2.h index 071d67b..92d852d 100644 --- a/xz/xz_lzma2.h +++ b/xz/xz_lzma2.h @@ -2,7 +2,7 @@ * LZMA2 definitions * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. diff --git a/xz/xz_stream.h b/xz/xz_stream.h index 66cb5a7..430bb3a 100644 --- a/xz/xz_stream.h +++ b/xz/xz_stream.h @@ -19,7 +19,7 @@ /* * See the .xz file format specification at - * http://tukaani.org/xz/xz-file-format.txt + * https://tukaani.org/xz/xz-file-format.txt * to understand the container format. */ -- To view, visit https://review.coreboot.org/c/em100/+/47898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I700e7f93d713d3c181125dd751ff84d74fd2efe2 Gerrit-Change-Number: 47898 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: util/amdfwtool: Fix EFS generation polarity
by Marshall Dawson (Code Review) 11 Dec '20

11 Dec '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47769 ) Change subject: util/amdfwtool: Fix EFS generation polarity ...................................................................... util/amdfwtool: Fix EFS generation polarity The DWORD used to indicate the Embedded Firmware Structure's generation uses 1 to indicate a first-gen structure, e.g. a SPI device's erased value of 0xffffffff. A 0 in bit 0 is how Client PSPs will interpret the structure as designed for second-gen. This change and the original addition should have no effects on any current products as none interpret offset 0x24. BUG=b:158755102 TEST=inspect EFS in coreboot.rom Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd --- M util/amdfwtool/amdfwtool.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47769/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 9cf6a4f..36d669b 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -333,7 +333,7 @@ uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; - uint32_t second_gen_efs; + uint32_t second_gen_efs; /* Client SKUs b0=1 is Gen1, b1=0 is Gen2, Servers TBD */ uint32_t bios3_entry; uint32_t reserved_2Ch; uint32_t promontory_fw_ptr; @@ -1182,13 +1182,11 @@ } switch (soc_id) { case PLATFORM_STONEYRIDGE: - amd_romsig->second_gen_efs = 0; amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; break; case PLATFORM_RAVEN: case PLATFORM_PICASSO: - amd_romsig->second_gen_efs = 0; amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1205,7 +1203,7 @@ break; case PLATFORM_RENOIR: case PLATFORM_LUCIENNE: - amd_romsig->second_gen_efs = 1; + amd_romsig->second_gen_efs = 0xfffffffe; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; switch (efs_spi_micron_flag) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd Gerrit-Change-Number: 47769 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/google/volteer: Switch to fw_config_probe_nodefault when appropriate
by Tim Wawrzynczak (Code Review) 11 Dec '20

11 Dec '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47972 ) Change subject: mb/google/volteer: Switch to fw_config_probe_nodefault when appropriate ...................................................................... mb/google/volteer: Switch to fw_config_probe_nodefault when appropriate In cases when a volteer device is unprovisioned, the safest thing to do for GPIOs that will normally be used for audio codec buses is to leave them disabled (configured as PAD_CFG_NC). The same is true for USB4 support; if it is not know explicitly to be supported, then leave the iTBT PCIe RPs disabled. Change-Id: I8efd101174f6e3d7233d2bf803b680673cada81a Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/romstage.c 3 files changed, 26 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/47972/1 diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 50e8f93..7be84bf 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -72,33 +72,43 @@ static void fw_config_handle(void *unused) { + /* + * When FW_CONFIG is undefined (e.g., in an unprovisioned board), we + * don't yet know which audio codec is connected. Our policy here is: + * 1) Configure bus-specific GPIOs which are not yet assigned to a device as NC. + * 2) Expose all of the devices in the ACPI tables, so they can be probed at runtime + * discovery and provisioning. + * Here, that means using fw_config_probe for AUDIO,NONE because it will return true + * for an unprovisioned board, and all GPIOs will get enabled; fw_config_probe_nodefault + * can only return true on provisioned boards. + */ if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) { printk(BIOS_INFO, "Configure GPIOs for no audio.\n"); gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW))) { + if (fw_config_probe_nodefault(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW))) { printk(BIOS_INFO, "Configure GPIOs for SoundWire audio.\n"); gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); } - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || - fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) || - fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { + if (fw_config_probe_nodefault(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || + fw_config_probe_nodefault(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) || + fw_config_probe_nodefault(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP3.\n"); gpio_configure_pads(i2s_up3_enable_pads, ARRAY_SIZE(i2s_up3_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S_UP4))) { + if (fw_config_probe_nodefault(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S_UP4))) { printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP4.\n"); gpio_configure_pads(i2s_up4_enable_pads, ARRAY_SIZE(i2s_up4_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } - if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S))) { + if (fw_config_probe_nodefault(FW_CONFIG(DB_SD, SD_GL9755S))) { printk(BIOS_INFO, "Configure GPIOs for SD GL9755S.\n"); gpio_configure_pads(sd_gl9755s_pads, ARRAY_SIZE(sd_gl9755s_pads)); } diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index ea9e08f..2f016ab 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -53,10 +53,10 @@ if (!conn) return; - if (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || - fw_config_probe(FW_CONFIG(DB_USB, USB3_ACTIVE)) || - fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)) || - fw_config_probe(FW_CONFIG(DB_USB, USB3_NO_A))) { + if (fw_config_probe_nodefault(FW_CONFIG(DB_USB, USB4_GEN2)) || + fw_config_probe_nodefault(FW_CONFIG(DB_USB, USB3_ACTIVE)) || + fw_config_probe_nodefault(FW_CONFIG(DB_USB, USB4_GEN3)) || + fw_config_probe_nodefault(FW_CONFIG(DB_USB, USB3_NO_A))) { struct drivers_intel_pmc_mux_conn_config *config = conn->chip_info; if (config) { @@ -164,8 +164,8 @@ bool has_usb4; /* If device doesn't have USB4 hardware, disable tbt */ - has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) - || fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); + has_usb4 = (fw_config_probe_nodefault(FW_CONFIG(DB_USB, USB4_GEN2)) + || fw_config_probe_nodefault(FW_CONFIG(DB_USB, USB4_GEN3))); if (!has_usb4) memset(params->ITbtPcieRootPortEn, 0, diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 315ec20..a529b75 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -22,15 +22,15 @@ }; bool half_populated = gpio_get(GPIO_MEM_CH_SEL); - /* Disable HDA device if no audio board is present. */ + /* Disable HDA device if no audio board is present (or FW_CONFIG is undefined). */ if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) mem_cfg->PchHdaEnable = 0; meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); - /* Disable TBT if no USB4 hardware */ - if (!(fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || - fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)))) { + /* Disable TBT if no USB4 hardware (or if unknown) */ + if (!(fw_config_probe_nodefault(FW_CONFIG(DB_USB, USB4_GEN2)) || + fw_config_probe_nodefault(FW_CONFIG(DB_USB, USB4_GEN3)))) { mem_cfg->TcssDma0En = 0; mem_cfg->TcssItbtPcie0En = 0; mem_cfg->TcssItbtPcie1En = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/47972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8efd101174f6e3d7233d2bf803b680673cada81a Gerrit-Change-Number: 47972 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: fw_config: Default to undefined fw_config value
by Tim Wawrzynczak (Code Review) 11 Dec '20

11 Dec '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47956 ) Change subject: fw_config: Default to undefined fw_config value ...................................................................... fw_config: Default to undefined fw_config value If for some reason a value for fw_config cannot be located, set its value to a magic undefined value. The current `fw_config_probe` function is modified to return true if fw_config is undefined, and a new function `fw_config_probe_nodefault` is added which will return false if the fw_config value is undefined. A new Kconfig option is added, FW_CONFIG_IGNORE_UNDEFINED (defaults to n), which controls the behavior of fw_config probing the devicetree. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ib3046233667e97a5f78961fabacbeb3099b3d442 --- M src/Kconfig M src/include/fw_config.h M src/lib/fw_config.c 3 files changed, 43 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/47956/1 diff --git a/src/Kconfig b/src/Kconfig index dc98ca2..a0f692c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -398,6 +398,16 @@ is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was found in CBFS. +config FW_CONFIG_IGNORE_UNDEFINED + bool "Undefined Firmware Configuration value will not probe devices" + depends on FW_CONFIG + default n + help + When probing devices with fw_config, when the value is undefined or + unable to be located, all devices will be successfully probed, and + fw_config_probe will always return true. Set this to 'y' if you do + not want this behavior. + config HAVE_RAMPAYLOAD bool diff --git a/src/include/fw_config.h b/src/include/fw_config.h index 3c87725..e02a38e 100644 --- a/src/include/fw_config.h +++ b/src/include/fw_config.h @@ -45,11 +45,21 @@ * fw_config_probe() - Check if field and option matches. * @match: Structure containing field and option to probe. * - * Return %true if match is found, %false if match is not found. + * Return %true if match is found or fw_config value is undefined. + * %false if match is not found. */ bool fw_config_probe(const struct fw_config *match); /** + * fw_config_probe_nodefault() - Check if field and option matches. + * @match: Structure containing field and option to probe. + * + * Return %true if match is found. + * %false if match is not found or fw_config value is undefined + */ +bool fw_config_probe_nodefault(const struct fw_config *match); + +/** * fw_config_for_each_found() - Call a callback for each fw_config field found * @cb: The callback function * @arg: A context argument that is passed to the callback diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index e17d40e..efbee01 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -29,7 +29,7 @@ CBFS_TYPE_RAW) != sizeof(fw_config_value)) { printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n", __func__); - fw_config_value = 0; + fw_config_value = UNDEFINED_FW_CONFIG; } else { printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n", fw_config_value); @@ -39,16 +39,24 @@ /* Read the value from EC CBI. */ if (CONFIG(FW_CONFIG_SOURCE_CHROMEEC_CBI)) { - if (google_chromeec_cbi_get_fw_config(&fw_config_value)) + if (google_chromeec_cbi_get_fw_config(&fw_config_value)) { printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__); + fw_config_value = UNDEFINED_FW_CONFIG; + } } printk(BIOS_INFO, "FW_CONFIG value is 0x%" PRIx64 "\n", fw_config_value); return fw_config_value; } -bool fw_config_probe(const struct fw_config *match) +static bool fw_config_match(const struct fw_config *match, bool undefined_match) { + uint64_t fw_config; + + fw_config = fw_config_get(); + if (fw_config == UNDEFINED_FW_CONFIG) + return undefined_match; + /* Compare to system value. */ if ((fw_config_get() & match->mask) == match->value) { if (match->field_name && match->option_name) @@ -64,6 +72,16 @@ return false; } +bool fw_config_probe(const struct fw_config *match) +{ + return fw_config_match(match, true); +} + +bool fw_config_probe_nodefault(const struct fw_config *match) +{ + return fw_config_match(match, false); +} + #if ENV_RAMSTAGE /* @@ -111,7 +129,7 @@ continue; for (probe = dev->probe_list; probe && probe->mask != 0; probe++) { - if (fw_config_probe(probe)) { + if (fw_config_match(probe, (bool)!CONFIG(FW_CONFIG_IGNORE_UNDEFINED))) { match = true; cached_configs[probe_index(probe->mask)] = probe; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/47956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3046233667e97a5f78961fabacbeb3099b3d442 Gerrit-Change-Number: 47956 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 27

Change in coreboot[master]: sb/intel/bd82x6x: Drop invalid SATA registers
by Angel Pons (Code Review) 11 Dec '20

11 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47099 ) Change subject: sb/intel/bd82x6x: Drop invalid SATA registers ...................................................................... sb/intel/bd82x6x: Drop invalid SATA registers Code was copy-pasted from older chips and has no effect on bd82x6x. Change-Id: I909158906c4dc8b6f0a16558c61f095ef425a776 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/sata.c 2 files changed, 2 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47099/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index eff0858..151627d 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -159,48 +159,8 @@ #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ -#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) - -#define IDE_SDMA_TIM 0x4a - -#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) - #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 484f0f1..875f3f7 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -117,20 +117,8 @@ printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); -- To view, visit https://review.coreboot.org/c/coreboot/+/47099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I909158906c4dc8b6f0a16558c61f095ef425a776 Gerrit-Change-Number: 47099 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm`
by Angel Pons (Code Review) 11 Dec '20

11 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45258 ) Change subject: sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm` ...................................................................... sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm` There's no need to compare the vendor ID. Change-Id: I4368f2615e5ce72430992f1f5581908c90c970f0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45258/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index c51cca6..3876b02 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -168,16 +168,16 @@ void intel_me_finalize_smm(void) { - u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID); switch (did) { - case 0x1c3a8086: + case 0x1c3a: intel_me7_finalize_smm(); break; - case 0x1e3a8086: + case 0x1e3a: intel_me8_finalize_smm(); break; default: - printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); + printk(BIOS_ERR, "No finalize handler for ME %04x.\n", did); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4368f2615e5ce72430992f1f5581908c90c970f0 Gerrit-Change-Number: 45258 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: Drop many cases of .previous directive use
by Kyösti Mälkki (Code Review) 11 Dec '20

11 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47963 ) Change subject: Drop many cases of .previous directive use ...................................................................... Drop many cases of .previous directive use Since most assembly files are no longer concatenated together but built separately, section changes with .previous at the end of the files have become spurious. Change-Id: I2970eed2b114a53475ba385eec4e97bb7ae7095c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/arm/id.S M src/arch/arm64/id.S M src/arch/ppc64/bootblock.S M src/arch/x86/c_start.S M src/arch/x86/id.S M src/cpu/intel/fit/fit.S 6 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/47963/1 diff --git a/src/arch/arm/id.S b/src/arch/arm/id.S index 3d3df96..a8f7a79 100644 --- a/src/arch/arm/id.S +++ b/src/arch/arm/id.S @@ -19,4 +19,3 @@ .globl __id_end __id_end: -.previous diff --git a/src/arch/arm64/id.S b/src/arch/arm64/id.S index 3d3df96..a8f7a79 100644 --- a/src/arch/arm64/id.S +++ b/src/arch/arm64/id.S @@ -19,4 +19,3 @@ .globl __id_end __id_end: -.previous diff --git a/src/arch/ppc64/bootblock.S b/src/arch/ppc64/bootblock.S index 106c61a..8b66fcd 100644 --- a/src/arch/ppc64/bootblock.S +++ b/src/arch/ppc64/bootblock.S @@ -31,4 +31,3 @@ .globl __id_end __id_end: -.previous diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index c46a45c..a7af64f 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -235,10 +235,4 @@ # restore rsp, it might not have been 16-byte aligned on entry mov %rdx, %rsp ret - - .previous -.code64 -#else - .previous -.code32 #endif diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S index 798b25d..a7b4be7 100644 --- a/src/arch/x86/id.S +++ b/src/arch/x86/id.S @@ -25,4 +25,3 @@ .globl __id_end __id_end: -.previous diff --git a/src/cpu/intel/fit/fit.S b/src/cpu/intel/fit/fit.S index 3b7396c..afecacd 100644 --- a/src/cpu/intel/fit/fit.S +++ b/src/cpu/intel/fit/fit.S @@ -6,7 +6,6 @@ fit_pointer: .long fit_table .long 0 -.previous .section .text .align 16 @@ -29,4 +28,3 @@ .byte 0x7d .fill CONFIG_CPU_INTEL_NUM_FIT_ENTRIES*16 fit_table_end: -.previous -- To view, visit https://review.coreboot.org/c/coreboot/+/47963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2970eed2b114a53475ba385eec4e97bb7ae7095c Gerrit-Change-Number: 47963 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/google/volteer/variant/lindar: Correct IOM port configation for li...
by Kevin Chang (Code Review) 11 Dec '20

11 Dec '20

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47785 ) Change subject: mb/google/volteer/variant/lindar: Correct IOM port configation for lindar ...................................................................... mb/google/volteer/variant/lindar: Correct IOM port configation for lindar Correct IOM setting and TCSS AUX setting to fix type C C0 port flip issue. BUG=b:173093980 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS, test USB function normally. Change-Id: I827a2d8a5b01dce412b4170fde0f638670ab8baf --- M src/mainboard/google/volteer/variants/lindar/overridetree.cb 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/47785/1 diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 0c6e8629..49749f4 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -1,6 +1,9 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" # USB Port Config register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 @@ -109,8 +112,7 @@ chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "9" register "usb3_port_number" = "1" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + # SBU & HSL follows CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn -- To view, visit https://review.coreboot.org/c/coreboot/+/47785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827a2d8a5b01dce412b4170fde0f638670ab8baf Gerrit-Change-Number: 47785 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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