coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/broadwell: Drop unnecessary `sa_dev`
by Angel Pons (Code Review) 16 Dec '20

16 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46982 ) Change subject: soc/intel/broadwell: Drop unnecessary `sa_dev` ...................................................................... soc/intel/broadwell: Drop unnecessary `sa_dev` Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/northbridge.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46982/1 diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 5fec655..eb8b5f0 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -268,7 +268,6 @@ uint64_t mc_values[NUM_MAP_ENTRIES]; unsigned long dpr_size = 0; u32 dpr_reg; - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* Read in the MAP registers and report their values */ mc_read_map_entries(dev, &mc_values[0]); @@ -280,7 +279,7 @@ * the DPR register reports the TOP of the region, which is the same * as TSEG base. The region size is reported in MiB in bits 11:4. */ - dpr_reg = pci_read_config32(sa_dev, DPR); + dpr_reg = pci_read_config32(dev, DPR); if (dpr_reg & DPR_EPM) { dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/46982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed Gerrit-Change-Number: 46982 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: [WIP] arch/x86: Clean up bootblock assembly
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47964 ) Change subject: [WIP] arch/x86: Clean up bootblock assembly ...................................................................... [WIP] arch/x86: Clean up bootblock assembly We hae identical gdtptr16 and gdtptr. The reference in gdtptr_offset calculation is not accounted for when considering --gc-sections, so to support linking gdt_init.S separately add dummy use of gdtptr symbol. Realmode execution already accessed gdt that was located outside [_start16bit,_estart16bit] region. Remove latter symbol as the former was not really a start of region, but entry point symbol. With the romcc bootblock solution, entry32.inc may have been linked into romstage once. Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/bootblock.ld M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/32bit/entry32.inc M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld 4 files changed, 6 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/47964/1 diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index ff7bb62..4a3dbb9 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -gdtptr16_offset = gdtptr16 & 0xffff; +gdtptr_offset = gdtptr & 0xffff; nullidt_offset = nullidt & 0xffff; /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 13d12be..2665cc6 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -108,7 +108,7 @@ movw $nullidt_offset, %bx subw %ax, %bx lidt %cs:(%bx) - movw $gdtptr16_offset, %bx + movw $gdtptr_offset, %bx subw %ax, %bx lgdtl %cs:(%bx) @@ -127,11 +127,8 @@ * The gdt is defined in entry32.inc, it has a 4 Gb code segment * at 0x08, and a 4 GB data segment at 0x10; */ -.align 4 -.globl gdtptr16 -gdtptr16: - .word gdt_end - gdt -1 /* compute the table limit */ - .long gdt /* we know the offset */ +__gdtptr: + .long gdtptr .align 4 .globl nullidt @@ -139,7 +136,3 @@ .word 0 /* limit */ .long 0 .word 0 - -.globl _estart16bit -_estart16bit: - .code32 diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index be67b53..8509448 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -8,29 +8,11 @@ .code32 /* - * When we come here we are in protected mode. We expand - * the stack and copies the data segment from ROM to the - * memory. - * - * After that, we call the chipset bootstrap routine that - * does what is left of the chipset initialization. - * + * When we come here we are in protected mode. * NOTE aligned to 4 so that we are sure that the prefetch * cache will be reloaded. - * - * In the bootblock there is already a ljmp to __protected_start and - * the reset vector jumps to symbol _start16bit in entry16.inc from - * the reset vectors's symbol which is _start. Therefore, don't - * expose the _start symbol for bootblock. */ .align 4 -#if !ENV_BOOTBLOCK -.globl _start -_start: -#endif - - lgdt %cs:gdtptr - ljmp $ROM_CODE_SEG, $__protected_start __protected_start: /* Save the BIST value */ diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 369d431..c2b37f8 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -98,7 +98,7 @@ #if ENV_BOOTBLOCK -gdtptr16_offset = gdtptr16 & 0xffff; +gdtptr_offset = gdtptr & 0xffff; nullidt_offset = nullidt & 0xffff; SECTIONS { -- To view, visit https://review.coreboot.org/c/coreboot/+/47964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9 Gerrit-Change-Number: 47964 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/mediatek/mt8192: return correct voltage of VM18
by hsin-hsiung wang (Code Review) 16 Dec '20

16 Dec '20

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48110 ) Change subject: soc/mediatek/mt8192: return correct voltage of VM18 ...................................................................... soc/mediatek/mt8192: return correct voltage of VM18 The voltage of vm18 should be microvolt instead of millivolt. BUG=b:155253454 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: Iea5b46c1df358dc350506d29cc033d01631b37b0 --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/48110/1 diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index 1646e53..0c34db3 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -417,7 +417,7 @@ reg_vol = 100 * mt6359p_read_field(PMIC_VM18_ANA_CON0, 0xF, VM18_VOL_REG_SHIFT); reg_cali = 10 * mt6359p_read_field(PMIC_VM18_ANA_CON0, 0xF, 0); - return 600 + reg_vol + reg_cali; + return 1000 * (600 + reg_vol + reg_cali); } static void init_pmif_arb(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/48110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea5b46c1df358dc350506d29cc033d01631b37b0 Gerrit-Change-Number: 48110 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/mediatek/mt8192: Keep CONN MCU in reset state
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46447 to review the following change. Change subject: soc/mediatek/mt8192: Keep CONN MCU in reset state ...................................................................... soc/mediatek/mt8192: Keep CONN MCU in reset state Keep the CONN MCU in reset state to prevent CONN from asserting the clk26m request to SPM. TEST=clk26m request from conn has been released. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f --- M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/46447/1 diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 35e8ff2..cafa1dd 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -306,6 +306,9 @@ DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24) +DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12) + enum { INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = ((0x1f << 12) | \ (0x1 << 17) | \ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 0366cd6..fdd0b1e 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -10,6 +10,7 @@ #include <soc/infracfg.h> #include <soc/mcucfg.h> #include <soc/pll.h> +#include <soc/wdt.h> enum mux_id { TOP_AXI_SEL, @@ -460,6 +461,11 @@ /* enable [14] dramc_pll104m_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + + /* reset CONNSYS MCU */ + SET32_BITFIELDS(&mtk_wdt->wdt_swsysrst, + WDT_SWSYSRST_KEY, 0x88, + WDT_SWSYSRST_CONN_MCU, 1); } void mt_pll_raise_little_cpu_freq(u32 freq) -- To view, visit https://review.coreboot.org/c/coreboot/+/46447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f Gerrit-Change-Number: 46447 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc init settings
by CK HU (Code Review) 16 Dec '20

16 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44700 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc init settings ...................................................................... soc/mediatek/mt8192: Do dramc init settings Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_basic_api.c A src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/dramc_utility.c M src/soc/mediatek/mt8192/emi.c 5 files changed, 242 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/44700/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index dd80beb..e82f182 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,6 +16,7 @@ verstage-y += ../common/uart.c romstage-y += ../common/cbmem.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_utility.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c new file mode 100644 index 0000000..9b1216c --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <string.h> +#include <timer.h> + +void global_option_init(struct ddr_cali *cali) +{ +} + +void dfs_init_for_calibration(const struct ddr_cali *cali) +{ +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c new file mode 100644 index 0000000..e2c7500 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/mt6359p.h> + +static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) +{ + u32 vcore = get_vcore_value(cali); + + dramc_info("Set DRAM vcore voltage to %u\n", vcore); + mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); +} + +static void dramc_calibration_all_channels(struct ddr_cali *cali) +{ +} + +void init_dram(const struct dramc_data *dparam) +{ + u32 bc_bak; + u8 k_shuffle, k_shuffle_end; + u8 pll_mode = 0; + bool first_freq_k = true; + + struct ddr_cali cali = {0}; + struct mr_values mr_value; + const struct ddr_base_info *ddr_info = &dparam->ddr_info; + + cali.pll_mode = &pll_mode; + cali.mr_value = &mr_value; + cali.support_ranks = ddr_info->support_ranks; + cali.cbt_mode[RANK_0] = ddr_info->cbt_mode[RANK_0]; + cali.cbt_mode[RANK_1] = ddr_info->cbt_mode[RANK_1]; + cali.emi_config = &ddr_info->emi_config; + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + global_option_init(&cali); + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + dramc_set_broadcast(bc_bak); + + if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) + k_shuffle_end = CALI_SEQ_MAX; + else + k_shuffle_end = CALI_SEQ1; + + for (k_shuffle = CALI_SEQ0; k_shuffle < k_shuffle_end; k_shuffle++) { + set_cali_datas(&cali, dparam, k_shuffle); + set_vcore_voltage_for_each_freq(&cali); + dfs_init_for_calibration(&cali); + + dramc_calibration_all_channels(&cali); + + first_freq_k= false; + } +} diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/soc/mediatek/mt8192/dramc_utility.c new file mode 100644 index 0000000..526059a --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_utility.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/infracfg.h> + +struct dfs_frequency_table { + u32 frequency; + dram_freq_grp freq_group; + dram_div_mode div_mode; + dram_dfs_shu shuffle_saved; + vref_cali_mode vref_cali; + u32 vcore; +}; + +static const struct dfs_frequency_table freq_shuffle_table[DRAM_DFS_SHU_MAX] = { + /* frequency freq_group div_mode shuffle_saved vref_cali vcore*/ + [CALI_SEQ0] = {800, DDRFREQ_800, DIV8_MODE, DRAM_DFS_SHU4, VREF_CALI_ON, 650000}, + [CALI_SEQ1] = {1200, DDRFREQ_1200, DIV8_MODE, DRAM_DFS_SHU2, VREF_CALI_ON, 662500}, + [CALI_SEQ2] = {600, DDRFREQ_600, DIV8_MODE, DRAM_DFS_SHU5, VREF_CALI_OFF, 650000}, + [CALI_SEQ3] = {933, DDRFREQ_933, DIV8_MODE, DRAM_DFS_SHU3, VREF_CALI_OFF, 662500}, + [CALI_SEQ4] = {400, DDRFREQ_400, DIV4_MODE, DRAM_DFS_SHU6, VREF_CALI_OFF, 650000}, + [CALI_SEQ5] = {2133, DDRFREQ_2133, DIV8_MODE, DRAM_DFS_SHU0, VREF_CALI_ON, 725000}, + [CALI_SEQ6] = {1600, DDRFREQ_1600, DIV8_MODE, DRAM_DFS_SHU1, VREF_CALI_OFF, 687500}, +}; + +void dramc_set_broadcast(u32 onoff) +{ + write32(&mt8192_infracfg->dramc_wbr, onoff); +} + +u32 dramc_get_broadcast(void) +{ + return read32(&mt8192_infracfg->dramc_wbr); +} + +u8 get_fsp(const struct ddr_cali *cali) +{ + return cali->fsp; +} + +dram_div_mode get_div_mode(const struct ddr_cali *cali) +{ + return cali->div_mode; +} + +dram_freq_grp get_freq_group(const struct ddr_cali *cali) +{ + return cali->freq_group; +} + +dbi_mode get_write_dbi(const struct ddr_cali *cali) +{ + return cali->w_dbi[get_fsp(cali)]; +} + +dram_odt_state get_odt_state(const struct ddr_cali *cali) +{ + return cali->odt_onoff; +} + +dram_dfs_shu get_shu(const struct ddr_cali *cali) +{ + return cali->shu; +} + +dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali) +{ + return cali->cbt_mode[cali->rank]; +} + +u32 get_vcore_value(const struct ddr_cali *cali) +{ + return cali->vcore_voltage; +} + +u32 get_frequency(const struct ddr_cali *cali) +{ + return cali->frequency; +} + +vref_cali_mode get_vref_cali(const struct ddr_cali *cali) +{ + return cali->vref_cali; +} + +dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali) +{ + return cali->pinmux_type; +} + +u8 get_mck2ui_div_shift(const struct ddr_cali *cali) +{ + if (get_div_mode(cali) == DIV4_MODE) + return 2; + else + return 3; +} + +dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_shu) +{ + return freq_shuffle_table[k_shu].shuffle_saved; +} + +dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu) +{ + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].shuffle_saved == shu) + return freq_shuffle_table[k_shu].freq_group; + + dramc_err("Invalid shuffle:%d\n", shu); + return DDRFREQ_800; +} + +u32 get_frequency_by_shu(dram_dfs_shu shu) +{ + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].shuffle_saved == shu) + return freq_shuffle_table[k_shu].frequency; + + dramc_err("Invalid shuffle:%d\n", shu); + return 800; +} + +dram_freq_grp get_highest_freq_group(void) +{ + dram_freq_grp highest_freq = DDRFREQ_800; + + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].freq_group > highest_freq) + highest_freq = freq_shuffle_table[k_shu].freq_group; + + dramc_dbg("Highest freq is :%d\n", highest_freq); + return highest_freq; +} + +void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_shu) +{ + cali->chn = CHANNEL_A; + cali->rank = RANK_0; + cali->fsp = (freq_shuffle_table[k_shu].freq_group < DDRFREQ_1600) ? FSP_0 : FSP_1; + cali->w_dbi[FSP_0] = DBI_OFF; + cali->w_dbi[FSP_1] = DBI_ON; + cali->frequency = freq_shuffle_table[k_shu].frequency; + cali->freq_group = freq_shuffle_table[k_shu].freq_group; + cali->div_mode = freq_shuffle_table[k_shu].div_mode; + cali->shu = freq_shuffle_table[k_shu].shuffle_saved; + cali->vref_cali = freq_shuffle_table[k_shu].vref_cali; + cali->vcore_voltage = freq_shuffle_table[k_shu].vcore; + cali->odt_onoff = (cali->fsp == FSP_0) ? ODT_OFF : ODT_ON; + cali->params = &dparam->freq_params[cali->shu]; + + dramc_dbg("cali data(size:%ld) use fsp:%d, freq_group:%d, div_mode:%d, shu:%d, vref_cali:%d, odt_onoff:%d, vcore:%d\n", + sizeof(*cali), cali->fsp, cali->freq_group, cali->div_mode, cali->shu, + cali->vref_cali, cali->odt_onoff, cali->vcore_voltage); +} + +void dramc_auto_refresh_switch(u8 chn, bool enable) +{ + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, enable ? 0 : 1); + + if (!enable) { + udelay(READ32_BITFIELD(&ch[chn].nao.misc_statusa, + MISC_STATUSA_REFRESH_QUEUE_CNT)); + } +} diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index 9e48918..f83acd3 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/emi.h> +#include <soc/dramc_pi_api.h> size_t sdram_size(void) { @@ -11,4 +11,5 @@ void mt_set_emi(const struct dramc_data *dparam) { + init_dram(dparam); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 Gerrit-Change-Number: 44700 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 75

Change in coreboot[master]: soc/amd/common: Use only byte access for IOMUX
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42978 ) Change subject: soc/amd/common: Use only byte access for IOMUX ...................................................................... soc/amd/common: Use only byte access for IOMUX Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h 1 file changed, 2 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42978/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index e684e36..34300af 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -239,36 +239,18 @@ write8(acpimmio_smbus + reg, value); } +/* These iomux_read/write8 are to be deprecated to enforce proper + use of <gpio.h> API for pin configurations. */ static inline uint8_t iomux_read8(uint8_t reg) { return read8(acpimmio_iomux + reg); } -static inline uint16_t iomux_read16(uint8_t reg) -{ - return read16(acpimmio_iomux + reg); -} - -static inline uint32_t iomux_read32(uint8_t reg) -{ - return read32(acpimmio_iomux + reg); -} - static inline void iomux_write8(uint8_t reg, uint8_t value) { write8(acpimmio_iomux + reg, value); } -static inline void iomux_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_iomux + reg, value); -} - -static inline void iomux_write32(uint8_t reg, uint32_t value) -{ - write32(acpimmio_iomux + reg, value); -} - static inline uint8_t misc_read8(uint8_t reg) { return read8(acpimmio_misc + reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/42978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Gerrit-Change-Number: 42978 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: dcm: mt8192: Enable DCM
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46407 ) Change subject: WIP: dcm: mt8192: Enable DCM ...................................................................... WIP: dcm: mt8192: Enable DCM Enable DCM settings. /* INFRACFG_AO */ dcm_infracfg_ao_aximem_bus_dcm(on); dcm_infracfg_ao_infra_bus_dcm(on); dcm_infracfg_ao_infra_conn_bus_dcm(on); dcm_infracfg_ao_infra_rx_p2p_dcm(on); dcm_infracfg_ao_peri_bus_dcm(on); dcm_infracfg_ao_peri_module_dcm(on); /* INFRA_AO_BCRM */ dcm_infra_ao_bcrm_infra_bus_dcm(on); dcm_infra_ao_bcrm_peri_bus_dcm(on); /* INFRACFG_AO_MEM */ /* move to preloader */ /* dcm_infracfg_ao_mem_dcm_emi_group(on); */ Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 --- M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/46407/1 diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 09c4c471..35e8ff2 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -306,4 +306,59 @@ DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +enum { + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = ((0x1f << 12) | \ + (0x1 << 17) | \ + (0x1 << 18)), + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = ((0x10 << 12) | \ + (0x1 << 17) | \ + (0x0 << 18)), + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x1 << 3) | \ + (0x1 << 4) | \ + (0x1f << 5) | \ + (0x1f << 10) | \ + (0x1 << 20) | \ + (0x1 << 23) | \ + (0x1 << 30)), + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x0 << 3) | \ + (0x0 << 4) | \ + (0x10 << 5) | \ + (0x1 << 10) | \ + (0x1 << 20) | \ + (0x1 << 23) | \ + (0x1 << 30)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON = ((0x0 << 8)), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = ((0xf << 0)), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = ((0x0 << 0)), + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x1 << 3) | \ + (0x1 << 4) | \ + (0x1f << 5) | \ + (0x1f << 10) | \ + (0x1f << 15) | \ + (0x1 << 20) | \ + (0x1 << 21)), + INFRACFG_AO_PERI_BUS_DCM_REG0_ON = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x0 << 3) | \ + (0x0 << 4) | \ + (0x1f << 5) | \ + (0x0 << 10) | \ + (0x1f << 15) | \ + (0x1 << 20) | \ + (0x1 << 21)), + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = ((0x1 << 29) | \ + (0x1 << 31)), + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = ((0x1 << 29) | \ + (0x1 << 31)), +}; + #endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 24cfafd..0366cd6 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -427,6 +427,27 @@ /* enable infrasys DCM */ setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + // dcm_infracfg_ao_aximem_bus_dcm + clrsetbits_le32(&mt8192_infracfg->infra_aximem_idle_bit_en_0, + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_infra_bus_dcm + clrsetbits_le32(&mt8192_infracfg->infra_bus_dcm_ctrl, + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_infra_conn_bus_dcm + clrsetbits_le32(&mt8192_infracfg->module_sw_cg_2_set, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON); + clrsetbits_le32(&mt8192_infracfg->module_sw_cg_2_clr, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON); + // dcm_infracfg_ao_infra_rx_p2p_dcm + clrsetbits_le32(&mt8192_infracfg->p2p_rx_clk_on, + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON); + // dcm_infracfg_ao_peri_bus_dcm + clrsetbits_le32(&mt8192_infracfg->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, INFRACFG_AO_PERI_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_peri_module_dcm + clrsetbits_le32(&mt8192_infracfg->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, INFRACFG_AO_PERI_MODULE_DCM_REG0_ON); + /* initialize SPM request */ setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3); -- To view, visit https://review.coreboot.org/c/coreboot/+/46407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 Gerrit-Change-Number: 46407 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

4 47

Change in coreboot[master]: soc/mediatek/mt8192: ufs: disable refer clk
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46408 ) Change subject: soc/mediatek/mt8192: ufs: disable refer clk ...................................................................... soc/mediatek/mt8192: ufs: disable refer clk ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage. Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing(a)mediatek.com> Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 4ce5e6a..7b098e8 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += devapc.c +ramstage-y += ufs.c ramstage-y += mcupm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 19728a3..85eac5b 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -47,6 +47,7 @@ SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + UFSHCI_BASE = IO_PHYS + 0x01270000, EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, diff --git a/src/soc/mediatek/mt8192/include/soc/ufs.h b/src/soc/mediatek/mt8192/include/soc/ufs.h new file mode 100644 index 0000000..259aaf4 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/ufs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_UFS_H +#define SOC_MEDIATEK_MT8192_UFS_H + +#include <device/mmio.h> +#include <soc/addressmap.h> + +void ufs_disable_refclk(void); + +enum ufshci_offset { + REG_UFS_REFCLK_CTRL = 0x144, +}; + +#define UFS_REFCLK_CTRL (ufshci_base + (unsigned long)REG_UFS_REFCLK_CTRL) + +#endif /* SOC_MEDIATEK_MT8192_UFS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index ba153f2..c865e6f 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -6,6 +6,7 @@ #include <symbols.h> #include <soc/devapc.h> #include <soc/mcupm.h> +#include <soc/ufs.h> static void soc_read_resources(struct device *dev) { @@ -16,7 +17,8 @@ { mtk_mmu_disable_l2c_sram(); dapc_init(); - mcupm_init(); + mcupm_init(); + ufs_disable_refclk(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8192/ufs.c b/src/soc/mediatek/mt8192/ufs.c new file mode 100644 index 0000000..854ef4c --- /dev/null +++ b/src/soc/mediatek/mt8192/ufs.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ufs.h> + +static unsigned long ufshci_base = (unsigned long)UFSHCI_BASE; + +void ufs_disable_refclk(void) +{ + /* disable ref clock to let UFSHCI release SPM signal */ + write32((void*)UFS_REFCLK_CTRL, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 Gerrit-Change-Number: 46408 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Initialize audio pll tuner frequency
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46400 to review the following change. Change subject: soc/mediatek/mt8192: Initialize audio pll tuner frequency ...................................................................... soc/mediatek/mt8192: Initialize audio pll tuner frequency Add AUDPLL TUNER init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 --- M src/soc/mediatek/mt8192/pll.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46400/1 diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 11750d2..24cfafd 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -392,6 +392,10 @@ for (i = 0; i < ARRAY_SIZE(rates); i++) pll_set_rate(&plls[rates[i].id], rates[i].rate); + /* AUDPLL Tuner Frequency Set */ + write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con2) + 1); + write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con2) + 1); + /* xPLL Frequency Enable */ for (i = 0; i < APMIXED_PLL_MAX; i++) { if (i == APMIXED_USBPLL) -- To view, visit https://review.coreboot.org/c/coreboot/+/46400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 Gerrit-Change-Number: 46400 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/xeon_sp: Lock down DMIC
by Arthur Heymans (Code Review) 16 Dec '20

16 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47449 ) Change subject: soc/intel/xeon_sp: Lock down DMIC ...................................................................... soc/intel/xeon_sp: Lock down DMIC This is required for CBnT. Change-Id: I290742c163f5f067c8d529ddca8e2d8572ab6e6a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/pch.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47449/1 diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 5427952..2b35223 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -39,6 +39,9 @@ reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); + + reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); } void bootblock_pch_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/47449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I290742c163f5f067c8d529ddca8e2d8572ab6e6a Gerrit-Change-Number: 47449 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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