coreboot-gerrit November 2020

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Change in coreboot[master]: soc/mediatek/mt8192: add 6359p driver support for romstage
by Yidi Lin (Code Review) 18 Dec '20

18 Dec '20

Hello hsin-hsiung wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46397 to review the following change. Change subject: soc/mediatek/mt8192: add 6359p driver support for romstage ...................................................................... soc/mediatek/mt8192: add 6359p driver support for romstage Add 6359p driver support for romstage. TEST=Boots correctly on asurada p0. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I46bca69836d41e7c35b196d91d9fbdbdb7d71df7 --- M src/mainboard/google/asurada/romstage.c M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/mt6359p.h M src/soc/mediatek/mt8192/mt6359p.c 4 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/46397/1 diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c index 3d03bd4..bd5cd74 100644 --- a/src/mainboard/google/asurada/romstage.c +++ b/src/mainboard/google/asurada/romstage.c @@ -6,6 +6,7 @@ #include <soc/dramc_param.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/mt6359p.h> /* This must be defined in chromeos.fmd in same name and size. */ #define CALIBRATION_REGION "RW_DDR_TRAINING" @@ -43,6 +44,7 @@ void platform_romstage_main(void) { + mt6359p_romstage_init(); mt_mem_init(&dparam_ops); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index e7ff25d..657aa8e 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -33,6 +33,7 @@ romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +romstage-y += mt6359p.c ramstage-y += auxadc.c ramstage-y += flash_controller.c diff --git a/src/soc/mediatek/mt8192/include/soc/mt6359p.h b/src/soc/mediatek/mt8192/include/soc/mt6359p.h index ce7ef24..c0f01a0 100644 --- a/src/soc/mediatek/mt8192/include/soc/mt6359p.h +++ b/src/soc/mediatek/mt8192/include/soc/mt6359p.h @@ -41,6 +41,7 @@ #define VM18_VOL_REG_SHIFT 8 void mt6359p_init(void); +void mt6359p_romstage_init(void); void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uv); u32 mt6359p_buck_get_voltage(u32 buck_id); void mt6359p_set_vm18_voltage(u32 vm18_uv); diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index c70485d..2eb3f60 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -457,3 +457,12 @@ pmic_lp_setting(); pmic_wk_vs2_voter_setting(); } + +void mt6359p_romstage_init(void) +{ + if (pmif_arb == NULL) { + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + if (pmif_arb == NULL) + die("ERROR - Failed to get pmif controller\n"); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46bca69836d41e7c35b196d91d9fbdbdb7d71df7 Gerrit-Change-Number: 46397 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/mediatek/mt8192: Set BL31 platform mt8192
by Yidi Lin (Code Review) 17 Dec '20

17 Dec '20

Hello CK HU, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46383 to review the following change. Change subject: soc/mediatek/mt8192: Set BL31 platform mt8192 ...................................................................... soc/mediatek/mt8192: Set BL31 platform mt8192 Change-Id: I80d4a339b4a75647f55a699af447dcd362aab7b5 Signed-off-by: CK Hu <ck.hu(a)mediatek.com> --- M src/soc/mediatek/mt8192/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46383/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 20acd24..8bc7b74 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -49,6 +49,8 @@ cbfs-files-y += $(DRAM_CBFS) endif +BL31_MAKEARGS += PLAT=mt8192 + CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include -- To view, visit https://review.coreboot.org/c/coreboot/+/46383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80d4a339b4a75647f55a699af447dcd362aab7b5 Gerrit-Change-Number: 46383 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: [WIP] arch/x86: Use intermediate .id section
by Kyösti Mälkki (Code Review) 17 Dec '20

17 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47602 ) Change subject: [WIP] arch/x86: Use intermediate .id section ...................................................................... [WIP] arch/x86: Use intermediate .id section The strings in id.S are the same as those defined in lib/version.c. Eliminating the calculation of reverse offsets allows the references across linker sections and dropping the duplicate strings in id.S. TBD: util/cbfstool needs to post-process and invert the offsets in .id section. Change-Id: I35d3312336e9c66d657d2ca619cf30fd79e18fd4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/id.S 1 file changed, 4 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47602/1 diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S index 4ff397d..545232a 100644 --- a/src/arch/x86/id.S +++ b/src/arch/x86/id.S @@ -4,23 +4,9 @@ .section ".id", "a", @progbits -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER - -#if ENV_X86_64 -.long 0xffffffff - ver + 1 /* Reverse offset to the version */ -.long 0xffffffff - vendor + 1 /* Reverse offset to the vendor id */ -.long 0xffffffff - part + 1 /* Reverse offset to the part number */ -#else -.long - ver /* Reverse offset to the version */ -.long - vendor /* Reverse offset to the vendor id */ -.long - part /* Reverse offset to the part number */ -#endif - -.long CONFIG_ROM_SIZE /* Size of this romimage */ +.long coreboot_version /* Reverse offset to the version */ +.long mainboard_vendor /* Reverse offset to the vendor id */ +.long mainboard_part_number /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ .previous -- To view, visit https://review.coreboot.org/c/coreboot/+/47602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35d3312336e9c66d657d2ca619cf30fd79e18fd4 Gerrit-Change-Number: 47602 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: arch/ppc64: Remove .id section in bootblock
by Kyösti Mälkki (Code Review) 17 Dec '20

17 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47966 ) Change subject: arch/ppc64: Remove .id section in bootblock ...................................................................... arch/ppc64: Remove .id section in bootblock The strings in .id are expected to match the build for the purpose of identifying the binary image. There is no identified use for the offsets. The files id.ld and prologue.inc were unused. Change-Id: Ida332671e0ace3f6afd11020474ffda04614bad5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/ppc64/Kconfig M src/arch/ppc64/bootblock.S D src/arch/ppc64/id.ld D src/arch/ppc64/prologue.inc 4 files changed, 0 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/47966/1 diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 546dbc8..44dbb1d 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -17,7 +17,3 @@ config ARCH_RAMSTAGE_PPC64 bool select ARCH_PPC64 - -config ID_SECTION_OFFSET - hex - default 0x80 diff --git a/src/arch/ppc64/bootblock.S b/src/arch/ppc64/bootblock.S index 8b66fcd..b443f05 100644 --- a/src/arch/ppc64/bootblock.S +++ b/src/arch/ppc64/bootblock.S @@ -8,26 +8,3 @@ .org 0x100, 0xff _start: b _start - .section ".id", "a", %progbits - - .section ".id", "a", @progbits - - .globl __id_start -__id_start: -ver: - .asciz "4" //COREBOOT_VERSION -vendor: - .asciz "qemu" //CONFIG_MAINBOARD_VENDOR -part: - .asciz "1" //CONFIG_MAINBOARD_PART_NUMBER - /* Reverse offset to the vendor id */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - ver - /* Reverse offset to the vendor id */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor - /* Reverse offset to the part number */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - part - /* of this romimage */ -.long CONFIG_ROM_SIZE - .globl __id_end - -__id_end: diff --git a/src/arch/ppc64/id.ld b/src/arch/ppc64/id.ld deleted file mode 100644 index 7449740..0000000 --- a/src/arch/ppc64/id.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; - .id (.): { - *(.id) - } -} diff --git a/src/arch/ppc64/prologue.inc b/src/arch/ppc64/prologue.inc deleted file mode 100644 index 21f7d49..0000000 --- a/src/arch/ppc64/prologue.inc +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -.section ".rom.data", "a", @progbits -.section ".rom.text", "ax", @progbits -- To view, visit https://review.coreboot.org/c/coreboot/+/47966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida332671e0ace3f6afd11020474ffda04614bad5 Gerrit-Change-Number: 47966 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: arch/x86: Remove ID_SECTION_OFFSET
by Kyösti Mälkki (Code Review) 17 Dec '20

17 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47598 ) Change subject: arch/x86: Remove ID_SECTION_OFFSET ...................................................................... arch/x86: Remove ID_SECTION_OFFSET The location is hardcoded inside flashrom at least and currently there is no platform that needs to locate it elsewhere. Change-Id: I8348f2ac0cab969ab78ecb50a55de486eee0cf9b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/ppc64/Kconfig M src/arch/x86/Kconfig M src/arch/x86/id.S M src/cpu/x86/16bit/reset16.ld 4 files changed, 12 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47598/1 diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 44dbb1d..546dbc8 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -17,3 +17,7 @@ config ARCH_RAMSTAGE_PPC64 bool select ARCH_PPC64 + +config ID_SECTION_OFFSET + hex + default 0x80 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index b5e52e6..f4ddd20 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -179,10 +179,6 @@ hex default 0xfed00000 if !HPET_ADDRESS_OVERRIDE -config ID_SECTION_OFFSET - hex - default 0x80 - # 64KiB default bootblock size config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S index 798b25d..f79952f 100644 --- a/src/arch/x86/id.S +++ b/src/arch/x86/id.S @@ -2,27 +2,18 @@ #include <build.h> - .section ".id", "a", @progbits +.section ".id", "a", @progbits - .globl __id_start -__id_start: ver: .asciz COREBOOT_VERSION vendor: .asciz CONFIG_MAINBOARD_VENDOR part: .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the - *vendor id - */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the - * vendor id - */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the - * part number - */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end -__id_end: +.long - ver /* Reverse offset to the version */ +.long - vendor /* Reverse offset to the vendor id */ +.long - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ + .previous diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index 1c7e40f..d356034 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -20,10 +20,11 @@ /* Trigger an error if I have an unuseable start address */ _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; + . = ID_SECTION; .id (.): { KEEP(*(.id)) } + ID_SECTION = 0xffffff80 - SIZEOF(.id); #if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) . = 0xffffffc0; -- To view, visit https://review.coreboot.org/c/coreboot/+/47598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8348f2ac0cab969ab78ecb50a55de486eee0cf9b Gerrit-Change-Number: 47598 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: autoport: Add a license header to non-empty asl files
by Iru Cai (vimacs) (Code Review) 17 Dec '20

17 Dec '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45464 to review the following change. Change subject: autoport: Add a license header to non-empty asl files ...................................................................... autoport: Add a license header to non-empty asl files Change-Id: I8078d8babf24feabb22856ee820ab45b7d466f62 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/ec_fixme.go M util/autoport/ec_lenovo.go M util/autoport/ec_none.go M util/autoport/main.go 4 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45464/1 diff --git a/util/autoport/ec_fixme.go b/util/autoport/ec_fixme.go index f5d039c..54f78ab 100644 --- a/util/autoport/ec_fixme.go +++ b/util/autoport/ec_fixme.go @@ -19,6 +19,7 @@ SouthBridge.EnableGPE(SouthBridge.DecodeGPE(sbGPE)) } + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { @@ -64,6 +65,7 @@ defer si.Close() if hasKeyboard { + Add_gpl(si) si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n") MainboardInit += fmt.Sprintf("\tpc_keyboard_init(NO_AUX_DEVICE);\n") MainboardIncludes = append(MainboardIncludes, "pc80/keyboard.h") @@ -72,6 +74,7 @@ ec := Create(ctx, "acpi/ec.asl") defer ec.Close() + Add_gpl(ec) ec.WriteString(`Device(EC) { Name (_HID, EISAID("PNP0C09")) diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go index 6851d6d..763ac26 100644 --- a/util/autoport/ec_lenovo.go +++ b/util/autoport/ec_lenovo.go @@ -39,6 +39,7 @@ Value: "1", }, GPEDefine) + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { @@ -57,6 +58,7 @@ si := Create(ctx, "acpi/superio.asl") defer si.Close() + Add_gpl(si) si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n") /* FIXME:XX Move this to ec/lenovo. */ @@ -163,6 +165,7 @@ ec := Create(ctx, "acpi/ec.asl") defer ec.Close() + Add_gpl(ec) ec.WriteString("#include <ec/lenovo/h8/acpi/ec.asl>\n") KconfigBool["EC_LENOVO_PMH7"] = true diff --git a/util/autoport/ec_none.go b/util/autoport/ec_none.go index eb2b87c..bcb61bf 100644 --- a/util/autoport/ec_none.go +++ b/util/autoport/ec_none.go @@ -4,6 +4,7 @@ ap := Create(ctx, "acpi/platform.asl") defer ap.Close() + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { diff --git a/util/autoport/main.go b/util/autoport/main.go index 1a9050a..e8436bd 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -825,9 +825,9 @@ dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } + Add_gpl(dsdt) dsdt.WriteString( ` - #include <acpi/acpi.h> DefinitionBlock( -- To view, visit https://review.coreboot.org/c/coreboot/+/45464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8078d8babf24feabb22856ee820ab45b7d466f62 Gerrit-Change-Number: 45464 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: [WIP]drivers: Replace set_vbe_mode_info_valid
by Patrick Rudolph (Code Review) 17 Dec '20

17 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39004 ) Change subject: [WIP]drivers: Replace set_vbe_mode_info_valid ...................................................................... [WIP]drivers: Replace set_vbe_mode_info_valid Replace set_vbe_mode_info_valid with fb_fill_framebuffer_info, as it doesn't need a complete edid struct s paramter. The platforms doesn't read an EDID anyway. Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/mainboard/emulation/qemu-armv7/mainboard.c M src/soc/nvidia/tegra210/dc.c 5 files changed, 33 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/39004/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index 2ec85ac..fed7754 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -30,6 +30,7 @@ */ #include <edid.h> +#include <framebuffer_info.h> #include "ast_drv.h" @@ -247,7 +248,12 @@ ast_hide_cursor(&crtc); /* Advertise new mode */ - set_vbe_mode_info_valid(&edid, fb.mmio_addr); + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (info) { + fb_fill_framebuffer_info(info, fb.mmio_addr, edid.x_resolution, + edid.y_resolution, edid.bytes_per_line, + edid.framebuffer_bits_per_pixel); + } /* Clear display */ memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index d9e4ce1..959d431 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -12,7 +12,6 @@ */ #include <stdint.h> -#include <edid.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> @@ -20,6 +19,7 @@ #include <device/pci_ops.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <framebuffer_info.h> /* VGA init. We use the Bochs VESA VBE extensions */ #define VBE_DISPI_IOPORT_INDEX 0x01CE @@ -65,7 +65,6 @@ static void bochs_init_linear_fb(struct device *dev) { - struct edid edid; int id, mem, bar; u32 addr; @@ -112,13 +111,11 @@ outb(0x20, 0x3c0); /* disable blanking */ - /* setup coreboot framebuffer */ - edid.mode.ha = width; - edid.mode.va = height; - edid.panel_bits_per_color = 8; - edid.panel_bits_per_pixel = 24; - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - set_vbe_mode_info_valid(&edid, addr); + /* Advertise new mode */ + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (info) { + fb_fill_framebuffer_info(info, addr, width, height, 4 * width, 24); + } } static void bochs_init_text_mode(struct device *dev) diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 6b1968c..8f048f9 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -13,13 +13,13 @@ */ #include <stdint.h> -#include <edid.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <framebuffer_info.h> static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES; static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES; @@ -311,14 +311,10 @@ vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext); write_hidden_dac (hidden_dac); - - struct edid edid; - edid.mode.ha = width; - edid.mode.va = height; - edid.panel_bits_per_color = 8; - edid.panel_bits_per_pixel = 24; - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - set_vbe_mode_info_valid(&edid, addr); + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (info) { + fb_fill_framebuffer_info(info, addr, width, height, 4 * width, 24); + } } static void cirrus_init_text_mode(struct device *dev) diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index 338cff9..22340b2 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -18,15 +18,14 @@ #include <device/device.h> #include <cbmem.h> #include <halt.h> -#include <edid.h> #include <device/mmio.h> #include <ramdetect.h> #include <symbols.h> +#include <framebuffer_info.h> static void init_gfx(void) { uint32_t *pl111; - struct edid edid; /* width is at most 4096 */ /* height is at most 1024 */ int width = 800, height = 600; @@ -42,12 +41,10 @@ write32(pl111 + 10, 0xff); write32(pl111 + 6, (5 << 1) | 0x801); - edid.framebuffer_bits_per_pixel = 32; - edid.bytes_per_line = width * 4; - edid.x_resolution = width; - edid.y_resolution = height; - - set_vbe_mode_info_valid(&edid, framebuffer); + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (info) { + fb_fill_framebuffer_info(info, framebuffer, width, height, 4 * width, 32); + } } static void mainboard_enable(struct device *dev) diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 46443cf..b4e3378 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -16,10 +16,10 @@ #include <console/console.h> #include <device/mmio.h> #include <stdint.h> -#include <edid.h> #include <device/device.h> #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> +#include <framebuffer_info.h> #include "chip.h" @@ -226,19 +226,13 @@ void pass_mode_info_to_payload( struct soc_nvidia_tegra210_config *config) { - struct edid edid; - - edid.mode.va = config->display_yres; - edid.mode.ha = config->display_xres; - edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel, 64); - - printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " - " x_res x y_res: %d x %d, size: %d\n", - __func__, edid.bytes_per_line, - edid.framebuffer_bits_per_pixel, - edid.x_resolution, edid.y_resolution, - (edid.bytes_per_line * edid.y_resolution)); - - set_vbe_mode_info_valid(&edid, 0); + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (info) { + uint32_t bytes_per_line = ALIGN_UP(config->display_xres * + DIV_ROUND_UP(config->framebuffer_bits_per_pixel, 8), 64); + //FIXME: Why not config->framebuffer_base? + fb_fill_framebuffer_info(info, 0, + config->display_xres, config->display_yres, + bytes_per_line, config->framebuffer_bits_per_pixel); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5 Gerrit-Change-Number: 39004 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

9 47

Change in coreboot[master]: mb/google/zork: Add Shuboz GPIO to proto support
by Kane Chen (Code Review) 17 Dec '20

17 Dec '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48002 ) Change subject: mb/google/zork: Add Shuboz GPIO to proto support ...................................................................... mb/google/zork: Add Shuboz GPIO to proto support 1. AGPIO5 to NC 2. AGPIO6 - EN_PWR_TOUCHPAD_R to HIGH 3. EGPIO141 to NC 4. EGPIO144 to NC BUG=b:none BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I51f291476e01982e1a3f92cd1b338a528434112d --- M src/mainboard/google/zork/variants/shuboz/Makefile.inc A src/mainboard/google/zork/variants/shuboz/gpio.c 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/48002/1 diff --git a/src/mainboard/google/zork/variants/shuboz/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/Makefile.inc index 295acd2..2a8f0f7 100644 --- a/src/mainboard/google/zork/variants/shuboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/shuboz/Makefile.inc @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-or-later subdirs-y += ./spd +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/shuboz/gpio.c b/src/mainboard/google/zork/variants/shuboz/gpio.c new file mode 100644 index 0000000..2ff5ae9 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/gpio.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> + +static const struct soc_amd_gpio bid_gpio_set_stage_ram[] = { + /* AGPIO_5 - NC */ + PAD_NC(GPIO_5), + /* AGPIO6 - EN_PWR_TOUCHPAD_R */ + PAD_GPO(GPIO_32, HIGH), + /* EGPIO141 - NC */ + PAD_NC(GPIO_141), + /* EGPIO144 - NC (etk5515 not used) */ + PAD_NC(GPIO_144), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(bid_gpio_set_stage_ram); + return bid_gpio_set_stage_ram; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51f291476e01982e1a3f92cd1b338a528434112d Gerrit-Change-Number: 48002 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/mediatek/mt8192: Do the dramc pinmux selection
by CK HU (Code Review) 16 Dec '20

16 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44701 to review the following change. Change subject: soc/mediatek/mt8192: Do the dramc pinmux selection ...................................................................... soc/mediatek/mt8192: Do the dramc pinmux selection Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 1 file changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/44701/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 9b1216c..08f3ea4 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -6,8 +6,108 @@ #include <string.h> #include <timer.h> +const u8 mrr_o1_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = { + [PINMUX_DSC] = { + [CHANNEL_A] = {0, 1, 7, 6, 4, 5, 2, 3, 9, 8, 11, 10, 14, 15, 13, 12}, + [CHANNEL_B] = {1, 0, 5, 6, 3, 2, 7, 4, 8, 9, 11, 10, 12, 14, 13, 15}, + }, + [PINMUX_LPBK] = { + }, + [PINMUX_EMCP] = { + [CHANNEL_A] = {1, 0, 3, 2, 4, 7, 6, 5,8, 9, 10, 14, 11, 15, 13, 12}, + [CHANNEL_B] = {0, 1, 4, 7, 3, 5, 6, 2,9, 8, 10, 12, 11, 14, 13, 15} + }, +}; + +static void set_rank_info_to_conf(const struct ddr_cali *cali) +{ + u8 value = ((cali->emi_config->cona_val >> 17) & 0x1) ? 0 : 1; + + SET32_BITFIELDS(&ch[0].ao.sa_reserve, + SA_RESERVE_MODE_RK0, cali->cbt_mode[RANK_0], + SA_RESERVE_MODE_RK1, cali->cbt_mode[RANK_1], + SA_RESERVE_SINGLE_RANK, value); +} + +static void get_dram_pinmux_sel(struct ddr_cali *cali) +{ + u32 value = (read32(&mtk_gpio->dram_pinmux_trapping) >> 19) & 0x1; + + if (value) + cali->pinmux_type = PINMUX_DSC; + else + cali->pinmux_type = PINMUX_EMCP; +} + +static void set_MRR_pinmux_mapping(const struct ddr_cali *cali) +{ + const u8 *map; + u32 bc_bak = dramc_get_broadcast(); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux1, + MRR_BIT_MUX1_MRR_BIT0_SEL, map[0], + MRR_BIT_MUX1_MRR_BIT1_SEL, map[1], + MRR_BIT_MUX1_MRR_BIT2_SEL, map[2], + MRR_BIT_MUX1_MRR_BIT3_SEL, map[3]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux2, + MRR_BIT_MUX2_MRR_BIT4_SEL, map[4], + MRR_BIT_MUX2_MRR_BIT5_SEL, map[5], + MRR_BIT_MUX2_MRR_BIT6_SEL, map[6], + MRR_BIT_MUX2_MRR_BIT7_SEL, map[7]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux3, + MRR_BIT_MUX3_MRR_BIT8_SEL, map[8], + MRR_BIT_MUX3_MRR_BIT9_SEL, map[9], + MRR_BIT_MUX3_MRR_BIT10_SEL, map[10], + MRR_BIT_MUX3_MRR_BIT11_SEL, map[11]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux4, + MRR_BIT_MUX4_MRR_BIT12_SEL, map[12], + MRR_BIT_MUX4_MRR_BIT13_SEL, map[13], + MRR_BIT_MUX4_MRR_BIT14_SEL, map[14], + MRR_BIT_MUX4_MRR_BIT15_SEL, map[15]); + } + dramc_set_broadcast(bc_bak); +} + +static void set_dqO1_pinmux_mapping(const struct ddr_cali *cali) +{ + const u8 *map; + u32 bc_bak = dramc_get_broadcast(); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl0, + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0, map[0], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1, map[1], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2, map[2], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3, map[3], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4, map[4], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5, map[5], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6, map[6], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7, map[7]); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl1, + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8, map[8], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9, map[9], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10, map[10], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11, map[11], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12, map[12], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13, map[13], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14, map[14], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15, map[15]); + } + + dramc_set_broadcast(bc_bak); +} + void global_option_init(struct ddr_cali *cali) { + set_rank_info_to_conf(cali); + get_dram_pinmux_sel(cali); + set_MRR_pinmux_mapping(cali); + set_dqO1_pinmux_mapping(cali); } void dfs_init_for_calibration(const struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 Gerrit-Change-Number: 44701 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: arch/x86: Link gdt_init.S into bootblock
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47965 ) Change subject: arch/x86: Link gdt_init.S into bootblock ...................................................................... arch/x86: Link gdt_init.S into bootblock Followup work forces gdtptr and gdt towards the top of bootblock. They need to be realmode-addressable, i.e. within top 64 KiB or same segment with .reset. Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/c_start.S M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/32bit/entry32.inc 4 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47965/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 5157564..00917f0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -98,6 +98,7 @@ bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c +bootblock-y += gdt_init.S bootblock-y += id.S bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c @@ -160,8 +161,6 @@ romstage-y += boot.c romstage-y += post.c -# gdt_init.S is included by entry32.inc when romstage is the first C -# environment. romstage-y += gdt_init.S romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index a7af64f..8bebf87 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -142,10 +142,10 @@ /* This is the gdt for GCC part of coreboot. * It is different from the gdt in ASM part of coreboot - * which is defined in entry32.inc + * which is defined in gdt_init.S * * When the machine is initially started, we use a very simple - * gdt from ROM (that in entry32.inc) which only contains those + * gdt from ROM (that in gdt_init.S) which only contains those * entries we need for protected mode. * * When we're executing code from RAM, we want to do more complex diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2665cc6..5e90da1 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -124,7 +124,7 @@ ljmpl $ROM_CODE_SEG, $__protected_start /** - * The gdt is defined in entry32.inc, it has a 4 Gb code segment + * The gdt is defined in gdt_init.S, it has a 4 Gb code segment * at 0x08, and a 4 GB data segment at 0x10; */ __gdtptr: diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 8509448..873a809 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -4,7 +4,6 @@ #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> -#include <arch/x86/gdt_init.S> .code32 /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5 Gerrit-Change-Number: 47965 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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