coreboot-gerrit November 2020

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Change in coreboot[master]: [WIP] arch/x86: Combine bootblock linker scripts
by Kyösti Mälkki (Code Review) 14 Dec '20

14 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47597 ) Change subject: [WIP] arch/x86: Combine bootblock linker scripts ...................................................................... [WIP] arch/x86: Combine bootblock linker scripts Change-Id: Ie8629a89fa47a28db63ecc33c631b29ac5a77448 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- D src/arch/x86/id.ld M src/arch/x86/memlayout.ld D src/cpu/intel/fit/fit.ld D src/cpu/x86/16bit/entry16.ld M src/cpu/x86/16bit/reset16.ld 5 files changed, 24 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47597/1 diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld deleted file mode 100644 index b69a8dc..0000000 --- a/src/arch/x86/id.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; - .id (.): { - KEEP(*(.id)) - } -} diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index cbf887c..b487e48 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -40,10 +40,5 @@ #if ENV_BOOTBLOCK /* Bootblock specific scripts which provide more SECTION directives. */ -#include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> -#include <arch/x86/id.ld> -#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) -#include <cpu/intel/fit/fit.ld> -#endif #endif /* ENV_BOOTBLOCK */ diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld deleted file mode 100644 index 2e8749b..0000000 --- a/src/cpu/intel/fit/fit.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -SECTIONS { - . = 0xffffffc0; - .fit_pointer (.): { - KEEP(*(.fit_pointer)) - } -} diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld deleted file mode 100644 index bc456e7..0000000 --- a/src/cpu/x86/16bit/entry16.ld +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -gdtptr16_offset = gdtptr16 & 0xffff; -nullidt_offset = nullidt & 0xffff; - -/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with - * Startup IPI message without RAM. - */ -#if CONFIG(SIPI_VECTOR_IN_ROM) -_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary"); -ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; -#endif diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index e00e0b4..1c7e40f 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -1,5 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +gdtptr16_offset = gdtptr16 & 0xffff; +nullidt_offset = nullidt & 0xffff; + +/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with + * Startup IPI message without RAM. + */ +#if CONFIG(SIPI_VECTOR_IN_ROM) +_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary"); +ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; +#endif + /* * _ROMTOP : The top of the ROM used where we * need to put the reset vector. @@ -8,6 +19,19 @@ SECTIONS { /* Trigger an error if I have an unuseable start address */ _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); + + . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; + .id (.): { + KEEP(*(.id)) + } + +#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) + . = 0xffffffc0; + .fit_pointer (.): { + KEEP(*(.fit_pointer)) + } +#endif + _ROMTOP = 0xfffffff0; . = _ROMTOP; .reset . : { -- To view, visit https://review.coreboot.org/c/coreboot/+/47597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8629a89fa47a28db63ecc33c631b29ac5a77448 Gerrit-Change-Number: 47597 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance
by Patrick Rudolph (Code Review) 14 Dec '20

14 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39003 ) Change subject: [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance ...................................................................... [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance Replace all duplications of fill_fb_framebuffer and provide a single one. Should not change the current behaviour. TODO: Libgfxinit seems to expose one,too Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/oprom/realmode/x86.c M src/device/oprom/yabel/vbe.c M src/drivers/intel/fsp1_1/fsp_gop.c M src/drivers/intel/fsp2_0/graphics.c M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/xgi/common/xgi_coreboot.c M src/lib/Kconfig M src/lib/Makefile.inc 8 files changed, 111 insertions(+), 185 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/39003/1 diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 8ba0241..4c11e6f 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -23,6 +23,7 @@ #include <pc80/i8254.h> #include <string.h> #include <vbe.h> +#include <framebuffer_info.h> /* we use x86emu's register file representation */ #include <x86emu/regs.h> @@ -218,6 +219,7 @@ #if CONFIG(FRAMEBUFFER_SET_VESA_MODE) static vbe_mode_info_t mode_info; static int mode_info_valid; +static struct edid_fb_info *fb_info; static int vbe_mode_info_valid(void) { @@ -362,6 +364,28 @@ } vbe_set_mode(&mode_info); + + if (!vbe_mode_info_valid()) + return; + + if (!fb_info) { + fb_info = fb_new_framebuffer_info(); + } + if (fb_info) { + fb_fill_framebuffer_info_ex(fb_info, mode_info.vesa.phys_base_ptr, + le16_to_cpu(mode_info.vesa.x_resolution), + le16_to_cpu(mode_info.vesa.y_resolution), + le16_to_cpu(mode_info.vesa.bytes_per_scanline), + mode_info.vesa.bits_per_pixel, + mode_info.vesa.reserved_mask_pos, + mode_info.vesa.reserved_mask_size, + mode_info.vesa.red_mask_pos, + mode_info.vesa.red_mask_size, + mode_info.vesa.green_mask_pos, + mode_info.vesa.green_mask_size, + mode_info.vesa.blue_mask_pos, + mode_info.vesa.blue_mask_size); + } } void vbe_textmode_console(void) @@ -373,34 +397,6 @@ die("\nError: In %s function\n", __func__); } -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - if (!vbe_mode_info_valid()) - return -1; - - framebuffer->physical_address = mode_info.vesa.phys_base_ptr; - - framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution); - framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution); - framebuffer->bytes_per_line = - le16_to_cpu(mode_info.vesa.bytes_per_scanline); - framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel; - - framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos; - framebuffer->red_mask_size = mode_info.vesa.red_mask_size; - - framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos; - framebuffer->green_mask_size = mode_info.vesa.green_mask_size; - - framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos; - framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size; - - framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos; - framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size; - - return 0; -} - #endif void run_bios(struct device *dev, unsigned long addr) diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index a3d736f..2c05338 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -162,6 +162,7 @@ } static int mode_info_valid; +static struct edid_fb_info *fb_info; static int vbe_mode_info_valid(void) { @@ -747,33 +748,28 @@ mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE; vbe_get_mode_info(&mode_info); vbe_set_mode(&mode_info); -} -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ if (!vbe_mode_info_valid()) - return -1; + return; - framebuffer->physical_address = le32_to_cpu(mode_info.vesa.phys_base_ptr); - - framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution); - framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution); - framebuffer->bytes_per_line = le16_to_cpu(mode_info.vesa.bytes_per_scanline); - framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel; - - framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos; - framebuffer->red_mask_size = mode_info.vesa.red_mask_size; - - framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos; - framebuffer->green_mask_size = mode_info.vesa.green_mask_size; - - framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos; - framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size; - - framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos; - framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size; - - return 0; + if (!fb_info) { + fb_info = fb_new_framebuffer_info(); + } + if (fb_info) { + fb_fill_framebuffer_info_ex(fb_info, mode_info.vesa.phys_base_ptr, + le16_to_cpu(mode_info.vesa.x_resolution), + le16_to_cpu(mode_info.vesa.y_resolution), + le16_to_cpu(mode_info.vesa.bytes_per_scanline), + mode_info.vesa.bits_per_pixel, + mode_info.vesa.reserved_mask_pos, + mode_info.vesa.reserved_mask_size, + mode_info.vesa.red_mask_pos, + mode_info.vesa.red_mask_size, + mode_info.vesa.green_mask_pos, + mode_info.vesa.green_mask_size, + mode_info.vesa.blue_mask_pos, + mode_info.vesa.blue_mask_size); + } } void vbe_textmode_console(void) diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c index eb64151..9b555e6 100644 --- a/src/drivers/intel/fsp1_1/fsp_gop.c +++ b/src/drivers/intel/fsp1_1/fsp_gop.c @@ -12,10 +12,12 @@ */ #include <boot/coreboot_tables.h> +#include <bootstate.h> #include <console/console.h> +#include <framebuffer_info.h> #include <fsp/util.h> -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +static void fill_framebuffer_info(void *unused) { VOID *hob_list_ptr; hob_list_ptr = get_hob_list(); @@ -30,20 +32,15 @@ printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n"); vbt_gop = GET_GUID_HOB_DATA(vbt_hob); - framebuffer->physical_address = vbt_gop->FrameBufferBase; - framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution; - framebuffer->y_resolution = vbt_gop->GraphicsMode.VerticalResolution; - framebuffer->bytes_per_line = vbt_gop->GraphicsMode.PixelsPerScanLine - * 4; - framebuffer->bits_per_pixel = 32; - framebuffer->red_mask_pos = 16; - framebuffer->red_mask_size = 8; - framebuffer->green_mask_pos = 8; - framebuffer->green_mask_size = 8; - framebuffer->blue_mask_pos = 0; - framebuffer->blue_mask_size = 8; - framebuffer->reserved_mask_pos = 24; - framebuffer->reserved_mask_size = 8; + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (!info) + return; - return 0; + fb_fill_framebuffer_info(info, vbt_gop->FrameBufferBase, + vbt_gop->GraphicsMode.HorizontalResolution, + vbt_gop->GraphicsMode.VerticalResolution, + vbt_gop->GraphicsMode.PixelsPerScanLine * 4, + 32); } + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, fill_framebuffer_info, NULL); diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index be7afdb..f35556f 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -17,6 +17,7 @@ #include <fsp/util.h> #include <soc/intel/common/vbt.h> #include <types.h> +#include <framebuffer_info.h> enum pixel_format { pixel_rgbx_8bpc = 0, @@ -58,48 +59,18 @@ [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, }; -enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +__weak uintptr_t fsp_soc_get_igd_bar(void) { - size_t size; - const struct hob_graphics_info *ginfo; - const struct fsp_framebuffer *fbinfo; - - ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size); - - if (!ginfo) { - printk(BIOS_ALERT, "Graphics hand-off block not found\n"); - return CB_ERR; - } - - if (ginfo->pixel_format >= ARRAY_SIZE(fsp_framebuffer_format_map)) { - printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n", - ginfo->pixel_format); - return CB_ERR; - } - - fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format; - - framebuffer->physical_address = ginfo->framebuffer_base; - framebuffer->x_resolution = ginfo->horizontal_resolution; - framebuffer->y_resolution = ginfo->vertical_resolution; - framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4; - framebuffer->bits_per_pixel = 32; - framebuffer->red_mask_pos = fbinfo->red.pos; - framebuffer->red_mask_size = fbinfo->red.size; - framebuffer->green_mask_pos = fbinfo->green.pos; - framebuffer->green_mask_size = fbinfo->green.size; - framebuffer->blue_mask_pos = fbinfo->blue.pos; - framebuffer->blue_mask_size = fbinfo->blue.size; - framebuffer->reserved_mask_pos = fbinfo->rsvd.pos; - framebuffer->reserved_mask_size = fbinfo->rsvd.pos; - - return CB_SUCCESS; + return 0; } -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +static void fill_framebuffer_info(void *unused) { + size_t size; enum cb_err ret; uintptr_t framebuffer_bar; + const struct hob_graphics_info *ginfo; + const struct fsp_framebuffer *fbinfo; /* Pci enumeration happens after silicon init. * After enumeration graphic framebuffer base may be relocated. @@ -109,24 +80,44 @@ if (!framebuffer_bar) { printk(BIOS_ALERT, "Framebuffer BAR invalid\n"); - return -1; - } - - ret = fsp_fill_lb_framebuffer(framebuffer); - if (ret != CB_SUCCESS) { - printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n"); - return -1; + return; } /* Resource allocator can move the BAR around after FSP configures it */ - framebuffer->physical_address = framebuffer_bar; - printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", - framebuffer->physical_address); + printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", framebuffer_bar); - return 0; + ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size); + + if (!ginfo) { + printk(BIOS_ALERT, "Graphics hand-off block not found\n"); + return; + } + + if (ginfo->pixel_format >= ARRAY_SIZE(fsp_framebuffer_format_map)) { + printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n", + ginfo->pixel_format); + return; + } + + fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format; + + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (!info) + return; + + fb_fill_framebuffer_info_ex(fb_info, ginfo->framebuffer_base, + ginfo->horizontal_resolution, + ginfo->vertical_resolution, + ginfo->pixels_per_scanline * 4, + 32, + fbinfo->rsvd.pos, + fbinfo->rsvd.size, + fbinfo->red.pos, + fbinfo->red.size, + fbinfo->green.pos, + fbinfo->green.size, + fbinfo->blue.pos, + fbinfo->blue.size); } -__weak uintptr_t fsp_soc_get_igd_bar(void) -{ - return 0; -} +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, fill_framebuffer_info, NULL); diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 303bafe..15e7390 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -76,7 +76,6 @@ void *fsp_get_hob_list_ptr(void); const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size); const void *fsp_find_nv_storage_data(size_t *size); -enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]); void fsp_display_fvi_version_hob(void); void fsp_find_reserved_memory(struct range_entry *re); diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index d65e007..235cbe2 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -21,6 +21,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/vga.h> +#include <framebuffer_info.h> #include "xgi_coreboot.h" #include "vstruct.h" @@ -31,8 +32,7 @@ #include "vb_setmode.h" #include "XGI_main.c" -static int xgi_vbe_valid; -static struct lb_framebuffer xgi_fb; +static struct edid_fb_info *fb_info; int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) { @@ -359,43 +359,16 @@ XGIbios_mode[xgifb_info->mode_idx].bpp, xgifb_info->refresh_rate); - /* Set LinuxBIOS framebuffer information */ - xgi_vbe_valid = 1; - xgi_fb.physical_address = xgifb_info->video_base; - xgi_fb.x_resolution = xgifb_info->video_width; - xgi_fb.y_resolution = xgifb_info->video_height; - xgi_fb.bytes_per_line = - xgifb_info->video_width * xgifb_info->video_bpp; - xgi_fb.bits_per_pixel = xgifb_info->video_bpp; - - xgi_fb.reserved_mask_pos = 0; - xgi_fb.reserved_mask_size = 0; - switch (xgifb_info->video_bpp) { - case 32: - case 24: - /* packed into 4-byte words */ - xgi_fb.reserved_mask_pos = 24; - xgi_fb.reserved_mask_size = 8; - xgi_fb.red_mask_pos = 16; - xgi_fb.red_mask_size = 8; - xgi_fb.green_mask_pos = 8; - xgi_fb.green_mask_size = 8; - xgi_fb.blue_mask_pos = 0; - xgi_fb.blue_mask_size = 8; - break; - case 16: - /* packed into 2-byte words */ - xgi_fb.red_mask_pos = 11; - xgi_fb.red_mask_size = 5; - xgi_fb.green_mask_pos = 5; - xgi_fb.green_mask_size = 6; - xgi_fb.blue_mask_pos = 0; - xgi_fb.blue_mask_size = 5; - break; - default: - printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, - xgifb_info->video_bpp); - xgi_vbe_valid = 0; + /* Set framebuffer information */ + if (!fb_info) { + fb_info = fb_new_framebuffer_info(); + } + if (fb_info) { + fb_fill_framebuffer_info(fb_info, xgifb_info->video_base, + xgifb_info->video_width, + xgifb_info->video_height, + xgifb_info->video_width * xgifb_info->video_bpp, + xgifb_info->video_bpp); } } else { /* @@ -415,22 +388,6 @@ return 0; } - -static int vbe_mode_info_valid(void) -{ - return xgi_vbe_valid; -} - -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - if (!vbe_mode_info_valid()) - return -1; - - *framebuffer = xgi_fb; - - return 0; -} - struct xgifb_video_info *xgifb_video_info_ptr; struct xgifb_video_info *pci_get_drvdata(struct pci_dev *pdev) { diff --git a/src/lib/Kconfig b/src/lib/Kconfig index dd9974a..d831975 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -5,14 +5,6 @@ implementation. This activates a stub that logs the missing board reset and halts execution. -config NO_EDID_FILL_FB - bool - default y if !MAINBOARD_DO_NATIVE_VGA_INIT - help - Don't include default fill_lb_framebuffer() implementation. Select - this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides - its own fill_lb_framebuffer() implementation. - config RAMSTAGE_ADA bool help diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2333f64..a1fb8c2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -134,9 +134,7 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-y += edid.c -ifneq ($(CONFIG_NO_EDID_FILL_FB),y) ramstage-y += edid_fill_fb.c -endif ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -- To view, visit https://review.coreboot.org/c/coreboot/+/39003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4 Gerrit-Change-Number: 39003 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

10 68

Change in coreboot[master]: [NOTFORMERGE]: drivers/pc80/tpm: Probe for tpm multiple times
by Patrick Rudolph (Code Review) 14 Dec '20

14 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42510 ) Change subject: [NOTFORMERGE]: drivers/pc80/tpm: Probe for tpm multiple times ...................................................................... [NOTFORMERGE]: drivers/pc80/tpm: Probe for tpm multiple times Change-Id: Icdd675c0978173755d9ee18c20d8c314c1537a7a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/pc80/tpm/tis.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/42510/1 diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 185df34..ef556fe 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -393,7 +393,11 @@ if (vendor_dev_id) return 0; /* Already probed. */ - didvid = tpm_read_did_vid(0); + for (i = 0; i < 10000; i++) { + didvid = tpm_read_did_vid(0); + if (didvid && didvid != 0xffffffff) + break; + } if (!didvid || (didvid == 0xffffffff)) { printf("%s: No TPM device found\n", __FUNCTION__); return TPM_DRIVER_ERR; -- To view, visit https://review.coreboot.org/c/coreboot/+/42510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdd675c0978173755d9ee18c20d8c314c1537a7a Gerrit-Change-Number: 42510 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: WIP: coreboot: Enable ANALOGIX_ANX7625
by yongqiang niu (Code Review) 14 Dec '20

14 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46576 ) Change subject: WIP: coreboot: Enable ANALOGIX_ANX7625 ...................................................................... WIP: coreboot: Enable ANALOGIX_ANX7625 Enable ANALOGIX_ANX7625 to support display in coreboot Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I837e56ba4e98cc94c33484e79c4d5ff45a62becd --- M src/mainboard/google/asurada/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46576/1 diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index 7c93815..3a825b6 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -27,6 +27,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_ASURADA config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/46576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837e56ba4e98cc94c33484e79c4d5ff45a62becd Gerrit-Change-Number: 46576 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: WIP: soc/mediatek/mt8192: Add display controller driver
by yongqiang niu (Code Review) 14 Dec '20

14 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46577 ) Change subject: WIP: soc/mediatek/mt8192: Add display controller driver ...................................................................... WIP: soc/mediatek/mt8192: Add display controller driver The MT8192 SOC has a DISP (display controller) that supports overlay, read/write DMA, ... etc. The output of DISP goes to display interface DSI, DPI or DBI directly. BUG=b:80501386,b:155713214 BRANCH=none TEST=Boots correctly on asurada Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/ddp.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ddp.h 4 files changed, 485 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index b2a8a9e..119d999 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -59,6 +59,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c +ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/dsi.c dsi.c MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 diff --git a/src/soc/mediatek/mt8192/ddp.c b/src/soc/mediatek/mt8192/ddp.c new file mode 100644 index 0000000..0d5eab5 --- /dev/null +++ b/src/soc/mediatek/mt8192/ddp.c @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <edid.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +static void disp_config_main_path_connection(void) +{ + /* ovl0->ovl0_2l */ + write32(&mmsys_cfg->mmsys_ovl_mout_en, + (DISP_OVL0_GO_BG | DISP_OVL0_2L_GO_BLEND)); + write32(&mmsys_cfg->ovl0_2l_mout_en, OVL0_MOUT_EN_DISP_RDMA0); + write32(&mmsys_cfg->rdma0_sel_in, RDMA0_SEL_IN_OVL0_2L); + write32(&mmsys_cfg->rdma0_sout_sel, RDMA0_SOUT_COLOR0); + write32(&mmsys_cfg->ccorr0_sout_sel, CCORR0_SOUT_AAL0); + write32(&mmsys_cfg->aal0_sel_in, AAL0_SEL_IN_CCORR0); + write32(&mmsys_cfg->dither0_mout_en, DITHER0_MOUT_DSI0); + write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_bgclr_in_sel(u32 idx) +{ + setbits32(&disp_ovl[idx]->datapath_con, BIT(2)); +} + +static void ovl_layer_smi_id_en(u32 idx) +{ + printk(BIOS_INFO, "%s\n", __func__); + + setbits32(&disp_ovl[idx]->datapath_con, BIT(0)); +} + +static void ccorr_config(u32 width, u32 height) +{ + struct disp_ccorr_regs *const regs = disp_ccorr; + int enable_relay = 0; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) { + setbits32(&regs->cfg, PQ_RELAY_MODE); + clrbits32(&regs->cfg, PQ_ENGINE_EN); + } else { + clrbits32(&regs->cfg, PQ_RELAY_MODE); + setbits32(&regs->cfg, PQ_ENGINE_EN); + } + + write32(&regs->en, PQ_EN); +} + +static void aal_config(u32 width, u32 height) +{ + struct disp_aal_regs *const regs = disp_aal; + int enable_relay = 1; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + write32(&regs->output_size, width << 16 | height); + + if (enable_relay) { + setbits32(&regs->cfg, PQ_RELAY_MODE); + clrbits32(&regs->cfg, PQ_ENGINE_EN); + } else { + clrbits32(&regs->cfg, PQ_RELAY_MODE); + setbits32(&regs->cfg, PQ_ENGINE_EN); + } + + write32(&regs->en, PQ_EN); +} + +static void gamma_config(u32 width, u32 height) +{ + struct disp_gamma_regs *const regs = disp_gamma; + int enable_relay = 0; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) + setbits32(&regs->cfg, PQ_RELAY_MODE); + else + clrbits32(&regs->cfg, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + +static void postmask_config(u32 width, u32 height) +{ + struct disp_postmask_regs *const regs = disp_postmask; + int enable_relay = 1; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) + setbits32(&regs->cfg, PQ_RELAY_MODE); + else + clrbits32(&regs->cfg, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + +static void dither_config(u32 width, u32 height) +{ + struct disp_dither_regs *const regs = disp_dither; + int enable_relay = 1; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) + setbits32(&regs->cfg, PQ_RELAY_MODE); + else + clrbits32(&regs->cfg, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 idx = 0; + u32 pixel_clk = width * height * vrefresh; + + printk(BIOS_INFO, "%s\n", __func__); + + for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) { + ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff); + ovl_layer_smi_id_en(idx); + } + + rdma_config(width, height, pixel_clk, 5 * KiB); + color_start(width, height); + ccorr_config(width, height); + aal_config(width, height); + gamma_config(width, height); + postmask_config(width, height); + dither_config(width, height); + disp_config_main_path_connection(); + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + + clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_ALL); + + clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + /* Turn off M4U port. */ + write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_DISP_POSTMASK0), 0); + write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0_HDR), 0); + write32((void *)(SMI_LARB0 + SMI_LARB_L0_OVL_RDMA0), 0); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + printk(BIOS_INFO, "%s display resolution: %dx%d@%d bpp %d\n", + __func__, width, height, vrefresh, bpp); + + if (!vrefresh) { + vrefresh = 60; + printk(BIOS_INFO, "%s invalid vrefresh %d\n", + __func__, vrefresh); + } + + main_disp_path_setup(width, height, vrefresh); + rdma_start(); + ovl_layer_config(fmt, bpp, width, height); + ovl_bgclr_in_sel(1); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index eac4a9a..198beaa 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -65,6 +65,19 @@ MSDC0_BASE = IO_PHYS + 0x01F60000, DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, MIPITX_BASE = IO_PHYS + 0x01E50000, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_MUTEX_BASE = IO_PHYS + 0x04001000, + SMI_BASE = IO_PHYS + 0x04002000, + SMI_LARB0 = IO_PHYS + 0x04003000, + DISP_OVL0_BASE = IO_PHYS + 0x04005000, /* ovl0 */ + DISP_OVL1_BASE = IO_PHYS + 0x04006000, /* ovl0_2l */ + DISP_RDMA0_BASE = IO_PHYS + 0x04007000, + DISP_COLOR0_BASE = IO_PHYS + 0x04009000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400A000, + DISP_AAL0_BASE = IO_PHYS + 0x0400B000, + DISP_GAMMA0_BASE = IO_PHYS + 0x0400C000, + DISP_POSTMASK0_BASE = IO_PHYS + 0x0400D000, + DISP_DITHER0_BASE = IO_PHYS + 0x0400E000, DSI0_BASE = IO_PHYS + 0x04010000, }; diff --git a/src/soc/mediatek/mt8192/include/soc/ddp.h b/src/soc/mediatek/mt8192/include/soc/ddp.h new file mode 100644 index 0000000..18b2e27 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/ddp.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MT8183_SOC_DDP_H_ +#define _MT8183_SOC_DDP_H_ + +#include <soc/addressmap.h> +#include <soc/ddp_common.h> +#include <types.h> + +#define MAIN_PATH_OVL_NR 2 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10C; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11C[33]; /* 0x11C */ + u32 mmsys_cg_con2; /* 0x1A0 */ + u32 mmsys_cg_set2; /* 0x1A4 */ + u32 mmsys_cg_clr2; /* 0x1A8 */ + u32 reserved_0x1AC[853]; /* 0x1AC */ + u32 reserved_0xF00; /* 0xF00 */ + u32 mmsys_ovl_mout_en; /* 0xF04 */ + u32 reserved_0xF08; /* 0xF08 */ + u32 reserved_0xF0C; /* 0xF0C */ + u32 reserved_0xF10; /* 0xF10 */ + u32 reserved_0xF14; /* 0xF14 */ + u32 ovl0_2l_mout_en; /* 0xF18 */ + u32 ovl0_mout_en; /* 0xF1C */ + u32 reserved_0xF20; /* 0xF20 */ + u32 reserved_0xF24; /* 0xF24 */ + u32 reserved_0xF28; /* 0xF28 */ + u32 rdma0_sel_in; /* 0xF2C */ + u32 rdma0_sout_sel; /* 0xF30 */ + u32 ccorr0_sout_sel; /* 0xF34 */ + u32 aal0_sel_in; /* 0xF38 */ + u32 dither0_mout_en; /* 0xF3C*/ + u32 dsi0_sel_in; /* 0xF40*/ +}; + +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110); +check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0); +check_member(mmsys_cfg_regs, mmsys_ovl_mout_en, 0xF04); +check_member(mmsys_cfg_regs, ovl0_2l_mout_en, 0xF18); +check_member(mmsys_cfg_regs, dsi0_sel_in, 0xF40); +static struct mmsys_cfg_regs *const mmsys_cfg = + (void *)MMSYS_BASE; + + +/* DISP_REG_CONFIG_MMSYS_CG_CON0 + Configures free-run clock gating 0 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON0_DISP_MUTEX0 = BIT(0), + CG_CON0_DISPSYS_CONFIG = BIT(1), + CG_CON0_DISP_OVL0 = BIT(2), + CG_CON0_DISP_RDMA0 = BIT(3), + CG_CON0_DISP_OVL0_2L = BIT(4), + CG_CON0_DISP_AAL0 = BIT(8), + CG_CON0_DISP_CCORR0 = BIT(9), + CG_CON0_DISP_DITHER0 = BIT(10), + CG_CON0_SMI_INFRA = BIT(11), + CG_CON0_DISP_GAMMA0 = BIT(12), + CG_CON0_DISP_POSTMASK0 = BIT(13), + CG_CON0_DISP_DSI0 = BIT(15), + CG_CON0_DISP_COLOR0 = BIT(16), + CG_CON0_SMI_COMMON = BIT(17), + + CG_CON0_SMI_GALS = BIT(27), + CG_CON0_DISP_ALL = CG_CON0_SMI_INFRA | + CG_CON0_SMI_COMMON | + CG_CON0_SMI_GALS | + CG_CON0_DISP_MUTEX0 | + CG_CON0_DISPSYS_CONFIG | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_OVL0_2L | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_DISP_GAMMA0 | + CG_CON0_DISP_POSTMASK0 | + CG_CON0_DISP_DSI0 | + CG_CON0_DISP_COLOR0, + CG_CON0_ALL = 0xffffffff +}; + +/* DISP_REG_CONFIG_MMSYS_CG_CON1 + Configures free-run clock gating 1 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON1_SMI_IOMMU = BIT(0), + CG_CON1_DISP_ALL = CG_CON1_SMI_IOMMU, + CG_CON1_ALL = 0xffffffff +}; + +enum { + CG_CON2_DSI_DSI0 = BIT(0), + CG_CON2_DPI_DPI0 = BIT(8), + CG_CON2_MM_26MHZ = BIT(24), + CG_CON2_DISP_ALL = CG_CON2_DSI_DSI0 | + CG_CON2_MM_26MHZ, + CG_CON2_ALL = 0xffffffff +}; + + +enum { + DISP_OVL0_GO_BLEND = BIT(0), + DISP_OVL0_GO_BG = BIT(1), + DISP_OVL0_2L_GO_BLEND = BIT(2), + DISP_OVL0_2L_GO_BG = BIT(3), + OVL0_MOUT_EN_DISP_RDMA0 = BIT(0), + DITHER0_MOUT_DSI0 = BIT(0), +}; + +enum { + RDMA0_SEL_IN_OVL0_2L = 0x3, + RDMA0_SOUT_COLOR0 = 0x1, + CCORR0_SOUT_AAL0 = 0x1, + AAL0_SEL_IN_CCORR0 = 0x1, + DSI0_SEL_IN_DITHER0 = 0x1, +}; + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[12]; +}; + +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; + +enum { + MUTEX_MOD_DISP_OVL0 = BIT(0), + MUTEX_MOD_DISP_OVL0_2L = BIT(1), + MUTEX_MOD_DISP_RDMA0 = BIT(2), + MUTEX_MOD_DISP_COLOR0 = BIT(4), + MUTEX_MOD_DISP_CCORR0 = BIT(5), + MUTEX_MOD_DISP_AAL0 = BIT(6), + MUTEX_MOD_DISP_GAMMA0 = BIT(7), + MUTEX_MOD_DISP_POSTMASK0 = BIT(8), + MUTEX_MOD_DISP_DITHER0 = BIT(9), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | + MUTEX_MOD_DISP_OVL0_2L | + MUTEX_MOD_DISP_RDMA0 | + MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | + MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0 | + MUTEX_MOD_DISP_POSTMASK0 | + MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +struct disp_ccorr_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[27]; + u32 shadow; +}; +check_member(disp_ccorr_regs, shadow, 0xA0); + +struct disp_gamma_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_gamma_regs, size, 0x30); + +struct disp_aal_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[47]; + u32 shadow; + u32 reserved3[249]; + u32 output_size; +}; +check_member(disp_aal_regs, shadow, 0xF0); +check_member(disp_aal_regs, output_size, 0x4D8); + +struct disp_postmask_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 reserved0[4]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_postmask_regs, size, 0x30); + +struct disp_dither_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[51]; + u32 shadow; +}; +check_member(disp_dither_regs, shadow, 0x100); + +enum { + PQ_EN = BIT(0), + PQ_RELAY_MODE = BIT(0), + PQ_ENGINE_EN = BIT(1), +}; + +static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; + +static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE; + +static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; + +static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE; + +enum { + SMI_LARB_PORT_L0_DISP_POSTMASK0 = 0x380, + SMI_LARB_PORT_L0_OVL_RDMA0_HDR = 0x384, + SMI_LARB_L0_OVL_RDMA0 = 0x388, +}; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154 Gerrit-Change-Number: 46577 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: WIP: coreboot: Add dsi file
by yongqiang niu (Code Review) 14 Dec '20

14 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46574 ) Change subject: WIP: coreboot: Add dsi file ...................................................................... WIP: coreboot: Add dsi file Add dsi APIs for coreboot display Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dsi.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 4 files changed, 129 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 04d57dc..b2a8a9e 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -59,6 +59,8 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c +ramstage-y += ../common/dsi.c dsi.c + MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 cbfs-files-y += dpm.dm diff --git a/src/soc/mediatek/mt8192/dsi.c b/src/soc/mediatek/mt8192/dsi.c new file mode 100644 index 0000000..9f54f49 --- /dev/null +++ b/src/soc/mediatek/mt8192/dsi.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <delay.h> +#include <soc/dsi.h> +#include <soc/pll.h> + +void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes) +{ + unsigned int txdiv0, txdiv1; + u64 pcw; + + if (data_rate >= 2000 * MHz) { + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000 * MHz) { + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500 * MHz) { + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250 * MHz) { + /* (data_rate == 250MHz) is a special case that should go to the + else-block below (txdiv0 = 4) */ + txdiv0 = 3; + txdiv1 = 0; + } else { + /* MIN = 125 */ + assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz); + txdiv0 = 4; + txdiv1 = 0; + } + + clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); + setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1); + pcw <<= 24; + pcw /= CLK26M_HZ; + + write32(&mipi_tx->pll_con0, pcw); + clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); + udelay(30); + setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + write32(&mipi_tx->lane_con, 0x3fff0180); + udelay(40); + write32(&mipi_tx->lane_con, 0x3fff00c0); + + /* Switch OFF each Lane */ + clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); + + setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); +} + +void mtk_dsi_reset(void) +{ + write32(&dsi0->dsi_force_commit, + DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS); + write32(&dsi0->dsi_con_ctrl, 1); + write32(&dsi0->dsi_con_ctrl, 0); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 3fd2bca..eac4a9a 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -64,6 +64,8 @@ MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, MSDC0_BASE = IO_PHYS + 0x01F60000, DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, + MIPITX_BASE = IO_PHYS + 0x01E50000, + DSI0_BASE = IO_PHYS + 0x04010000, }; #endif diff --git a/src/soc/mediatek/mt8192/include/soc/dsi.h b/src/soc/mediatek/mt8192/include/soc/dsi.h new file mode 100644 index 0000000..4535d90 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dsi.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8183_DSI_H +#define SOC_MEDIATEK_MT8183_DSI_H + +#include <soc/dsi_common.h> + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a Gerrit-Change-Number: 46574 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: WIP: soc/mediatek/mt8192: add i2c driver support
by wang qii (Code Review) 14 Dec '20

14 Dec '20

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47800 ) Change subject: WIP: soc/mediatek/mt8192: add i2c driver support ...................................................................... WIP: soc/mediatek/mt8192: add i2c driver support Add i2c controller driver code TEST=Boots correctly on MT8192P1 Signed-off-by: Qii Wang <qii.wang(a)mediatek.com> Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368 --- M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/i2c.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/i2c.h 6 files changed, 285 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47800/1 diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index 87925ba..e028ab1 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -10,14 +10,34 @@ #include <soc/i2c.h> #include <device/i2c_simple.h> -static inline void i2c_dma_reset(struct mt_i2c_dma_regs *dma_regs) +static inline void i2c_hw_reset(uint8_t bus) { - write32(&dma_regs->dma_rst, 0x1); - udelay(50); - write32(&dma_regs->dma_rst, 0x2); - udelay(50); - write32(&dma_regs->dma_rst, 0x0); - udelay(50); + struct mt_i2c_regs *regs; + struct mt_i2c_dma_regs *dma_regs; + + regs = mtk_i2c_bus_controller[bus].i2c_regs; + dma_regs = mtk_i2c_bus_controller[bus].i2c_dma_regs; + + if (mtk_i2c_bus_controller[bus].mt_i2c_flag == I2C_APDMA_ASYNC) { + write32(&dma_regs->dma_rst, I2C_DMA_WARM_RST); + udelay(10); + write32(&dma_regs->dma_rst, I2C_DMA_CLR_FLAG); + udelay(10); + write32(&dma_regs->dma_rst, (I2C_DMA_HARD_RST | I2C_DMA_HANDSHAKE_RST)); + write32(&regs->softreset, (I2C_SOFT_RST | I2C_HANDSHAKE_RST)); + udelay(10); + write32(&dma_regs->dma_rst, I2C_DMA_CLR_FLAG); + write32(&regs->softreset, I2C_CLR_FLAG); + } else { + write32(&regs->softreset, I2C_SOFT_RST); + + write32(&dma_regs->dma_rst, I2C_DMA_WARM_RST); + udelay(50); + write32(&dma_regs->dma_rst, I2C_DMA_HARD_RST); + udelay(50); + write32(&dma_regs->dma_rst, I2C_DMA_CLR_FLAG); + udelay(50); + } } static inline void mtk_i2c_dump_info(struct mt_i2c_regs *regs) @@ -47,6 +67,7 @@ { uint32_t ret_code = I2C_OK; uint16_t status; + uint16_t dma_sync = 0; uint32_t time_out_val = 0; uint8_t addr; uint32_t write_len = 0; @@ -62,6 +83,12 @@ addr = seg[0].slave; + if (mtk_i2c_bus_controller[bus].mt_i2c_flag == I2C_APDMA_ASYNC) { + dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; + if (mode == I2C_WRITE_READ_MODE) + dma_sync |= I2C_DMA_DIR_CHANGE; + } + switch (mode) { case I2C_WRITE_MODE: assert(seg[0].len > 0 && seg[0].len <= 255); @@ -113,7 +140,7 @@ write32(&regs->slave_addr, addr << 1); /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_TX); + write32(&dma_regs->dma_con, I2C_DMA_CON_TX | dma_sync); write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); write32(&dma_regs->dma_tx_len, write_len); break; @@ -132,7 +159,7 @@ write32(&regs->slave_addr, (addr << 1 | 0x1)); /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_RX); + write32(&dma_regs->dma_con, I2C_DMA_CON_RX | dma_sync); write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); write32(&dma_regs->dma_rx_len, read_len); break; @@ -154,7 +181,7 @@ write32(&regs->slave_addr, addr << 1); /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG | dma_sync); write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); write32(&dma_regs->dma_tx_len, write_len); write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); @@ -206,9 +233,7 @@ I2C_TRANSAC_COMP); /* reset the i2c controller for next i2c transfer. */ - write32(&regs->softreset, 0x1); - - i2c_dma_reset(dma_regs); + i2c_hw_reset(bus); return ret_code; } diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index 0100e26..d2da27e 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -38,6 +38,12 @@ I2C_DMA_INT_FLAG_NONE = 0x0, I2C_DMA_CLR_FLAG = 0x0, I2C_DMA_FLUSH_FLAG = 0x1, + I2C_DMA_ASYNC_MODE = 0x0004, + I2C_DMA_SKIP_CONFIG = 0x0010, + I2C_DMA_DIR_CHANGE = 0x0200, + I2C_DMA_WARM_RST = 0x1, + I2C_DMA_HARD_RST = 0x2, + I2C_DMA_HANDSHAKE_RST = 0x4, }; enum { @@ -46,6 +52,11 @@ I2C_CONTROL_MASK = (0x3f << 1) }; +enum { + I2C_APDMA_NOASYNC = 0, + I2C_APDMA_ASYNC = 1, +}; + /* Register mask */ enum { I2C_HS_NACKERR = (1 << 2), @@ -53,6 +64,13 @@ I2C_TRANSAC_COMP = (1 << 0), }; +/* reset bits */ +enum { + I2C_CLR_FLAG = 0x0, + I2C_SOFT_RST = 0x1, + I2C_HANDSHAKE_RST = 0x20, +}; + /* i2c control bits */ enum { ASYNC_MODE = (1 << 9), @@ -80,6 +98,7 @@ struct mtk_i2c { struct mt_i2c_regs *i2c_regs; struct mt_i2c_dma_regs *i2c_dma_regs; + uint32_t mt_i2c_flag; }; extern struct mtk_i2c mtk_i2c_bus_controller[]; diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 5d1c0ae..3980b5a 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -5,6 +5,7 @@ bootblock-y += eint_event.c bootblock-y += flash_controller.c bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -20,6 +21,7 @@ verstage-y += ../common/auxadc.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c @@ -32,6 +34,7 @@ romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c +romstage-y += ../common/i2c.c i2c.c romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c @@ -42,6 +45,7 @@ ramstage-y += ../common/auxadc.c ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += dpm.c diff --git a/src/soc/mediatek/mt8192/i2c.c b/src/soc/mediatek/mt8192/i2c.c new file mode 100644 index 0000000..6b9c1ea --- /dev/null +++ b/src/soc/mediatek/mt8192/i2c.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <soc/pll.h> +#include <soc/i2c.h> +#include <soc/gpio.h> + +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) +struct mtk_i2c mtk_i2c_bus_controller[] = { + /* i2c0 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x250000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c1 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x70000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x80), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c2 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x71000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x100), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c3 setting */ + { + .i2c_regs = (void *)(I2C_BASE), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x280), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c4 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x72000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x300), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c5 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x150000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c6 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x251000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x500), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c7 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x50000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c8 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x51000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x700), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c9 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x52000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x880), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, +}; + +#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + { + PAD_FUNC(SDA6, SDA6), + PAD_FUNC(SCL6, SCL6), + }, + { + PAD_FUNC(SDA7, SDA7), + PAD_FUNC(SCL7, SCL7), + }, + { + PAD_FUNC(SDA8, SDA8), + PAD_FUNC(SCL8, SCL8), + }, + { + PAD_FUNC(SDA9, SDA9), + PAD_FUNC(SCL9, SCL9), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +static void mtk_i2c_speed_init(uint8_t bus) +{ + uint8_t step_div; + const uint8_t clock_div = 5; + const uint8_t sample_div = 1; + uint32_t i2c_freq; + + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (400 * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && i2c_freq <= 400 * KHz && + i2c_freq >= 380 * KHz); + + /* Init i2c bus Timing register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming, + (sample_div - 1) << 6 | (step_div - 1)); + + /* Init i2c bus clock_div register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div, + clock_div - 1); +} + +void mtk_i2c_bus_init(uint8_t bus) +{ + mtk_i2c_speed_init(bus); + mtk_i2c_set_gpio_pinmux(bus); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index eb75823..68ea6a0 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -30,6 +30,7 @@ PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + I2C_DMA_BASE = IO_PHYS + 0x00217080, EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, @@ -51,6 +52,7 @@ UFSHCI_BASE = IO_PHYS + 0x01270000, EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, + I2C_BASE = IO_PHYS + 0x01CB0000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, IOCFG_BL_BASE = IO_PHYS + 0x01D30000, IOCFG_BR_BASE = IO_PHYS + 0x01D40000, diff --git a/src/soc/mediatek/mt8192/include/soc/i2c.h b/src/soc/mediatek/mt8192/include/soc/i2c.h new file mode 100644 index 0000000..72a9af1 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/i2c.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_I2C_H +#define SOC_MEDIATEK_MT8192_I2C_H + +#include <soc/i2c_common.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus); + +#endif /* SOC_MEDIATEK_MT8192_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368 Gerrit-Change-Number: 47800 Gerrit-PatchSet: 1 Gerrit-Owner: wang qii <Qii.Wang(a)mediatek.com> Gerrit-MessageType: newchange

5 37

Change in coreboot[master]: soc/amd/common: Refactor ACPIMMIO posted writes
by Kyösti Mälkki (Code Review) 12 Dec '20

12 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42825 ) Change subject: soc/amd/common: Refactor ACPIMMIO posted writes ...................................................................... soc/amd/common: Refactor ACPIMMIO posted writes Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/i2c.c M src/soc/amd/stoneyridge/i2c.c 3 files changed, 8 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42825/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 2775b52..8546da9 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -369,12 +369,6 @@ write32(gpio_ctrl_ptr(gpio_num), value); } -static inline void gpio_write32_rb(uint8_t gpio_num, uint32_t value) -{ - write32(gpio_ctrl_ptr(gpio_num), value); - read32(gpio_ctrl_ptr(gpio_num)); -} - /* GPIO bank 0 */ static inline uint8_t gpio0_read8(uint8_t reg) { diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 881278f..61a4f8a 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -161,9 +161,11 @@ static void restore_i2c_pin_registers(uint8_t gpio, struct soc_amd_i2c_save *save_table) { + /* Write and flush posted writes. */ iomux_write8(gpio, save_table->mux_value); - iomux_read8(gpio); - gpio_write32_rb(gpio, save_table->control_value); + iomux_read8(0); + gpio_write32(gpio, save_table->control_value); + gpio_read32(0); } /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 0327028..cd42cda 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -144,9 +144,11 @@ static void restore_i2c_pin_registers(uint8_t gpio, struct soc_amd_i2c_save *save_table) { + /* Write and flush posted writes. */ iomux_write8(gpio, save_table->mux_value); - iomux_read8(gpio); - gpio_write32_rb(gpio, save_table->control_value); + iomux_read8(0); + gpio_write32(gpio, save_table->control_value); + gpio_read32(0); } /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Gerrit-Change-Number: 42825 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: [TESTONLY] Revert "src/amd/common: Exclude biosram from psp_verstage"
by Kyösti Mälkki (Code Review) 12 Dec '20

12 Dec '20

Hello build bot (Jenkins), Raul Rangel, Martin Roth, Patrick Georgi, Julius Werner, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43067 to review the following change. Change subject: [TESTONLY] Revert "src/amd/common: Exclude biosram from psp_verstage" ...................................................................... [TESTONLY] Revert "src/amd/common: Exclude biosram from psp_verstage" This reverts commit f38af663d2c2c854859715803da249e6c24032db. I just want to see where the build fails. Change-Id: I0a995301404b67224be6addbeebf984c4b5c47d5 --- M src/soc/amd/common/block/acpimmio/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/43067/1 diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 553d9e2..69253b9 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -6,7 +6,7 @@ smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -- To view, visit https://review.coreboot.org/c/coreboot/+/43067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a995301404b67224be6addbeebf984c4b5c47d5 Gerrit-Change-Number: 43067 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()
by Julius Werner (Code Review) 12 Dec '20

12 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39306 to review the following change. Change subject: cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() ...................................................................... cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() This patch introduces two new CBFS API functions which are equivalent to cbfs_map() and cbfs_load(), respectively, with the difference that they always operate on the read-only CBFS region ("COREBOOT" FMAP section). Use it to replace some of the simple cases that needed to use cbfs_locate_file_in_region(). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f --- M src/drivers/pc80/rtc/option.c M src/include/cbfs.h M src/lib/cbfs.c M src/northbridge/intel/haswell/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/quark/romstage/romstage.c 6 files changed, 60 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39306/1 diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 4789b15..1f9abb5 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -60,36 +60,28 @@ return CB_SUCCESS; } -static enum cb_err locate_cmos_layout(struct region_device *rdev) +static struct cmos_option_table *get_cmos_layout(struct region_device *rdev) { - uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - MAYBE_STATIC_BSS struct cbfsf fh = {}; + MAYBE_STATIC_BSS struct cmos_option_table ct = NULL; /* * In case VBOOT is enabled and this function is called from SMM, * we have multiple CMOS layout files and to locate them we'd need to * include VBOOT into SMM... * - * Support only one CMOS layout in the 'COREBOOT' region for now. + * Support only one CMOS layout in the RO CBFS for now. */ - if (!region_device_sz(&(fh.data))) { - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - } - - cbfs_file_data(rdev, &fh); - - return CB_SUCCESS; + if (!ct) + ct = cbfs_ro_map("cmos_layout.bin", NULL); + if (!ct) + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); + return ct; } enum cb_err cmos_get_option(void *dest, const char *name) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; size_t namelen; int found = 0; @@ -97,16 +89,9 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -119,19 +104,15 @@ } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) return CB_CMOS_CHECKSUM_INVALID; - } - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); +} + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); +} return CB_SUCCESS; } @@ -179,7 +160,6 @@ enum cb_err cmos_set_option(const char *name, void *value) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -188,16 +168,9 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -210,7 +183,6 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -219,18 +191,13 @@ length = MAX(strlen((const char *)value) * 8, ce->length - 8); /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); return CB_SUCCESS; } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index cc61b16..8cd5713 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -36,9 +36,12 @@ NOTE: Since this may return a direct pointer to memory-mapped hardware, compressed files are NOT transparently decompressed (unlike cbfs_load()). */ void *cbfs_map(const char *name, size_t *size); -/* Removes a mapping previously allocated with cbfs_map(). Should try to unmap - mappings in strict LIFO order where possible, since mapping backends often - don't support more complicated cases. */ +/* Like cbfs_map(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG_VBOOT is enabled. */ +void *cbfs_ro_map(const char *name, size_t *size); +/* Removes a previously allocated CBFS mapping. Should try to unmap mappings in + strict LIFO order where possible, since mapping backends often don't support + more complicated cases. */ int cbfs_unmap(void *mapping); /* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, @@ -47,6 +50,9 @@ success or 0 on error. File will get decompressed as necessary. Same decompression requirements as cbfs_load_and_decompress(). */ size_t cbfs_load(const char *name, void *buf, size_t buf_size); +/* Like cbfs_load(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG_VBOOT is enabled. */ +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size); /* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes * large |buffer|, decompressing it according to |compression| in the process. * Returns the decompressed file size, or 0 on error. diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c3660aa..ba50c34 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -79,9 +79,9 @@ return 0; } -void *cbfs_map(const char *name, size_t *size) +static void *_cbfs_map(const char *name, size_t *size, bool force_ro) { - const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); union cbfs_mdata mdata; size_t data_offset; @@ -96,6 +96,16 @@ return rdev_mmap(&cbd->rdev, data_offset, data_size); } +void *cbfs_map(const char *name, size_t *size) +{ + return _cbfs_map(name, size, false); +} + +void *cbfs_ro_map(const char *name, size_t *size) +{ + return _cbfs_map(name, size, true); +} + int cbfs_unmap(void *mapping) { /* This works because munmap() only works on the root rdev and never @@ -215,7 +225,8 @@ return prog_entry(&stage); } -size_t cbfs_load(const char *name, void *buf, size_t buf_size) +static size_t _cbfs_load(const char *name, void *buf, size_t buf_size, + bool force_ro) { const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); union cbfs_mdata mdata; @@ -238,6 +249,16 @@ compression); } +size_t cbfs_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, false); +} + +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, true); +} + size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) { struct cbfs_stage stage; diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 8267833..00211bd 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -118,8 +118,6 @@ void sdram_initialize(struct pei_data *pei_data) { unsigned long entry; - uint32_t type = CBFS_TYPE_MRC; - struct cbfsf f; printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); @@ -144,12 +142,11 @@ /* * Locate and call UEFI System Agent binary. The binary needs to be at * a fixed offset in the flash and can therefore only reside in the - * COREBOOT fmap region + * COREBOOT fmap region. We don't care about leaking the mapping. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) + entry = (unsigned long)cbfs_ro_map("mrc.bin", NULL); + if (!entry) die("mrc.bin not found!"); - /* We don't care about leaking the mapping */ - entry = (unsigned long)rdev_mmap_full(&f.data); if (entry) { int rv; asm volatile ( diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 3759c1f..bcf7148 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -43,8 +43,6 @@ struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; - struct cbfsf f; - uint32_t type = CBFS_TYPE_MRC; broadwell_fill_pei_data(pei_data); @@ -76,15 +74,10 @@ pei_data->saved_data_size = 0; } - /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) - die("mrc.bin not found!"); /* We don't care about leaking the mapping */ - entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); - if (entry == NULL) { - printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); - return; - } + entry = cbfs_ro_map("mrc.bin", NULL); + if (entry == NULL) + die("mrc.bin not found!"); printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4ac580e..3e08663 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -63,29 +63,16 @@ void *locate_rmu_file(size_t *rmu_file_len) { - struct cbfsf fh; size_t fsize; void *rmu_data; - uint32_t type; /* Locate the rmu.bin file in the read-only region of the flash */ - type = CBFS_TYPE_RAW; - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "rmu.bin", &type)) + rmu_data = cbfs_ro_map("rmu.bin", &fsize); + if (!rmu_data) return NULL; - /* Get the file size */ - fsize = region_device_sz(&fh.data); if (rmu_file_len != NULL) *rmu_file_len = fsize; - /* Get the data address */ - rmu_data = rdev_mmap(&fh.data, 0, fsize); - - /* Since the SPI flash is directly mapped into memory, we do not need - * the mapping provided by the rdev service. Unmap the file to prevent - * a memory leak. Return/leak the SPI flash address for the rmu.bin - * file data which will be directly accessed by FSP MemoryInit. - */ - rdev_munmap(&fh.data, rmu_data); return rmu_data; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f Gerrit-Change-Number: 39306 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 15

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