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Change in coreboot[master]: [WIP] soc/amd/common/block/acpimmio: Redo acpimmio for psp_verstage a...
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42523 ) Change subject: [WIP] soc/amd/common/block/acpimmio: Redo acpimmio for psp_verstage again ...................................................................... [WIP] soc/amd/common/block/acpimmio: Redo acpimmio for psp_verstage again Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/Makefile.inc M src/soc/amd/common/block/acpimmio/mmio_util.c D src/soc/amd/common/block/acpimmio/mmio_util_psp.c A src/soc/amd/common/block/acpimmio/psp_verstage_stub.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h D src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h 7 files changed, 67 insertions(+), 245 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/42523/1 diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 13864e4..28d78d5 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -13,5 +13,5 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO),y) verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += biosram.c verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += mmio_util.c -verstage-$(CONFIG_ARCH_VERSTAGE_ARM) += mmio_util_psp.c +verstage-$(CONFIG_ARCH_VERSTAGE_ARM) += mmio_util.c endif diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index c5f82f9..2bfa878 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -2,9 +2,12 @@ #include <types.h> #include <arch/io.h> -#include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> +#if CONSTANT_ACPIMMIO_BASE_ADDRESS +#include <amdblocks/acpimmio_map.h> +#endif + DECLARE_ACPIMMIO(acpimmio_sm_pci, SM_PCI); DECLARE_ACPIMMIO(acpimmio_gpio_100, GPIO_100); DECLARE_ACPIMMIO(acpimmio_smi, SMI); diff --git a/src/soc/amd/common/block/acpimmio/mmio_util_psp.c b/src/soc/amd/common/block/acpimmio/mmio_util_psp.c deleted file mode 100644 index 75f71e4..0000000 --- a/src/soc/amd/common/block/acpimmio/mmio_util_psp.c +++ /dev/null @@ -1,163 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/mmio.h> -#include <amdblocks/acpimmio.h> - -static uintptr_t iomux_bar; - -void iomux_set_bar(void *bar) -{ - iomux_bar = (uintptr_t)bar; -} - -u8 iomux_read8(u8 reg) -{ - return read8((void *)(iomux_bar + reg)); -} - -u16 iomux_read16(u8 reg) -{ - return read16((void *)(iomux_bar + reg)); -} - -u32 iomux_read32(u8 reg) -{ - return read32((void *)(iomux_bar + reg)); -} - -void iomux_write8(u8 reg, u8 value) -{ - write8((void *)(iomux_bar + reg), value); -} - -void iomux_write16(u8 reg, u16 value) -{ - write16((void *)(iomux_bar + reg), value); -} - -void iomux_write32(u8 reg, u32 value) -{ - write32((void *)(iomux_bar + reg), value); -} - -static uintptr_t misc_bar; - -void misc_set_bar(void *bar) -{ - misc_bar = (uintptr_t)bar; -} - -u8 misc_read8(u8 reg) -{ - return read8((void *)(misc_bar + reg)); -} - -u16 misc_read16(u8 reg) -{ - return read16((void *)(misc_bar + reg)); -} - -u32 misc_read32(u8 reg) -{ - return read32((void *)(misc_bar + reg)); -} - -void misc_write8(u8 reg, u8 value) -{ - write8((void *)(misc_bar + reg), value); -} - -void misc_write16(u8 reg, u16 value) -{ - write16((void *)(misc_bar + reg), value); -} - -void misc_write32(u8 reg, u32 value) -{ - write32((void *)(misc_bar + reg), value); -} - -static uintptr_t gpio_bar; - -void gpio_set_bar(void *bar) -{ - gpio_bar = (uintptr_t)bar; -} - -void *gpio_get_bar(void) -{ - return (void *)gpio_bar; -} - -static uintptr_t aoac_bar; - -void aoac_set_bar(void *bar) -{ - aoac_bar = (uintptr_t)bar; -} - -u8 aoac_read8(u8 reg) -{ - return read8((void *)(aoac_bar + reg)); -} - -void aoac_write8(u8 reg, u8 value) -{ - write8((void *)(aoac_bar + reg), value); -} - -static uintptr_t io_bar; - -void io_set_bar(void *bar) -{ - io_bar = (uintptr_t)bar; -} - -u8 io_read8(u16 reg) -{ - return read8((void *)(io_bar + reg)); -} - -void io_write8(u16 reg, u8 value) -{ - write8((void *)(io_bar + reg), value); -} - -/* PM registers are accessed a byte at a time via CD6/CD7 */ -uint8_t pm_io_read8(uint8_t reg) -{ - outb(reg, PM_INDEX); - return inb(PM_DATA); -} - -uint16_t pm_io_read16(uint8_t reg) -{ - return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); -} - -uint32_t pm_io_read32(uint8_t reg) -{ - return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); -} - -void pm_io_write8(uint8_t reg, uint8_t value) -{ - outb(reg, PM_INDEX); - outb(value, PM_DATA); -} - -void pm_io_write16(uint8_t reg, uint16_t value) -{ - pm_io_write8(reg, value & 0xff); - value >>= 8; - pm_io_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void pm_io_write32(uint8_t reg, uint32_t value) -{ - pm_io_write16(reg, value & 0xffff); - value >>= 16; - pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); -} diff --git a/src/soc/amd/common/block/acpimmio/psp_verstage_stub.c b/src/soc/amd/common/block/acpimmio/psp_verstage_stub.c new file mode 100644 index 0000000..9c74f8f --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/psp_verstage_stub.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpimmio.h> + +static void iomux_set_bar(void *bar) +{ + acpimmio_iomux_bar = bar; +} + +static void misc_set_bar(void *bar) +{ + acpimmio_misc_bar = bar; +} + +static void gpio_set_bar(void *bar) +{ + acpimmio_gpio0_bar = bar; +} + +static void aoac_set_bar(void *bar) +{ + acpimmio_aoac_bar = bar; +} + +static void io_set_bar(void *bar) +{ + acpimmio_io_bar = bar; +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 3caed11..3f00ae2 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -6,6 +6,40 @@ #include <device/mmio.h> #include <types.h> +/* For x86 base is constant, while PSP does mapping runtime. */ +#define CONSTANT_ACPIMMIO_BASE_ADDRESS ENV_X86 + +#if CONSTANT_ACPIMMIO_BASE_ADDRESS +#define MAYBE_CONST const +#define DECLARE_ACPIMMIO(ptr, bank) \ + uint8_t *const ptr = (void *)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) +#else +#define MAYBE_CONST +#define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr +#endif + +extern uint8_t *MAYBE_CONST acpimmio_gpio_100; +extern uint8_t *MAYBE_CONST acpimmio_sm_pci; +extern uint8_t *MAYBE_CONST acpimmio_smi; +extern uint8_t *MAYBE_CONST acpimmio_pmio; +extern uint8_t *MAYBE_CONST acpimmio_pmio2; +extern uint8_t *MAYBE_CONST acpimmio_biosram; +extern uint8_t *MAYBE_CONST acpimmio_cmosram; +extern uint8_t *MAYBE_CONST acpimmio_cmos; +extern uint8_t *MAYBE_CONST acpimmio_acpi; +extern uint8_t *MAYBE_CONST acpimmio_asf; +extern uint8_t *MAYBE_CONST acpimmio_smbus; +extern uint8_t *MAYBE_CONST acpimmio_wdt; +extern uint8_t *MAYBE_CONST acpimmio_hpet; +extern uint8_t *MAYBE_CONST acpimmio_iomux; +extern uint8_t *MAYBE_CONST acpimmio_misc; +extern uint8_t *MAYBE_CONST acpimmio_dpvga; +extern uint8_t *MAYBE_CONST acpimmio_gpio0; +extern uint8_t *MAYBE_CONST acpimmio_xhci_pm; +extern uint8_t *MAYBE_CONST acpimmio_acdc_tmr; +extern uint8_t *MAYBE_CONST acpimmio_aoac; + +#undef MAYBE_CONST /* Enable the AcpiMmio range at 0xfed80000 */ @@ -23,13 +57,6 @@ void pm_io_write16(uint8_t reg, uint16_t value); void pm_io_write32(uint8_t reg, uint32_t value); -#if !ENV_X86 - -#include <amdblocks/acpimmio_psp.h> - -#else - -#include <amdblocks/acpimmio_map.h> static inline uint8_t sm_pci_read8(uint8_t reg) { @@ -384,6 +411,4 @@ write8(acpimmio_aoac + reg, value); } -#endif /* ENV_X86 */ - #endif /* __AMDBLOCKS_ACPIMMIO_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 912e891..5d71287 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -112,20 +112,8 @@ * across family/model products. */ -/* For x86 base is constant, while PSP does mapping runtime. */ -#define CONSTANT_ACPIMMIO_BASE_ADDRESS ENV_X86 - #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#if CONSTANT_ACPIMMIO_BASE_ADDRESS -#define MAYBE_CONST const -#define DECLARE_ACPIMMIO(ptr, bank) \ - uint8_t *const ptr = (void *)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) -#else -#define MAYBE_CONST -#define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr -#endif - #ifdef __ACPI__ /* ASL fails on additions. */ @@ -161,29 +149,6 @@ #define ACPIMMIO_ASF_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ASF_BANK) #define ACPIMMIO_SMBUS_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_SMBUS_BANK) -extern uint8_t *MAYBE_CONST acpimmio_gpio_100; -extern uint8_t *MAYBE_CONST acpimmio_sm_pci; -extern uint8_t *MAYBE_CONST acpimmio_smi; -extern uint8_t *MAYBE_CONST acpimmio_pmio; -extern uint8_t *MAYBE_CONST acpimmio_pmio2; -extern uint8_t *MAYBE_CONST acpimmio_biosram; -extern uint8_t *MAYBE_CONST acpimmio_cmosram; -extern uint8_t *MAYBE_CONST acpimmio_cmos; -extern uint8_t *MAYBE_CONST acpimmio_acpi; -extern uint8_t *MAYBE_CONST acpimmio_asf; -extern uint8_t *MAYBE_CONST acpimmio_smbus; -extern uint8_t *MAYBE_CONST acpimmio_wdt; -extern uint8_t *MAYBE_CONST acpimmio_hpet; -extern uint8_t *MAYBE_CONST acpimmio_iomux; -extern uint8_t *MAYBE_CONST acpimmio_misc; -extern uint8_t *MAYBE_CONST acpimmio_dpvga; -extern uint8_t *MAYBE_CONST acpimmio_gpio0; -extern uint8_t *MAYBE_CONST acpimmio_xhci_pm; -extern uint8_t *MAYBE_CONST acpimmio_acdc_tmr; -extern uint8_t *MAYBE_CONST acpimmio_aoac; - -#undef MAYBE_CONST - #endif #endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h deleted file mode 100644 index b8ca7b5..0000000 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __AMDBLOCKS_ACPIMMIO_PSP_H__ -#define __AMDBLOCKS_ACPIMMIO_PSP_H__ - -#include <device/mmio.h> -#include <types.h> - -void iomux_set_bar(void *bar); -void *iomux_get_bar(void); -void misc_set_bar(void *bar); -void *misc_get_bar(void); -void gpio_set_bar(void *bar); -void *gpio_get_bar(void); -void aoac_set_bar(void *bar); -void *aoac_get_bar(void); -void io_set_bar(void *bar); -u8 io_read8(u16 reg); -void io_write8(u16 reg, u8 value); - -u8 iomux_read8(u8 reg); -u16 iomux_read16(u8 reg); -u32 iomux_read32(u8 reg); -void iomux_write8(u8 reg, u8 value); -void iomux_write16(u8 reg, u16 value); -void iomux_write32(u8 reg, u32 value); -u8 misc_read8(u8 reg); -u16 misc_read16(u8 reg); -u32 misc_read32(u8 reg); -void misc_write8(u8 reg, u8 value); -void misc_write16(u8 reg, u16 value); -void misc_write32(u8 reg, u32 value); -u8 aoac_read8(u8 reg); -void aoac_write8(u8 reg, u8 value); - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Gerrit-Change-Number: 42523 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 27

Change in coreboot[master]: soc/amd/common: Move lpc_util to verstage_x86
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43328 ) Change subject: soc/amd/common: Move lpc_util to verstage_x86 ...................................................................... soc/amd/common: Move lpc_util to verstage_x86 The file seems to be all about PCI configuration access. Change-Id: I1e64d3d7df3caa33ee92961fe7246d03f2707ab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/lpc/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/43328/1 diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc index 7db176b..b55004c 100644 --- a/src/soc/amd/common/block/lpc/Makefile.inc +++ b/src/soc/amd/common/block/lpc/Makefile.inc @@ -1,7 +1,7 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c +verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c -- To view, visit https://review.coreboot.org/c/coreboot/+/43328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e64d3d7df3caa33ee92961fe7246d03f2707ab4 Gerrit-Change-Number: 43328 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/amd/common: Redo ACPIMMIO_BASE and _BANK
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42894 ) Change subject: soc/amd/common: Redo ACPIMMIO_BASE and _BANK ...................................................................... soc/amd/common: Redo ACPIMMIO_BASE and _BANK Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/common/block/smbus/smbus.c M src/soc/amd/picasso/acpi/aoac.asl M src/soc/amd/stoneyridge/smbus_spd.c 6 files changed, 16 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42894/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 5084672..8acd27f 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -5,12 +5,9 @@ #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> -#define ACPI_BANK_PTR(bank) \ - (void *)(uintptr_t)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) - #if CONSTANT_ACPIMMIO_BASE_ADDRESS #define DECLARE_ACPIMMIO(ptr, bank) \ - uint8_t *const ptr = ACPI_BANK_PTR(bank) + uint8_t *const ptr = (void *)(uintptr_t)ACPIMMIO_BASE(bank) #else #define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr #endif diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 758a5562..e5caefc 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -95,13 +95,10 @@ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 #ifdef __ACPI__ - -/* ASL fails on additions. */ +/* ASL MemoryFixed32() fails if these are additions. */ #define ACPIMMIO_MISC_BASE 0xfed80e00 #define ACPIMMIO_GPIO0_BASE 0xfed81500 -#define ACPIMMIO_AOAC_BASE 0xfed81e00 - -#else +#endif #define ACPIMMIO_SM_PCI_BANK 0x0000 #define ACPIMMIO_GPIO_100_BANK 0x0100 @@ -126,10 +123,6 @@ #define ACPIMMIO_ACDCTMR_BANK 0x1d00 #define ACPIMMIO_AOAC_BANK 0x1e00 -/* FIXME: Passing host base for SMBUS is not long-term solution. */ -#define ACPIMMIO_ASF_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ASF_BANK) -#define ACPIMMIO_SMBUS_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_SMBUS_BANK) - -#endif +#define ACPIMMIO_BASE(bank) (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) #endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index c5c1ed8..f540e97 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -27,9 +27,9 @@ pbus = get_pbus_smbus(dev); res = find_resource(pbus->dev, 0x90); if (res->base == SMB_BASE_ADDR) - return ACPIMMIO_SMBUS_BASE; + return ACPIMMIO_BASE(SMBUS); - return ACPIMMIO_ASF_BASE; + return ACPIMMIO_BASE(ASF); } static int lsmbus_recv_byte(struct device *dev) diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c index e304483..fe1862f 100644 --- a/src/soc/amd/common/block/smbus/smbus.c +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -13,12 +13,15 @@ */ #define SMBUS_TIMEOUT (100 * 1000 * 10) +/* FIXME: Passing host base for SMBUS is not long-term solution. + It is possible to have multiple buses behind same host. */ + static u8 controller_read8(uintptr_t base, u8 reg) { switch (base) { - case ACPIMMIO_SMBUS_BASE: + case ACPIMMIO_BASE(SMBUS): return smbus_read8(reg); - case ACPIMMIO_ASF_BASE: + case ACPIMMIO_BASE(ASF): return asf_read8(reg); default: printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", @@ -30,10 +33,10 @@ static void controller_write8(uintptr_t base, u8 reg, u8 val) { switch (base) { - case ACPIMMIO_SMBUS_BASE: + case ACPIMMIO_BASE(SMBUS): smbus_write8(reg, val); break; - case ACPIMMIO_ASF_BASE: + case ACPIMMIO_BASE(ASF): asf_write8(reg, val); break; default: diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl index f26f85f..1b9e255 100644 --- a/src/soc/amd/picasso/acpi/aoac.asl +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -4,7 +4,7 @@ #define AOAC_DEVICE(DEV_NAME, DEV_ID, SX) \ PowerResource(DEV_NAME, SX, 0) { \ - OperationRegion (AOAC, SystemMemory, ACPIMMIO_AOAC_BASE + 0x40 + (DEV_ID << 1), 2) \ + OperationRegion (AOAC, SystemMemory, ACPIMMIO_BASE(AOAC) + 0x40 + (DEV_ID << 1), 2) \ Field (AOAC, ByteAcc, NoLock, Preserve) { \ /* \ * Target Device State \ diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 7c54d8d..38aac76 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -34,7 +34,7 @@ dev_addr = (SmbusSlaveAddress >> 1); /* Read the first SPD byte */ - error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0); + error = do_smbus_read_byte(ACPIMMIO_BASE(SMBUS), dev_addr, 0); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; @@ -44,7 +44,7 @@ /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ for (index = 1 ; index < count ; index++) { - error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr); + error = do_smbus_recv_byte(ACPIMMIO_BASE(SMBUS), dev_addr); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; -- To view, visit https://review.coreboot.org/c/coreboot/+/42894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50 Gerrit-Change-Number: 42894 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: [WIP] soc/amd/common: Avoid MMIO aliasing on SMBus
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42074 ) Change subject: [WIP] soc/amd/common: Avoid MMIO aliasing on SMBus ...................................................................... [WIP] soc/amd/common: Avoid MMIO aliasing on SMBus Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/smbus/smbus.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 20 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/42074/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index b95a347..ac48538 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -250,46 +250,6 @@ write32(acpimmio_acpi + reg, value); } -static inline uint8_t asf_read8(uint8_t reg) -{ - return read8(acpimmio_asf + reg); -} - -static inline uint16_t asf_read16(uint8_t reg) -{ - return read16(acpimmio_asf + reg); -} - -static inline void asf_write8(uint8_t reg, uint8_t value) -{ - write8(acpimmio_asf + reg, value); -} - -static inline void asf_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_asf + reg, value); -} - -static inline uint8_t smbus_read8(uint8_t reg) -{ - return read8(acpimmio_smbus + reg); -} - -static inline uint16_t smbus_read16(uint8_t reg) -{ - return read16(acpimmio_smbus + reg); -} - -static inline void smbus_write8(uint8_t reg, uint8_t value) -{ - write8(acpimmio_smbus + reg, value); -} - -static inline void smbus_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_smbus + reg, value); -} - static inline uint8_t iomux_read8(uint8_t reg) { return read8(acpimmio_iomux + reg); diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c index b5db56b..f8bab62 100644 --- a/src/soc/amd/common/block/smbus/smbus.c +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -3,7 +3,7 @@ #include <stdint.h> #include <console/console.h> #include <device/smbus_host.h> -#include <amdblocks/acpimmio.h> +#include <amdblocks/acpimmio_map.h> #include <soc/southbridge.h> /* @@ -12,37 +12,31 @@ */ #define SMBUS_TIMEOUT (100 * 1000 * 10) -static u8 controller_read8(uintptr_t base, u8 reg) +union reg_bank { + uint8_t reg8[0x100]; + uint16_t reg16[0x100 / sizeof(uint16_t)]; +}; + +static __always_inline u8 controller_read8(const u32 base, const u8 reg) { - switch (base) { - case ACPIMMIO_SMBUS_BASE: - return smbus_read8(reg); - case ACPIMMIO_ASF_BASE: - return asf_read8(reg); - default: - printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", - base); - } - return 0xff; + volatile union reg_bank *controller = (void *)(uintptr_t)base; + return controller->reg8[reg]; } -static void controller_write8(uintptr_t base, u8 reg, u8 val) +static __always_inline void controller_write8(const u32 base, const u8 reg, const u8 val) { - switch (base) { - case ACPIMMIO_SMBUS_BASE: - smbus_write8(reg, val); - break; - case ACPIMMIO_ASF_BASE: - asf_write8(reg, val); - break; - default: - printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n", - base); - } + volatile union reg_bank *controller = (void *)(uintptr_t)base; + controller->reg8[reg] = val; } static int smbus_wait_until_ready(uintptr_t mmio) { + if ((mmio != (uintptr_t)acpimmio_smbus) && + (mmio != (uintptr_t)acpimmio_asf)) { + printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio); + return -1; + } + u32 loops; loops = SMBUS_TIMEOUT; do { diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index e90fe1b..7bdc4a4 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -366,6 +366,7 @@ static void fch_smbus_init(void) { +#if 0 /* 400 kHz smbus speed. */ const uint8_t smbus_speed = (66000000 / (400000 * 4)); @@ -376,6 +377,7 @@ smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); +#endif } /* Before console init */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Gerrit-Change-Number: 42074 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 26

Change in coreboot[master]: soc/intel/xeon_sp: Fix final MTRR usage
by Arthur Heymans (Code Review) 15 Dec '20

15 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47868 ) Change subject: soc/intel/xeon_sp: Fix final MTRR usage ...................................................................... soc/intel/xeon_sp: Fix final MTRR usage The region top_of_ram -> cbmem_top is used by FSP, but is also just regular DRAM. Marking it as such improves the final MTRR solution a lot and fixes MTRR starvation depending on the setup. Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47868/1 diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 15a9f0f..94aabab 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -182,6 +182,11 @@ LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb); ram_resource(dev, index++, base_kb, size_kb); + /* fsp_mem_base -> cbmem_top */ + base_kb = top_of_ram / KiB; + size_kb = ((uintptr_t)cbmem_top() - top_of_ram) / KiB; + reserved_ram_resource(dev, index++, base_kb, size_kb); + /* * FSP meomoy, CBMem regions are already added as reserved * Add TSEG and MESEG Regions as reserved memory -- To view, visit https://review.coreboot.org/c/coreboot/+/47868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3 Gerrit-Change-Number: 47868 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: WIP: coreboot: Add anx7625 panel driver
by yongqiang niu (Code Review) 15 Dec '20

15 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46575 ) Change subject: WIP: coreboot: Add anx7625 panel driver ...................................................................... WIP: coreboot: Add anx7625 panel driver Add panel anx7625 to support display Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I045d2042b5649e36470500f266f108564b7063fa --- M src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/panel.h A src/mainboard/google/asurada/panel_anx7625.c 3 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46575/1 diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index d3f8ce6..2e5d86f 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -20,3 +20,5 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c + +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += panel_anx7625.c \ No newline at end of file diff --git a/src/mainboard/google/asurada/panel.h b/src/mainboard/google/asurada/panel.h new file mode 100644 index 0000000..648440b --- /dev/null +++ b/src/mainboard/google/asurada/panel.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ +#define __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ + +#include <edid.h> +#include <soc/dsi.h> + +/* + * The data that to be serialized and put into CBFS. + * Note some fields, for example edid.mode.name, were actually pointers and + * cannot be really serialized. + */ +struct panel_serializable_data { + struct edid edid; /* edid info of this panel */ + enum lb_fb_orientation orientation; /* Panel orientation */ + u8 init[]; /* A packed array of lcm_init_command */ +}; + +struct panel_description { + const char *name; /* Panel name for constructing CBFS file name */ + struct panel_serializable_data *s; + void (*power_on)(void); /* Callback to turn on panel */ +}; + +/* Returns the panel description from given ID. */ +struct panel_description *get_panel_description(int panel_id); + +/* Loads panel serializable data from CBFS. */ +struct panel_description *get_panel_from_cbfs(struct panel_description *desc); + +#define INIT_DCS_CMD(...) \ + LCM_DCS_CMD, \ + sizeof((u8[]){__VA_ARGS__}), \ + __VA_ARGS__ + +#define INIT_GENERIC_CMD(...) \ + LCM_GENERIC_CMD, \ + sizeof((u8[]){__VA_ARGS__}), \ + __VA_ARGS__ + +#define INIT_DELAY_CMD(delay) \ + LCM_DELAY_CMD, \ + delay + +#define INIT_END_CMD \ + LCM_END_CMD + +/* GPIO names */ +#define GPIO_MIPIBRDG_INT_ODL GPIO(EINT6) /* 6 */ +#define GPIO_MIPIBRDG_PWREN GPIO(DSI_TE) /* 41 */ +#define GPIO_MIPIBRDG_RST_L_1V8 GPIO(LCM_RST) /* 42 */ +#define GPIO_MIPIBRDG_PP3300_EN GPIO(PERIPHERAL_EN1) /* 127 */ +#define GPIO_MIPIBRDG_PP1800_EN GPIO(PERIPHERAL_EN2) /* 128 */ +#define GPIO_MIPIBRDG_PP1000_EN GPIO(PERIPHERAL_EN3) /* 129 */ +#define GPIO_PP3300_PANEL GPIO(CAM_CLK3) /* 136 */ + +#endif /* __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ */ diff --git a/src/mainboard/google/asurada/panel_anx7625.c b/src/mainboard/google/asurada/panel_anx7625.c new file mode 100644 index 0000000..0145859 --- /dev/null +++ b/src/mainboard/google/asurada/panel_anx7625.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <drivers/analogix/anx7625/anx7625.h> +#include <edid.h> +#include <gpio.h> +#include <soc/i2c.h> + +#include "panel.h" + + +static void power_on_anx7625(void) +{ + /* Disable backlight before turning on bridge */ + gpio_output(GPIO(KPROW1), 0); + gpio_output(GPIO(DISP_PWM), 0); + gpio_output(GPIO_PP3300_PANEL, 1); + + /* Turn on bridge */ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + gpio_output(GPIO_MIPIBRDG_PP1000_EN, 1); + gpio_output(GPIO_MIPIBRDG_PP1800_EN, 1); + gpio_output(GPIO_MIPIBRDG_PP3300_EN, 1); + mdelay(2); + gpio_output(GPIO_MIPIBRDG_PWREN, 1); + mdelay(10); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); +} + +static void dummy_power_on(void) +{ + /* The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static struct panel_serializable_data anx7625_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static struct panel_description anx7625_panel = { + .s = &anx7625_data, + .power_on = dummy_power_on, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + /* To read panel EDID, we have to first power on anx7625. */ + power_on_anx7625(); + + u8 i2c_bus = 3; + mtk_i2c_bus_init(i2c_bus); + + if (anx7625_init(i2c_bus)) { + printk(BIOS_ERR, "Can't init ANX7625 bridge.\n"); + return NULL; + } + struct edid *edid = &anx7625_data.edid; + if (anx7625_dp_get_edid(i2c_bus, edid)) { + printk(BIOS_ERR, "Can't get panel's edid.\n"); + return NULL; + } + if (anx7625_dp_start(i2c_bus, edid) < 0) { + printk(BIOS_ERR, "Can't start display via ANX7625.\n"); + return NULL; + } + + return &anx7625_panel; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I045d2042b5649e36470500f266f108564b7063fa Gerrit-Change-Number: 46575 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 33

Change in coreboot[master]: WIP: coreboot: Add display code
by yongqiang niu (Code Review) 15 Dec '20

15 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46578 ) Change subject: WIP: coreboot: Add display code ...................................................................... WIP: coreboot: Add display code Add display init code to support display Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46578/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 677e917..30e98e8 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -1,16 +1,27 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <bl31.h> +#include <boardid.h> +#include <bootmode.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/mmio.h> +#include <edid.h> +#include <gpio.h> #include <lib.h> +#include <soc/ddp.h> +#include <soc/dsi.h> #include <soc/dpm.h> +#include <soc/gpio.h> #include <soc/gpio_common.h> +#include <soc/mtcmos.h> #include <soc/spm.h> #include <soc/usb.h> #include "gpio.h" +#include "panel.h" #include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h> @@ -34,10 +45,102 @@ register_bl31_aux_param(&param_reset.h); } +/* Default implementation for boards without panels defined yet. */ +struct panel_description __weak *get_panel_description(int panel_id) +{ + printk(BIOS_ERR, "%s: ERROR: No panels defined for board: %s.\n", + __func__, CONFIG_MAINBOARD_PART_NUMBER); + return NULL; +} + +/* Set up backlight control pins as output pin and power-off by default */ +static void configure_panel_backlight(void) +{ + gpio_output(GPIO(KPROW1), 0); + gpio_output(GPIO(DISP_PWM), 0); +} + +static void power_on_panel(struct panel_description *panel) +{ + if (panel->power_on) { + panel->power_on(); + return; + } + + /* Default power sequence for most panels. */ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + mdelay(6); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); + mdelay(6); +} + +static struct panel_description *get_active_panel(void) +{ + /* TODO(hungte) Create a dedicated panel_id() in board_id.c */ + int panel_id = sku_id() >> 4; + + struct panel_description *panel = get_panel_description(panel_id); + if (!panel) { + printk(BIOS_ERR, "%s: Panel %d is not supported.\n", + __func__, panel_id); + return NULL; + } + assert(panel->s); + + const struct edid *edid = &panel->s->edid; + const char *name = edid->ascii_string; + if (name[0] == '\0') + name = "unknown name"; + printk(BIOS_INFO, "%s: Found ID %d: '%s %s' %dx%d@%dHz\n", __func__, + panel_id, edid->manufacturer_name, name, edid->mode.ha, + edid->mode.va, edid->mode.refresh); + return panel; +} + +static bool configure_display(void) +{ + struct panel_description *panel = get_active_panel(); + if (!panel) + return false; + + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + configure_panel_backlight(); + power_on_panel(panel); + + struct edid *edid = &panel->s->edid; + edid_set_framebuffer_bits_per_pixel(edid, 32, 0); + mtk_ddp_init(); + u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM); + if (CONFIG(DRIVER_ANALOGIX_ANX7625)) + mipi_dsi_flags |= MIPI_DSI_MODE_EOT_PACKET; + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, edid, + panel->s->init) < 0) { + printk(BIOS_ERR, "%s: Failed in DSI init.\n", __func__); + return false; + } + mtk_ddp_mode_set(edid); + set_vbe_mode_info_valid(edid, 0); + set_vbe_framebuffer_orientation(panel->s->orientation); + return true; +} + static void mainboard_init(struct device *dev) { int i; + if (display_init_required()) { + printk(BIOS_INFO, "%s: Starting display init.\n", __func__); + if (!configure_display()) + printk(BIOS_ERR, "%s: Failed to init display.\n", + __func__); + } else { + printk(BIOS_INFO, "%s: Skipped display init.\n", __func__); + } + + /* HACK, set pinctrl for SD card */ for (i = 51; i <= 56; i++) gpio_set_mode((gpio_t){.id = i}, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/46578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf Gerrit-Change-Number: 46578 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

4 27

Change in coreboot[master]: mb/prodrive/hermes: Update PCIe slots in devicetree
by Patrick Rudolph (Code Review) 14 Dec '20

14 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47239 ) Change subject: mb/prodrive/hermes: Update PCIe slots in devicetree ...................................................................... mb/prodrive/hermes: Update PCIe slots in devicetree * Drop PcieRpSlotImplemented on internal slots * Add PCIe port 15 that connected to CNVi/M2.E Change-Id: Iaa05affa760b447fc1725e674b12366684a63720 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 9 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/47239/1 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 2c0c26a..56348c2 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -187,30 +187,21 @@ smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[0]" = "1" end - device pci 1c.4 on # PCIe root port 5 (PHY 3) - register "PcieRpSlotImplemented[4]" = "1" - end - device pci 1c.5 on # PCIe root port 6 (PHY 4) - register "PcieRpSlotImplemented[5]" = "1" - end - device pci 1c.6 on # PCIe root port 7 (PHY 2) - register "PcieRpSlotImplemented[6]" = "1" - end - device pci 1c.7 on # PCIe root port 8 (PHY 1) - register "PcieRpSlotImplemented[7]" = "1" - end + device pci 1c.4 on end # PCIe root port 5 (PHY 3) + device pci 1c.5 on end # PCIe root port 6 (PHY 4) + device pci 1c.6 on end # PCIe root port 7 (PHY 2) + device pci 1c.7 on end # PCIe root port 8 (PHY 1) device pci 1d.0 on # PCIe root port 9 (M2 M) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[8]" = "1" end - device pci 1d.5 on # PCIe root port 14 (PHY 0) - register "PcieRpSlotImplemented[13]" = "1" + device pci 1d.5 on end # PCIe root port 14 (PHY 0) + device pci 1d.6 on end # PCIe root port 15 (BMC) + device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi) + # Disabled when CNVi is present + register "PcieRpSlotImplemented[15]" = "1" end - device pci 1d.6 on # PCIe root port 15 (BMC) - register "PcieRpSlotImplemented[14]" = "1" - end - device pci 1e.0 on end # UART #0 device pci 1e.1 on end # UART #1 device pci 1e.2 off end # GSPI #0 -- To view, visit https://review.coreboot.org/c/coreboot/+/47239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa05affa760b447fc1725e674b12366684a63720 Gerrit-Change-Number: 47239 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: cbfs: Enable CBFS mcache on (almost) all boards
by Julius Werner (Code Review) 14 Dec '20

14 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38424 to review the following change. Change subject: cbfs: Enable CBFS mcache on (almost) all boards ...................................................................... cbfs: Enable CBFS mcache on (almost) all boards This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Only a few boards with notoriously little space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/cpu/ti/am335x/memlayout.ld M src/lib/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/google/octopus/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M src/soc/samsung/exynos5420/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/memlayout.ld 25 files changed, 51 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 1c55bdb..7cf049d 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -155,6 +155,13 @@ help Increase this value if preram cbmem console is getting truncated +config CBFS_MCACHE_SIZE + hex + depends on !NO_CBFS_MCACHE + default 0x2000 + help + Increase this value if you see CBFS mcache overflow warnings + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 2e29112..52e081a 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -60,6 +60,9 @@ #if !CONFIG(NO_FMAP_CACHE) FMAP_CACHE(., FMAP_SIZE) #endif +#if !CONFIG(NO_CBFS_MCACHE) + CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) +#endif _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld index f69a315..9bc7b75 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/cpu/ti/am335x/memlayout.ld @@ -19,7 +19,8 @@ { DRAM_START(0x40000000) BOOTBLOCK(0x402f0400, 20K) - ROMSTAGE(0x402f5400, 88K) + ROMSTAGE(0x402f5400, 80K) + CBFS_MCACHE(0x40309400, 8K) FMAP_CACHE(0x4030b400, 2K) STACK(0x4030be00, 4K) RAMSTAGE(0x80200000, 192K) diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 26bf0be..4d2bf80 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -78,7 +78,6 @@ config NO_CBFS_MCACHE bool - default y help Disables the CBFS metadata cache. This means that your platform does not need to provide a CBFS_MCACHE section in memlayout and can save diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index aba4205..544f89f 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -24,7 +24,8 @@ DRAM_START(0x40000000) BOOTBLOCK(0x60010000, 64K) - STACK(0x60020000, 62K) + STACK(0x60020000, 54K) + CBFS_MCACHE(0x6002D800, 8K) FMAP_CACHE(0x6002F800, 2K) ROMSTAGE(0x60030000, 128K) RAMSTAGE(0x60070000, 16M) diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 2b33cb3..de09cbb 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -43,6 +43,7 @@ BOOTBLOCK(0x00000, 64K) FMAP_CACHE(0x10000, 2K) + CBFS_MCACHE(0x10800, 8K) DRAM_START(0x60000000) STACK(0x60000000, 64K) diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index c22d3e4..81fe7f4 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -27,5 +27,6 @@ STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) FMAP_CACHE(0x82000, 2K) + CBFS_MCACHE(0x82800, 8K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index e53df38..7eb0f00 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -38,6 +38,7 @@ #endif PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) FMAP_CACHE(STAGES_START + 136K, 2K) + CBFS_MCACHE(STAGES_START + 138K, 8K) RAMSTAGE(STAGES_START + 200K, 16M) STACK(STAGES_START + 200K + 16M, 4K) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index b6e4d9d..376b9b1 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -24,7 +24,8 @@ DRAM_START(START) BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) - FMAP_CACHE(START + 8M + 4K, 2K) + FMAP_CACHE(START + 12M, 2K) + CBFS_CACHE(START + 14M, 8K) /* hole at (START + 8M + 6K, 58K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 3139716..8a33b5f 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -23,6 +23,7 @@ select MAINBOARD_HAS_TPM2 select GOOGLE_SMBIOS_MAINBOARD_VERSION select NO_FMAP_CACHE + select NO_CBFS_MCACHE if BOARD_GOOGLE_BASEBOARD_OCTOPUS diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 1a0eb15..e78aa20 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -34,7 +34,8 @@ PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) - BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) + BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 56K) + CBFS_MCACHE(BOOTROM_OFFSET + 0x2e000, 8K) VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x33000, 2K) VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 2358c39..2d364b5 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -43,7 +43,8 @@ FMAP_CACHE(0x00103800, 2K) PRERAM_CBMEM_CONSOLE(0x00104000, 12K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) + PRERAM_CBFS_CACHE(0x00107004, 8K - 4) + CBFS_MCACHE(0x00109000, 8K) TIMESTAMP(0x0010B000, 4K) ROMSTAGE(0x0010C000, 92K) STACK(0x00124000, 16K) diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 996d2ec..0d20e31 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -43,7 +43,8 @@ SRAM_L2C_START(0x00200000) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) - BOOTBLOCK(0x00230000, 64K) + BOOTBLOCK(0x00230000, 56K) + CBFS_MCACHE(0x0023e000, 8K) DRAM_INIT_CODE(0x00240000, 208K) PRERAM_CBFS_CACHE(0x00274000, 48K) SRAM_L2C_END(0x00280000) diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 7e2cc7a..a342f6a 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -29,7 +29,8 @@ TTB(0x40000000, 16K + 32) PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) FMAP_CACHE(0x40005800, 2K) - PRERAM_CBFS_CACHE(0x40006000, 14K) + CBFS_MCACHE(0x40006000, 8K) + PRERAM_CBFS_CACHE(0x40008000, 6K) VBOOT2_WORK(0x40009800, 12K) VBOOT2_TPM_LOG(0x4000D800, 2K) STACK(0x4000E000, 8K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index b7268d1..44f0153 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -30,7 +30,8 @@ SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 2K) FMAP_CACHE(0x40000800, 2K) - PRERAM_CBFS_CACHE(0x40001000, 28K) + PRERAM_CBFS_CACHE(0x40001000, 20K) + CBFS_MCACHE(0x40006000, 8K) VBOOT2_WORK(0x40008000, 12K) VBOOT2_TPM_LOG(0x4000B000, 2K) #if ENV_ARM64 diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index 6ff1018..76685cf 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -34,7 +34,8 @@ /* This includes bootblock image, can be reused after bootblock starts */ /* UBER_SBL(0x0A0C0000, 48K) */ - PRERAM_CBFS_CACHE(0x0A0C0000, 92K) + PRERAM_CBFS_CACHE(0x0A0C0000, 84K) + CBFS_MCACHE(0x0A0ED800, 8K) FMAP_CACHE(0x0A0EF800, 2K) TTB(0x0A0F0000, 16K) diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 595d939..6e309c0 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -38,7 +38,8 @@ QCA_SHARED_RAM(2A03F000, 4K) */ STACK(0x2A040000, 16K) - PRERAM_CBFS_CACHE(0x2A044000, 91K) + PRERAM_CBFS_CACHE(0x2A044000, 83K) + CBFS_MCACHE(0x2A059000, 8K) FMAP_CACHE(0x2A05B000, 2K) TTB_SUBTABLES(0x2A05B800, 2K) TTB(0x2A05C000, 16K) diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index dd013b5..9d92949 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -38,7 +38,8 @@ STACK(0x8C4B000, 16K) TIMESTAMP(0x8C4F000, 1K) PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) - PRERAM_CBFS_CACHE(0x8C57400, 70K) + PRERAM_CBFS_CACHE(0x8C57400, 62K) + CBFS_MCACHE(0x8C66C00, 8K) FMAP_CACHE(0x8C68C00, 2K) REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100) BSRAM_END(0x8D80000) diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 7323119..838fda3 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -52,6 +52,7 @@ REGION(qclib_serial_log, 0x14852000, 4K, 4K) REGION(ddr_information, 0x14853000, 1K, 1K) FMAP_CACHE(0x14853400, 2K) + CBFS_MCACHE(0x14853C00, 8K) REGION(dcb, 0x14870000, 16K, 4K) REGION(pmic, 0x14874000, 44K, 4K) REGION(limits_cfg, 0x1487F000, 4K, 4K) diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index c3a3b4c..5ea3e96 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -58,7 +58,8 @@ PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) FMAP_CACHE(0x1484FC00, 2K) - REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) + CBFS_MCACHE(0x1485400, 8K) + REGION(bsram_unused, 0x14852400, 0x9BB00, 0x100) REGION(ddr_information, 0x148EDF00, 256, 256) REGION(limits_cfg, 0x148EE000, 4K, 4K) REGION(qclib_serial_log, 0x148EF000, 4K, 4K) diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 6a44ccd..e36a8e8 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -30,6 +30,7 @@ select HAVE_LINEAR_FRAMEBUFFER select NO_BOOTBLOCK_CONSOLE select NO_FMAP_CACHE + select NO_CBFS_MCACHE if SOC_ROCKCHIP_RK3288 diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 4e46e2d..2c7be29 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -37,11 +37,12 @@ FMAP_CACHE(0xFF8C1400, 2K) TIMESTAMP(0xFF8C1C00, 1K) /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) - BOOTBLOCK(0xFF8D8000, 40K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 84K - 4) + BOOTBLOCK(0xFF8D7000, 40K) #endif - VBOOT2_WORK(0XFF8E2000, 12K) - TTB(0xFF8E5000, 24K) + CBFS_MCACHE(0xFF8E1000, 8K) + VBOOT2_WORK(0XFF8E3000, 12K) + TTB(0xFF8E6000, 20K) PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) STACK(0xFF8ED000, 12K) SRAM_END(0xFF8F0000) diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 7e052f0..e97fcb0 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -31,7 +31,8 @@ ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 76K) + PRERAM_CBFS_CACHE(0x205C000, 68K) + CBFS_MCACHE(0x206D000, 8K) FMAP_CACHE(0x206F000, 2K) VBOOT2_TPM_LOG(0x206F800, 2K) VBOOT2_WORK(0x2070000, 12K) diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld index ff781d2..e2e51c0 100644 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld @@ -32,7 +32,8 @@ ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 74K) + PRERAM_CBFS_CACHE(0x205C000, 66K) + CBFS_MCACHE(0x206C800, 8K) FMAP_CACHE(0x206E800, 2K) STACK(0x206F000, 16K) /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index 46c559c..cc4f900 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -26,7 +26,8 @@ L2LIM_START(FU540_L2LIM) BOOTBLOCK(FU540_L2LIM, 64K) CAR_STACK(FU540_L2LIM + 64K, 20K) - PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) + PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 76K, 8K) + CBFS_MCACHE(FU540_L2LIM + 84K, 8K) FMAP_CACHE(FU540_L2LIM + 92K, 2K) ROMSTAGE(FU540_L2LIM + 128K, 128K) PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) -- To view, visit https://review.coreboot.org/c/coreboot/+/38424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Gerrit-Change-Number: 38424 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

10 44

Change in coreboot[master]: soc/intel/xeon_sp: Configure DPR on all stacks
by Arthur Heymans (Code Review) 14 Dec '20

14 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46818 ) Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ...................................................................... soc/intel/xeon_sp: Configure DPR on all stacks Configure DPR to span the region between TSEG_BASE and the cbmem_top. This region was already unavailable to the OS. Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46818/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index a28fac6..bbeee1f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -79,6 +79,7 @@ #define VMD_FUNC_NUM 0x05 #define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 #define VTD_FUNC_NUM 0x0 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 32c316d..6523b6d 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -128,6 +128,7 @@ #define HPET0_FUNC_NUM 0x00 #define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 #define VTD_FUNC_NUM 0x0 diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 332b9a4..c9ffeb6 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -11,6 +11,8 @@ #include <soc/ramstage.h> #include <soc/util.h> #include <fsp/util.h> +#include <security/intel/txt/txt_platform.h> +#include <soc/pci_devs.h> struct map_entry { uint32_t reg; @@ -88,6 +90,17 @@ } } +static void configure_dpr(struct device *dev) +{ + const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB; + union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + + dpr.size = dpr.top - cbmem_top_mb; + dpr.lock = 1; + dpr.epm = 1; + pci_write_config32(dev, VTD_LTDPR, dpr.raw); +} + /* * Host Memory Map: * @@ -127,6 +140,8 @@ * | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000) * +--------------------------+ * | Tseg (relocatable) | N x 8MB (0x70000000 - 0x77ffffff, 0x20000) + * +--------------------------+ + * | DPR | * +--------------------------+ cbmem_top * | Reserved - CBMEM | (0x6fffe000 - 0x6fffffff, 0x2000) * +--------------------------+ @@ -199,6 +214,13 @@ LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb); reserved_ram_resource(dev, index++, base_kb, size_kb); + /* Reserve and set up DPR */ + configure_dpr(dev); + union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + if (dpr.size) + reserved_ram_resource(dev, index++, (dpr.top - dpr.size) << 10, dpr.size << 10); + + /* Mark region between TSEG - TOLM (eg. MESEG) as reserved */ if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) { base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10); @@ -290,3 +312,25 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = mmapvtd_ids }; + +static void vtd_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + configure_dpr(dev); +} + +static struct device_operations vtd_ops = { + .read_resources = vtd_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +// .init = mmapvtd_init, + .ops_pci = &soc_pci_ops, +}; + +/* VTD devices on other stacks */ +static const struct pci_driver vtd_driver __pci_driver = { + .ops = &vtd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = MMAP_VTD_STACK_CFG_REG_DEVID, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Gerrit-Change-Number: 46818 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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