coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: soc/amd/stoneyridge: align AOAC code with Picasso
by Felix Held (Code Review) 01 Dec '20

01 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48181 ) Change subject: soc/amd/stoneyridge: align AOAC code with Picasso ...................................................................... soc/amd/stoneyridge: align AOAC code with Picasso In commit 09d50671e6b43c23853a91ff4d6fb26c1e7e17a1 the AOAC code was reworked for Picasso and this patch ports this back to Stoneyridge to facilitate factoring out the functionality into common code. Change-Id: I836b91dc647987d064170fff7c8ca6ef2ee49211 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 36 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/48181/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index cbd9caa..9450a92 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -190,16 +190,20 @@ #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) /* FCH AOAC Registers 0xfed81e00 */ -#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 -#define FCH_AOAC_D3_CONTROL_I2C0 0x4a -#define FCH_AOAC_D3_CONTROL_I2C1 0x4c -#define FCH_AOAC_D3_CONTROL_I2C2 0x4e -#define FCH_AOAC_D3_CONTROL_I2C3 0x50 -#define FCH_AOAC_D3_CONTROL_UART0 0x56 -#define FCH_AOAC_D3_CONTROL_UART1 0x58 -#define FCH_AOAC_D3_CONTROL_AMBA 0x62 -#define FCH_AOAC_D3_CONTROL_USB2 0x64 -#define FCH_AOAC_D3_CONTROL_USB3 0x6e +#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) +#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) + +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C0 5 +#define FCH_AOAC_DEV_I2C1 6 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_USB2 18 +#define FCH_AOAC_DEV_USB3 23 + /* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) #define FCH_AOAC_DEVICE_STATE BIT(2) @@ -209,16 +213,6 @@ #define FCH_AOAC_SW_RST_B BIT(6) #define FCH_AOAC_IS_SW_CONTROL BIT(7) -#define FCH_AOAC_D3_STATE_CLK_GEN 0x41 -#define FCH_AOAC_D3_STATE_I2C0 0x4b -#define FCH_AOAC_D3_STATE_I2C1 0x4d -#define FCH_AOAC_D3_STATE_I2C2 0x4f -#define FCH_AOAC_D3_STATE_I2C3 0x51 -#define FCH_AOAC_D3_STATE_UART0 0x57 -#define FCH_AOAC_D3_STATE_UART1 0x59 -#define FCH_AOAC_D3_STATE_AMBA 0x63 -#define FCH_AOAC_D3_STATE_USB2 0x65 -#define FCH_AOAC_D3_STATE_USB3 0x6f /* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ #define FCH_AOAC_PWR_RST_STATE BIT(0) #define FCH_AOAC_RST_CLK_OK_STATE BIT(1) @@ -292,11 +286,6 @@ #define RST_CMD BIT(2) #define SYS_RST BIT(1) -struct stoneyridge_aoac { - int enable; - int status; -}; - typedef struct aoac_devs { unsigned int :5; unsigned int ic0e:1; /* 5: I2C0 */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 267f747..05f3072 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -31,14 +31,13 @@ * waiting for each device to become available, a single delay will be * executed. */ -static const struct stoneyridge_aoac aoac_devs[] = { - { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), - (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, - { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, - { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, - { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, - { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, - { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } +static const unsigned int aoac_devs[] = { + FCH_AOAC_DEV_UART0 + CONFIG_UART_FOR_CONSOLE * 2, + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, }; static int is_sata_config(void) @@ -146,21 +145,21 @@ return irq_association; } -static void power_on_aoac_device(int aoac_device_control_register) +static void power_on_aoac_device(unsigned int dev) { uint8_t byte; /* Power on the UART and AMBA devices */ - byte = aoac_read8(aoac_device_control_register); + byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte |= FCH_AOAC_PWR_ON_DEV; - aoac_write8(aoac_device_control_register, byte); + aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } -static bool is_aoac_device_enabled(int aoac_device_status_register) +static bool is_aoac_device_enabled(unsigned int dev) { uint8_t byte; - byte = aoac_read8(aoac_device_status_register); + byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) return true; @@ -174,14 +173,14 @@ int i; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - power_on_aoac_device(aoac_devs[i].enable); + power_on_aoac_device(aoac_devs[i]); /* Wait for AOAC devices to indicate power and clock OK */ do { udelay(100); status = true; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - status &= is_aoac_device_enabled(aoac_devs[i].status); + status &= is_aoac_device_enabled(aoac_devs[i]); } while (!status); } @@ -545,14 +544,14 @@ if (gnvs == NULL) return; - gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); - gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); - gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); - gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); - gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); - gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); - gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); - gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); + gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0); + gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1); + gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); + gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); + gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); + gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); + gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2); + gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/48181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I836b91dc647987d064170fff7c8ca6ef2ee49211 Gerrit-Change-Number: 48181 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/amd/picasso/aoac: make aoac_devs array unsigned
by Felix Held (Code Review) 01 Dec '20

01 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48180 ) Change subject: soc/amd/picasso/aoac: make aoac_devs array unsigned ...................................................................... soc/amd/picasso/aoac: make aoac_devs array unsigned The numbers in the array are unsigned, so use an unsigned type there. Change-Id: I9a85594de0e4c53db965ab84239f19eb46432348 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/aoac.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/48180/1 diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index f9fe0e2..00f26fe 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -21,7 +21,7 @@ * waiting for each device to become available, a single delay will be * executed. The console UART is handled separately from this table. */ -const static int aoac_devs[] = { +const static unsigned int aoac_devs[] = { FCH_AOAC_DEV_AMBA, FCH_AOAC_DEV_I2C2, FCH_AOAC_DEV_I2C3, -- To view, visit https://review.coreboot.org/c/coreboot/+/48180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a85594de0e4c53db965ab84239f19eb46432348 Gerrit-Change-Number: 48180 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/amd/picasso/aoac: fix type in comment
by Felix Held (Code Review) 01 Dec '20

01 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48155 ) Change subject: soc/amd/picasso/aoac: fix type in comment ...................................................................... soc/amd/picasso/aoac: fix type in comment the power_off_aoac_device function clears the FCH_AOAC_PWR_ON_DEV bit, so the comment should be that it powers off the devices. Change-Id: Ia5e5d80b1977c3f53fcd9cf6d48bdb59045dfc3c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/aoac.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/48155/1 diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index 1f7dcb0..f9fe0e2 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -45,7 +45,7 @@ { uint8_t byte; - /* Power on the UART and AMBA devices */ + /* Power off the UART and AMBA devices */ byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte &= ~FCH_AOAC_PWR_ON_DEV; aoac_write8(AOAC_DEV_D3_CTL(dev), byte); -- To view, visit https://review.coreboot.org/c/coreboot/+/48155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5e5d80b1977c3f53fcd9cf6d48bdb59045dfc3c Gerrit-Change-Number: 48155 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: cpu/x86/64bit/entry64: Use ramstage code segment in ramstage
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48176 ) Change subject: cpu/x86/64bit/entry64: Use ramstage code segment in ramstage ...................................................................... cpu/x86/64bit/entry64: Use ramstage code segment in ramstage Change-Id: I232370dd92f11e7ce897d41514cced751c7e573d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/entry64.inc 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48176/1 diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 65c0fdc..1376fcc 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -14,9 +14,15 @@ #if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0 #error pagetables must be 4KiB aligned! #endif +#if defined(__RAMSTAGE__) +#include <arch/ram_segs.h> +#define CODE_SEG64 RAM_CODE_SEG64 +#else +#include <arch/rom_segs.h> +#define CODE_SEG64 ROM_CODE_SEG64 +#endif #include <cpu/x86/msr.h> -#include <arch/rom_segs.h> setup_longmode: /* Get page table address */ @@ -42,7 +48,7 @@ movl %eax, %cr0 /* use long jump to switch to 64-bit code segment */ - ljmp $ROM_CODE_SEG64, $__longmode_start + ljmp $CODE_SEG64, $__longmode_start .code64 __longmode_start: -- To view, visit https://review.coreboot.org/c/coreboot/+/48176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232370dd92f11e7ce897d41514cced751c7e573d Gerrit-Change-Number: 48176 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/common/block/smm/smihandler: Fix compilation under x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48172 ) Change subject: soc/intel/common/block/smm/smihandler: Fix compilation under x86_64 ...................................................................... soc/intel/common/block/smm/smihandler: Fix compilation under x86_64 Change-Id: Ie44ded11a6a9ddd2a1163d2f57dad6935e1ea167 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/smm/smihandler.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/48172/1 diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 270b1aa..74d5719 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -292,7 +292,7 @@ { u8 sub_command, ret; void *io_smi; - uint32_t reg_ebx; + uintptr_t reg_ebx; io_smi = find_save_state(save_state_ops, APM_CNT_SMMSTORE); if (!io_smi) @@ -409,7 +409,7 @@ if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) { /* power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - pmc_disable_pm1_control(-1UL); + pmc_disable_pm1_control(~0); pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44ded11a6a9ddd2a1163d2f57dad6935e1ea167 Gerrit-Change-Number: 48172 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48171 ) Change subject: soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64 ...................................................................... soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64 Change-Id: Ieac4a4924ff4684b2a419471cd54e3d3b1f5bbe6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/cpu/car/exit_car.S 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48171/1 diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 9480a5a..191232a 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -28,7 +28,11 @@ * Retrieve return address from stack as it will get trashed below if * execution is utilizing the cache-as-ram stack. */ +#if ENV_X86_64 + pop %rbx +#else pop %ebx +#endif /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx @@ -95,4 +99,8 @@ #endif /* Return to caller. */ +#if ENV_X86_64 + jmp *%rbx +#else jmp *%ebx +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieac4a4924ff4684b2a419471cd54e3d3b1f5bbe6 Gerrit-Change-Number: 48171 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/common/block/cpu/car/cache_as_ram: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48170 ) Change subject: soc/intel/common/block/cpu/car/cache_as_ram: Fix compilation on x86_64 ...................................................................... soc/intel/common/block/cpu/car/cache_as_ram: Fix compilation on x86_64 Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48170/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5af1fc6..167342f 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -9,6 +9,7 @@ #include <rules.h> #include <intelblocks/msr.h> +.code32 .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -161,6 +162,15 @@ /* Need to align stack to 16 bytes at call instruction. Account for the two pushes below. */ andl $0xfffffff0, %esp + +#if ENV_X86_64 + #include <cpu/x86/64bit/entry64.inc> + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else sub $8, %esp /* push TSC value to stack */ @@ -168,6 +178,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_carstage: post_code(0x2A) -- To view, visit https://review.coreboot.org/c/coreboot/+/48170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344 Gerrit-Change-Number: 48170 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: drivers/aspeed/common/ast: Fix compilation under x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48169 ) Change subject: drivers/aspeed/common/ast: Fix compilation under x86_64 ...................................................................... drivers/aspeed/common/ast: Fix compilation under x86_64 Change-Id: I5fb6594ff83904df02083bcbea14b2d0b89cd9dd Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/48169/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index bf974ff..bb30d20 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -32,7 +32,7 @@ return -ENOMEM; } - fb->mmio_addr = (u32)res2mmio(res, 4095, 4095); + fb->mmio_addr = (uintptr_t)res2mmio(res, 4095, 4095); ast_set_offset_reg(crtc); ast_set_start_address_crt1(ast, fb->mmio_addr); @@ -230,7 +230,7 @@ set_vbe_mode_info_valid(&edid, fb.mmio_addr); /* Clear display */ - memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); + memset((void *)(uintptr_t)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fb6594ff83904df02083bcbea14b2d0b89cd9dd Gerrit-Change-Number: 48169 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: drivers/intel/fsp2_0/notify: Fix compilation under x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48168 ) Change subject: drivers/intel/fsp2_0/notify: Fix compilation under x86_64 ...................................................................... drivers/intel/fsp2_0/notify: Fix compilation under x86_64 Change-Id: Id63b9b372bf23e80e25b7dbef09d1b8bfa9be069 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp2_0/notify.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48168/1 diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 76cdf12..ee04630 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -57,7 +57,7 @@ static void fsp_notify_dummy(void *arg) { - enum fsp_notify_phase phase = (uint32_t)arg; + enum fsp_notify_phase phase = (uint32_t)(uintptr_t)arg; display_mtrrs(); -- To view, visit https://review.coreboot.org/c/coreboot/+/48168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id63b9b372bf23e80e25b7dbef09d1b8bfa9be069 Gerrit-Change-Number: 48168 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/common/block/systemagent: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48167 ) Change subject: soc/intel/common/block/systemagent: Fix compilation on x86_64 ...................................................................... soc/intel/common/block/systemagent: Fix compilation on x86_64 Change-Id: Ibc8dc1cf33f594284edb82d4730967e077739c3c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/systemagent/systemagent_early.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48167/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 53d6077..ca11ee6 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -95,8 +95,8 @@ base = fixed_set_resources[i].base; index = fixed_set_resources[i].index; if (base >> 32) - write32((void *)(MCH_BASE_ADDRESS + index + 4), base >> 32); - write32((void *)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc8dc1cf33f594284edb82d4730967e077739c3c Gerrit-Change-Number: 48167 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020