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Change in coreboot[master]: mb/google/volteer: Create drobit variant
by Patrick Georgi (Code Review) 30 Nov '20

30 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47787 ) Change subject: mb/google/volteer: Create drobit variant ...................................................................... mb/google/volteer: Create drobit variant Create the drobit variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171947885 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I63b7312bba236bd5af028359804d042f6850d8ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/47787 Reviewed-by: Zhuohao Lee <zhuohao(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/drobit/include/variant/ec.h A src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h A src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc A src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt A src/mainboard/google/volteer/variants/drobit/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 1553a3a..f2e4adc 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -106,6 +106,7 @@ default "Boldar" if BOARD_GOOGLE_BOLDAR default "Elemi" if BOARD_GOOGLE_ELEMI default "Voema" if BOARD_GOOGLE_VOEMA + default "Drobit" if BOARD_GOOGLE_DROBIT config MAX_CPUS int @@ -146,6 +147,7 @@ default "boldar" if BOARD_GOOGLE_BOLDAR default "elemi" if BOARD_GOOGLE_ELEMI default "voema" if BOARD_GOOGLE_VOEMA + default "drobit" if BOARD_GOOGLE_DROBIT config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 0f9b6e2..7536dc5 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -89,3 +89,7 @@ bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + +config BOARD_GOOGLE_DROBIT + bool "-> Drobit" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h b/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h b/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc b/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt new file mode 100644 index 0000000..f51b3af --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb new file mode 100644 index 0000000..32204c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/47787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63b7312bba236bd5af028359804d042f6850d8ba Gerrit-Change-Number: 47787 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/vboot: use transfer_buffer_valid function
by Felix Held (Code Review) 30 Nov '20

30 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47977 ) Change subject: soc/amd/common/vboot: use transfer_buffer_valid function ...................................................................... soc/amd/common/vboot: use transfer_buffer_valid function show_psp_transfer_info reimplemented the functionality of transfer_buffer_valid, so use replace that with a function call. Change-Id: Ie3d373b10bdb0ab00640dabeea12b13ec25406cc Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/vboot/vboot_bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/47977/1 diff --git a/src/soc/amd/common/vboot/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c index 45ad9de..da652eb 100644 --- a/src/soc/amd/common/vboot/vboot_bootblock.c +++ b/src/soc/amd/common/vboot/vboot_bootblock.c @@ -47,7 +47,7 @@ struct transfer_info_struct *info = (struct transfer_info_struct *) (void *)(uintptr_t)_transfer_buffer; - if (info->magic_val == TRANSFER_MAGIC_VAL) { + if (transfer_buffer_valid(info)) { if ((info->psp_info & PSP_INFO_VALID) == 0) { printk(BIOS_INFO, "No PSP info found in transfer buffer.\n"); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/47977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3d373b10bdb0ab00640dabeea12b13ec25406cc Gerrit-Change-Number: 47977 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: move vboot-on-PSP-related functions to common/vboot
by Felix Held (Code Review) 30 Nov '20

30 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47976 ) Change subject: soc/amd: move vboot-on-PSP-related functions to common/vboot ...................................................................... soc/amd: move vboot-on-PSP-related functions to common/vboot Change-Id: I4f07d3ab12116229a13d2e8c02b2deb06e51a1af Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/vboot/vboot_bootblock.c M src/soc/amd/picasso/bootblock/bootblock.c M src/soc/amd/picasso/include/soc/psp_transfer.h 3 files changed, 52 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47976/1 diff --git a/src/soc/amd/common/vboot/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c index 3fbc4ef..45ad9de 100644 --- a/src/soc/amd/common/vboot/vboot_bootblock.c +++ b/src/soc/amd/common/vboot/vboot_bootblock.c @@ -2,13 +2,23 @@ #include <amdblocks/reset.h> #include <bl_uapp/bl_syscall_public.h> +#include <bootblock_common.h> #include <console/console.h> #include <pc80/mc146818rtc.h> #include <security/vboot/vbnv.h> #include <security/vboot/symbols.h> #include <soc/psp_transfer.h> +#include <timestamp.h> #include <2struct.h> +static int transfer_buffer_valid(const struct transfer_info_struct *ptr) +{ + if (ptr->magic_val == TRANSFER_MAGIC_VAL) + return 1; + else + return 0; +} + void verify_psp_transfer_buf(void) { if (*(uint32_t *)_vboot2_work == VB2_SHARED_DATA_MAGIC) { @@ -51,3 +61,43 @@ "Production" : "Pre-Production"); } } + +void boot_with_psp_timestamp(uint64_t base_timestamp) +{ + const struct transfer_info_struct *info = (const struct transfer_info_struct *) + (void *)(uintptr_t)_transfer_buffer; + + if (!transfer_buffer_valid(info) || info->timestamp == 0) + return; + + /* + * info->timestamp is PSP's timestamp (in microseconds) + * when x86 processor is released. + */ + uint64_t psp_last_ts = info->timestamp; + + int i; + struct timestamp_table *psp_ts_table = + (struct timestamp_table *)(void *) + ((uintptr_t)_transfer_buffer + info->timestamp_offset); + /* new base_timestamp will be offset for all PSP timestamps. */ + base_timestamp -= psp_last_ts; + + for (i = 0; i < psp_ts_table->num_entries; i++) { + struct timestamp_entry *tse = &psp_ts_table->entries[i]; + /* + * We ignore the time between x86 processor release and bootblock. + * Since timestamp_add subtracts base_time, we first add old base_time + * to make it absolute then add base_timestamp again since + * it'll be a new base_time. + * + * We don't need to convert unit since both PSP and coreboot + * will use 1us granularity. + * + */ + tse->entry_stamp += psp_ts_table->base_time + base_timestamp; + } + + bootblock_main_with_timestamp(base_timestamp, psp_ts_table->entries, + psp_ts_table->num_entries); +} diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 4bff042..0b52a17 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -3,7 +3,6 @@ #include <stdint.h> #include <symbols.h> #include <amdblocks/reset.h> -#include <timestamp.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/x86/cache.h> @@ -18,7 +17,6 @@ #include <soc/i2c.h> #include <amdblocks/amd_pci_mmconf.h> #include <acpi/acpi.h> -#include <security/vboot/vbnv.h> asmlinkage void bootblock_resume_entry(void); @@ -110,54 +108,6 @@ wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); } -static int transfer_buffer_valid(const struct transfer_info_struct *ptr) -{ - if (ptr->magic_val == TRANSFER_MAGIC_VAL) - return 1; - else - return 0; -} - -static void boot_with_psp_timestamp(uint64_t base_timestamp) -{ - const struct transfer_info_struct *info = (const struct transfer_info_struct *) - (void *)(uintptr_t)_transfer_buffer; - - if (!transfer_buffer_valid(info) || info->timestamp == 0) - return; - - /* - * info->timestamp is PSP's timestamp (in microseconds) - * when x86 processor is released. - */ - uint64_t psp_last_ts = info->timestamp; - - int i; - struct timestamp_table *psp_ts_table = - (struct timestamp_table *)(void *) - ((uintptr_t)_transfer_buffer + info->timestamp_offset); - /* new base_timestamp will be offset for all PSP timestamps. */ - base_timestamp -= psp_last_ts; - - for (i = 0; i < psp_ts_table->num_entries; i++) { - struct timestamp_entry *tse = &psp_ts_table->entries[i]; - /* - * We ignore the time between x86 processor release and bootblock. - * Since timestamp_add subtracts base_time, we first add old base_time - * to make it absolute then add base_timestamp again since - * it'll be a new base_time. - * - * We don't need to convert unit since both PSP and coreboot - * will use 1us granularity. - * - */ - tse->entry_stamp += psp_ts_table->base_time + base_timestamp; - } - - bootblock_main_with_timestamp(base_timestamp, psp_ts_table->entries, - psp_ts_table->num_entries); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index ce197c1..a6e85a7 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -46,6 +46,8 @@ void verify_psp_transfer_buf(void); /* Display the transfer block's PSP_info data */ void show_psp_transfer_info(void); +/* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */ +void boot_with_psp_timestamp(uint64_t); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f07d3ab12116229a13d2e8c02b2deb06e51a1af Gerrit-Change-Number: 47976 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: move vboot bootblock functions to common folder
by Felix Held (Code Review) 30 Nov '20

30 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47975 ) Change subject: soc/amd: move vboot bootblock functions to common folder ...................................................................... soc/amd: move vboot bootblock functions to common folder Change-Id: I9e9fed26a686b8f90797687dd720902be48dae72 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/vboot/Makefile.inc R src/soc/amd/common/vboot/vboot_bootblock.c M src/soc/amd/picasso/Makefile.inc 3 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/47975/1 diff --git a/src/soc/amd/common/vboot/Makefile.inc b/src/soc/amd/common/vboot/Makefile.inc index aff927a..8a6f116 100644 --- a/src/soc/amd/common/vboot/Makefile.inc +++ b/src/soc/amd/common/vboot/Makefile.inc @@ -4,3 +4,5 @@ romstage-y += vbnv_cmos.c ramstage-y += vbnv_cmos.c endif + +bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += vboot_bootblock.c diff --git a/src/soc/amd/picasso/bootblock/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c similarity index 100% rename from src/soc/amd/picasso/bootblock/vboot_bootblock.c rename to src/soc/amd/common/vboot/vboot_bootblock.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 5f4ab9b..f010c7b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -23,7 +23,6 @@ bootblock-y += smi_util.c bootblock-y += config.c bootblock-y += reset.c -bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += bootblock/vboot_bootblock.c romstage-y += i2c.c romstage-y += romstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/47975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e9fed26a686b8f90797687dd720902be48dae72 Gerrit-Change-Number: 47975 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: move assembly part of non-CAR bootblock to common directory
by Felix Held (Code Review) 30 Nov '20

30 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47880 ) Change subject: soc/amd: move assembly part of non-CAR bootblock to common directory ...................................................................... soc/amd: move assembly part of non-CAR bootblock to common directory There will be more files added to the common non-CAR Makefile.inc, so use an ifeq statement there. Change-Id: I1f71954d27fbf10725387a0e95bc57f5040024cc Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/cpu/Makefile.inc A src/soc/amd/common/block/cpu/noncar/Makefile.inc R src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/amd/picasso/Makefile.inc 4 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47880/1 diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index df2ccfa..6298f3b 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car +subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR) += noncar diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc new file mode 100644 index 0000000..7a3be34 --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y) + +bootblock-y += pre_c.S + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S similarity index 100% rename from src/soc/amd/picasso/bootblock/pre_c.S rename to src/soc/amd/common/block/cpu/noncar/pre_c.S diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 6ec4cd1..5f4ab9b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -11,7 +11,6 @@ subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage -bootblock-y += bootblock/pre_c.S bootblock-y += bootblock/bootblock.c bootblock-y += aoac.c bootblock-y += southbridge.c -- To view, visit https://review.coreboot.org/c/coreboot/+/47880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f71954d27fbf10725387a0e95bc57f5040024cc Gerrit-Change-Number: 47880 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: introduce SOC_AMD_COMMON_BLOCK_PCI_MMCONF
by Felix Held (Code Review) 30 Nov '20

30 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47878 ) Change subject: soc/amd/common: introduce SOC_AMD_COMMON_BLOCK_PCI_MMCONF ...................................................................... soc/amd/common: introduce SOC_AMD_COMMON_BLOCK_PCI_MMCONF Add a Kconfig symbol for including the PCIe MMCONF setup function in the build and select it when SOC_AMD_COMMON_BLOCK_PCI is selected and in the southbridges call enable_pci_mmconf(), but don't select SOC_AMD_COMMON_BLOCK_PCI. Change-Id: I32de7450bff5b231442f9f2094a18ebe01874ee7 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/pci/Kconfig M src/soc/amd/common/block/pci/Makefile.inc M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/cimx/sb800/Kconfig M src/southbridge/amd/pi/hudson/Kconfig 5 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/47878/1 diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index 74ea697..a59d87e 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -1,6 +1,14 @@ config SOC_AMD_COMMON_BLOCK_PCI bool default n + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF help This option builds functions used to program PCI interrupt routing, both PIC and APIC modes. + +config SOC_AMD_COMMON_BLOCK_PCI_MMCONF + bool + default n + help + Selecting this option adds the AMD-common enable_pci_mmconf function + to the build. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 1fed96e..e895397 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,8 +1,11 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c -# FIXME: This gets added when CONFIG_SOC_AMD_COMMON is set, which is a bit unexpected. +ifeq ($(SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) + bootblock-y += amd_pci_mmconf.c verstage_x86-y += amd_pci_mmconf.c romstage-y += amd_pci_mmconf.c postcar-y += amd_pci_mmconf.c ramstage-y += amd_pci_mmconf.c + +endif # SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index b755fe1..d0fbc49 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -16,6 +16,7 @@ select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR hex diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 96737cf..ecfc1e1 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -10,6 +10,7 @@ select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF if SOUTHBRIDGE_AMD_CIMX_SB800 config ENABLE_IDE_COMBINED_MODE diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 89dcad6..c87d7a0 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -19,6 +19,7 @@ select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR hex -- To view, visit https://review.coreboot.org/c/coreboot/+/47878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32de7450bff5b231442f9f2094a18ebe01874ee7 Gerrit-Change-Number: 47878 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Update GPIO configurations according to schematics
by Jonathan Zhang (Code Review) 30 Nov '20

30 Nov '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47229 ) Change subject: mb/ocp/deltalake: Update GPIO configurations according to schematics ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/47229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Gerrit-Change-Number: 47229 Gerrit-PatchSet: 8 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 30 Nov 2020 16:17:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Tim Crawford (Code Review) 30 Nov '20

30 Nov '20

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47892/3/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/47892/3/src/mainboard/system76/ory… PS3, Line 87: subsystemid 0x1558 0x95e6 inherit > Please check if it's correct in static.c in build/mainboard/.. Values in static.c are correct. I didn't notice anything in the FSP integration guide about the subsystem ID. Is it something that can be prevented so this value is written? -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 30 Nov 2020 15:32:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jslrvp: Modify the flash layout for fsp debug build
by V Sowmya (Code Review) 30 Nov '20

30 Nov '20

Hello Maulik V Vaghela, Krishna P Bhat D, Karthik Ramasubramanian, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48154 to look at the new patch set (#2). Change subject: mb/intel/jslrvp: Modify the flash layout for fsp debug build ...................................................................... mb/intel/jslrvp: Modify the flash layout for fsp debug build Current flash layout doesn't support the fsp debug builds since the FW_MAIN_A/B doesn't have enough space to hold the fsp debug binaries along with ME RW binaries. This patch reduces the SI_ALL size to 3.5MiB and increase the SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries. BRANCH=dedede TEST=Build jslrvp with fsp debug enabled. Cq-Depend: chrome-internal:3425366 Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/chromeos.fmd 1 file changed, 25 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/48154/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Gerrit-Change-Number: 48154 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lenovo/g505s: remove the unused and not present devices
by Mike Banon (Code Review) 30 Nov '20

30 Nov '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47913 ) Change subject: lenovo/g505s: remove the unused and not present devices ...................................................................... lenovo/g505s: remove the unused and not present devices Remove the devices unused or not present on this laptop. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I0decad499dfbb5f1e0a189d21f0fca47c80bd490 --- M src/mainboard/lenovo/g505s/acpi/routing.asl M src/mainboard/lenovo/g505s/mptable.c 2 files changed, 0 insertions(+), 183 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/47913/1 diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl index bf6a881..6f91672 100644 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ b/src/mainboard/lenovo/g505s/acpi/routing.asl @@ -19,12 +19,6 @@ Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, @@ -37,20 +31,6 @@ Package(){0x0005FFFF, 2, INTD, 0 }, Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 1, INTB, 0 }, @@ -75,12 +55,6 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 PCIe Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, }) Name(APR0, Package(){ @@ -97,12 +71,6 @@ Package(){0x0002FFFF, 2, 0, 16 }, Package(){0x0002FFFF, 3, 0, 17 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, 0, 16 }, Package(){0x0004FFFF, 1, 0, 17 }, @@ -115,20 +83,6 @@ Package(){0x0005FFFF, 2, 0, 19 }, Package(){0x0005FFFF, 3, 0, 16 }, - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, @@ -153,12 +107,6 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, }) Name(PS2, Package(){ @@ -205,107 +153,13 @@ Package(){0x0000FFFF, 2, 0, 19 }, Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, }) Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, }) - Name(PS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, }) Name(APS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - /* SB PCI Bridge J21, J22 */ Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, }) diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index bc1759a..5d8eb4d 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -124,43 +124,6 @@ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); -- To view, visit https://review.coreboot.org/c/coreboot/+/47913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0decad499dfbb5f1e0a189d21f0fca47c80bd490 Gerrit-Change-Number: 47913 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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