coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz
by Patrick Georgi (Code Review) 30 Nov '20

30 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47736 ) Change subject: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz ...................................................................... mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:173670150 TEST=Verified that I2C5 frequency is between 386-387kHz. Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47736 Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> Reviewed-by: Zhuohao Lee <zhuohao(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, approved Zhuohao Lee: Looks good to me, but someone else must approve Frank Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index bd4bf80..904f3e0 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -2,6 +2,49 @@ register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + # Acoustic settings register "AcousticNoiseMitigation" = "1" register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" -- To view, visit https://review.coreboot.org/c/coreboot/+/47736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Gerrit-Change-Number: 47736 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add initial chipset.cb
by Tim Wawrzynczak (Code Review) 30 Nov '20

30 Nov '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48009 ) Change subject: soc/intel/alderlake: Add initial chipset.cb ...................................................................... soc/intel/alderlake: Add initial chipset.cb Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 --- M src/soc/intel/alderlake/Kconfig A src/soc/intel/alderlake/chipset.cb 2 files changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/48009/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0aab3c5..7e693cb 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -92,6 +92,10 @@ Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. +config CHIPSET_DEVICETREE + string + default "soc/intel/alderlake/chipset.cb" + config IFD_CHIPSET string default "adl" diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb new file mode 100644 index 0000000..ff81560 --- /dev/null +++ b/src/soc/intel/alderlake/chipset.cb @@ -0,0 +1,67 @@ +chip soc/intel/alderlake + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 01.0 alias pcie5 off end + device pci 02.0 alias igpu off end + device pci 04.0 alias dtt off end + device pci 06.0 alias pcie4_0 off end + device pci 06.2 alias pcie4_1 off end + device pci 07.0 alias tbt_pcie_rp0 off end + device pci 07.1 alias tbt_pcie_rp1 off end + device pci 07.2 alias tbt_pcie_rp2 off end + device pci 07.3 alias tbt_pcie_rp3 off end + device pci 08.0 alias gna off end + device pci 09.0 alias north_tracehub off end + device pci 0a.0 alias crashlog off end + device pci 0d.0 alias north_xhci off end + device pci 0d.1 alias north_xdci off end + device pci 0d.2 alias tbt_dma0 off end + device pci 0d.3 alias tbt_dma1 off end + device pci 0e.0 alias vmd off end + device pci 10.6 alias thc0 off end + device pci 10.7 alias thc1 off end + device pci 12.0 alias ish off end + device pci 12.6 alias gspi2 off end + device pci 13.0 alias gspi3 off end + device pci 14.0 alias south_xhci off end + device pci 14.1 alias south_xdci off end + device pci 14.2 alias shared_sram off end + device pci 14.3 alias cnvi_wifi off end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 16.0 alias heci1 off end + device pci 16.1 alias heci2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias sata off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1c.4 alias pcie_rp5 off end + device pci 1c.5 alias pcie_rp6 off end + device pci 1c.6 alias pcie_rp7 off end + device pci 1c.7 alias pcie_rp8 off end + device pci 1d.0 alias pcie_rp9 off end + device pci 1d.1 alias pcie_rp10 off end + device pci 1d.2 alias pcie_rp11 off end + device pci 1d.3 alias pcie_rp12 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1f.0 alias pch_espi on end + device pci 1f.1 alias p2sb off end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias south_tracehub off end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/48009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Gerrit-Change-Number: 48009 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/device/pci_ids.h: Fix device id for gspi2
by Bora Guvendik (Code Review) 30 Nov '20

30 Nov '20

Hello Selma Bensaid, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48060 to review the following change. Change subject: include/device/pci_ids.h: Fix device id for gspi2 ...................................................................... include/device/pci_ids.h: Fix device id for gspi2 Device ID for "D18:F6 - GSPI #2" shoud be 0xA0FB BUG=none TEST=Boot to OS, verify SSDT Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.com> Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I0d814170d24ff1b989eceb1d9ebdf6134df85e2e --- M src/include/device/pci_ids.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/48060/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c123002..51c0abf 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3563,7 +3563,7 @@ #define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4 #define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa #define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab -#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0x34fb +#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0xa0fb #define PCI_DEVICE_ID_INTEL_TGP_GSPI3 0xa0fd #define PCI_DEVICE_ID_INTEL_TGP_GSPI4 0xa0fe #define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de -- To view, visit https://review.coreboot.org/c/coreboot/+/48060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d814170d24ff1b989eceb1d9ebdf6134df85e2e Gerrit-Change-Number: 48060 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA de...
by Tim Wawrzynczak (Code Review) 30 Nov '20

30 Nov '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47410 ) Change subject: soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devices ...................................................................... soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devices Change-Id: I6289d2049fbbb6bb532be3d9e2355c563ec98d1b Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/tigerlake/include/soc/pci_devs.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/47410/1 diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index cfb70cd..9a74e33 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -50,6 +50,8 @@ #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) #define SA_DEV_SLOT_TCSS 0x0d +#define NUM_TCSS_DMA_FUNCTIONS 2 +#define SA_DEVFN_TCSS_DMA(x) PCI_DEVFN(SA_DEV_SLOT_TCSS, (x + 2)) #define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) #define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) #define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) -- To view, visit https://review.coreboot.org/c/coreboot/+/47410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6289d2049fbbb6bb532be3d9e2355c563ec98d1b Gerrit-Change-Number: 47410 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: elog: Add new wake source codes
by Tim Wawrzynczak (Code Review) 30 Nov '20

30 Nov '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47395 ) Change subject: elog: Add new wake source codes ...................................................................... elog: Add new wake source codes Tiger Lake introduces new wake-capable devices, including thunderbolt ports, TCSS XHCI & XDCI as well as DMA ports. Add new ELOG_WAKE_SOURCE macros for each of these types of devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456 --- M src/include/elog.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47395/1 diff --git a/src/include/elog.h b/src/include/elog.h index 8c50e00..ed1722b 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -120,6 +120,11 @@ #define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a #define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b #define ELOG_WAKE_SOURCE_GPIO 0x2c +#define ELOG_WAKE_SOURCE_PME_TBT 0x2d +#define ELOG_WAKE_SOURCE_PME_TCSS_XHCI 0x2e +#define ELOG_WAKE_SOURCE_PME_TCSS_XDCI 0x2f +#define ELOG_WAKE_SOURCE_PME_TCSS_DMA0 0x30 +#define ELOG_WAKE_SOURCE_PME_TCSS_DMA1 0x31 struct elog_event_data_wake { u8 source; -- To view, visit https://review.coreboot.org/c/coreboot/+/47395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456 Gerrit-Change-Number: 47395 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/docker/Makefile: Add missing separator
by Frans Hendriks (Code Review) 30 Nov '20

30 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47992 ) Change subject: util/docker/Makefile: Add missing separator ...................................................................... util/docker/Makefile: Add missing separator Build using docker results in error: Makefile:86: *** missing separator. Add space after ifeq. Tested: Building Facebook FBG1701 binary. Change-Id: Ib42abe966e67dac380173ec982c9f6bd4cf074cc Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M util/docker/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/47992/1 diff --git a/util/docker/Makefile b/util/docker/Makefile index 8b1d0ef..cf14c0d 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -83,7 +83,7 @@ @$(MAKE) clean-coreboot-images docker-cleanall: test-docker -ifeq($(Y),1) +ifeq ($(Y),1) @if [ -n "$$($(DOCKER) ps -a | grep -v "CONTAINER")" ]; then \ $(DOCKER) kill $$($(DOCKER) ps | grep -v "CONTAINER" | sed 's|\s.*$$||') ; \ $(DOCKER) rm $$($(DOCKER) ps -a | grep -v "CONTAINER" | sed 's|\s.*$$||'); \ -- To view, visit https://review.coreboot.org/c/coreboot/+/47992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib42abe966e67dac380173ec982c9f6bd4cf074cc Gerrit-Change-Number: 47992 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variant/copano: Add memory part support
by Nick Vaccaro (Code Review) 30 Nov '20

30 Nov '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47981 ) Change subject: mb/google/volteer/variant/copano: Add memory part support ...................................................................... mb/google/volteer/variant/copano: Add memory part support Add support for the following 5 LPDDR4x memory parts: - MT53E512M64D4NW-046 WT:E - H9HCNNNCRMBLPR-NEE - MT53D1G64D4NW-046 WT:A - H9HCNNNFBMBLPR-NEE - MT53D512M64D4NW-046 WT:F BUG=b:172993397 TEST=none Change-Id: Iff8f6257c6cff77fc3f0bda7e75434f9f4de1777 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- A src/mainboard/google/volteer/variants/copano/memory/Makefile.inc A src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt 3 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/47981/1 diff --git a/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc b/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc new file mode 100644 index 0000000..4a7f1d7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E, H9HCNNNCRMBLPR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53D1G64D4NW-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNFBMBLPR-NEE +SPD_SOURCES += lp4x-spd-6.hex # ID = 3(0b0011) Parts = MT53D512M64D4NW-046 WT:F diff --git a/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt new file mode 100644 index 0000000..5dc1ebd --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +MT53E512M64D4NW-046 WT:E 0 (0000) +H9HCNNNCRMBLPR-NEE 0 (0000) +MT53D1G64D4NW-046 WT:A 1 (0001) +H9HCNNNFBMBLPR-NEE 2 (0010) +MT53D512M64D4NW-046 WT:F 3 (0011) diff --git a/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt new file mode 100644 index 0000000..4afc390 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt @@ -0,0 +1,5 @@ +MT53E512M64D4NW-046 WT:E +H9HCNNNCRMBLPR-NEE +MT53D1G64D4NW-046 WT:A +H9HCNNNFBMBLPR-NEE +MT53D512M64D4NW-046 WT:F -- To view, visit https://review.coreboot.org/c/coreboot/+/47981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff8f6257c6cff77fc3f0bda7e75434f9f4de1777 Gerrit-Change-Number: 47981 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs
by Nick Vaccaro (Code Review) 30 Nov '20

30 Nov '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47980 ) Change subject: lp4x: Add new memory parts and generate SPDs ...................................................................... lp4x: Add new memory parts and generate SPDs Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics. Add new generic SPD lp4x-spd-6.hex based on attributes of MT53D512M64D4NW-046 WT:F. BUG=b:172993397 TEST=none Change-Id: I09c6eab640c169dbdb451964967d14a31e314496 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- A src/soc/intel/tigerlake/spd/lp4x-spd-6.hex M src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 3 files changed, 46 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47980/1 diff --git a/src/soc/intel/tigerlake/spd/lp4x-spd-6.hex b/src/soc/intel/tigerlake/spd/lp4x-spd-6.hex new file mode 100644 index 0000000..f330d4b --- /dev/null +++ b/src/soc/intel/tigerlake/spd/lp4x-spd-6.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 00 08 00 00 00 00 02 01 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt index c7e9690..3450f1f 100644 --- a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt @@ -16,3 +16,4 @@ H9HCNNNCRMBLPR-NEE,lp4x-spd-1.hex H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex +MT53D512M64D4NW-046 WT:F,lp4x-spd-6.hex diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt index 91062d0..7dc502e 100644 --- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt @@ -217,6 +217,18 @@ "ranksPerChannel": 1, "speedMbps": 4267 } - } + }, + { + "name": "MT53D512M64D4NW-046 WT:F", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 1, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } + } ] } -- To view, visit https://review.coreboot.org/c/coreboot/+/47980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09c6eab640c169dbdb451964967d14a31e314496 Gerrit-Change-Number: 47980 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Use PCH_DEV_SMBUS definition
by Angel Pons (Code Review) 30 Nov '20

30 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47959 ) Change subject: mb/prodrive/hermes: Use PCH_DEV_SMBUS definition ...................................................................... mb/prodrive/hermes: Use PCH_DEV_SMBUS definition This allows dropping ugly preprocessor usage from this file. Change-Id: Idb66d295129d98725f38d11ac162978418bd94c2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/hermes/eeprom.c 1 file changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47959/1 diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index 94811f6..fee40a0 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -31,14 +31,8 @@ { int ret = 0; -#if ENV_ROMSTAGE - pci_devfn_t dev = PCI_DEV(0, PCH_DEV_SLOT_LPC, 4); -#else - const struct device *dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 4); -#endif - - u32 smb_ctrl_reg = pci_read_config32(dev, HOSTC); - pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN); + u32 smb_ctrl_reg = pci_read_config32(PCH_DEV_SMBUS, HOSTC); + pci_write_config32(PCH_DEV_SMBUS, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN); printk(BIOS_SPEW, "%s\tOffset: %04zx\tSize: %02zx\n", __func__, read_offset, size); @@ -61,7 +55,7 @@ } /* Restore I2C_EN bit */ - pci_write_config32(dev, HOSTC, smb_ctrl_reg); + pci_write_config32(PCH_DEV_SMBUS, HOSTC, smb_ctrl_reg); return ret; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb66d295129d98725f38d11ac162978418bd94c2 Gerrit-Change-Number: 47959 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Encapsulate GPIO setup
by Angel Pons (Code Review) 30 Nov '20

30 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47958 ) Change subject: mb/prodrive/hermes: Encapsulate GPIO setup ...................................................................... mb/prodrive/hermes: Encapsulate GPIO setup Having variants' gpio.c call the `gpio_configure_pads` function results in an API that does not need to pass data around, which is much simpler. Change-Id: I1064dc6258561bcf83f0e249d65b823368cf0d31 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/hermes/bootblock.c M src/mainboard/prodrive/hermes/ramstage.c M src/mainboard/prodrive/hermes/variants/baseboard/gpio.c M src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h 4 files changed, 13 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47958/1 diff --git a/src/mainboard/prodrive/hermes/bootblock.c b/src/mainboard/prodrive/hermes/bootblock.c index 1426a55..40fd0b4 100644 --- a/src/mainboard/prodrive/hermes/bootblock.c +++ b/src/mainboard/prodrive/hermes/bootblock.c @@ -6,20 +6,12 @@ #include <variant/gpio.h> #include "gpio.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't do. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - size_t num = 0; - const struct pad_config *early_gpio_table = get_early_gpio_table(&num); - - gpio_configure_pads(early_gpio_table, num); -} - void bootblock_mainboard_early_init(void) { - early_config_gpio(); + /* This is a hack for FSP because it does things in MemoryInit() + which it shouldn't do. We have to prepare certain gpios here + because of the brokenness in FSP. */ + program_early_gpio_pads(); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c index 135d775..e3dfffc 100644 --- a/src/mainboard/prodrive/hermes/ramstage.c +++ b/src/mainboard/prodrive/hermes/ramstage.c @@ -10,12 +10,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) { - size_t num = 0; - const struct pad_config *gpio_table = get_gpio_table(&num); - /* Configure pads prior to SiliconInit() in case there's any dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, num); + program_gpio_pads(); params->SataLedEnable = 1; diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c index 8735a9e..096dc35 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c +++ b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c @@ -2,6 +2,8 @@ #include "include/variant/gpio.h" #include <commonlib/helpers.h> +#include <soc/gpio.h> +#include <intelblocks/gpio_defs.h> /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { @@ -389,14 +391,12 @@ PAD_CFG_GPO(GPP_H5, 0, DEEP), /* PCH_HBLED_n */ }; -const struct pad_config *get_gpio_table(size_t *num) +void program_gpio_pads(void) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } -const struct pad_config *get_early_gpio_table(size_t *num) +void program_early_gpio_pads(void) { - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h index 50d1801..8fce3c8 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h @@ -3,10 +3,7 @@ #ifndef PCH_GPIO_H #define PCH_GPIO_H -#include <soc/gpio.h> -#include <intelblocks/gpio_defs.h> - -const struct pad_config *get_gpio_table(size_t *num); -const struct pad_config *get_early_gpio_table(size_t *num); +void program_gpio_pads(void); +void program_early_gpio_pads(void); #endif /* PCH_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1064dc6258561bcf83f0e249d65b823368cf0d31 Gerrit-Change-Number: 47958 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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