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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: rework gpio setup to not use headers
by Michael Niewöhner (Code Review) 29 Nov '20

29 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48087 ) Change subject: mb/supermicro/x11-lga1151-series: rework gpio setup to not use headers ...................................................................... mb/supermicro/x11-lga1151-series: rework gpio setup to not use headers Rework gpio setup for the board series to not use headers but stage-specific compilation units. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48087 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/supermicro/x11-lga1151-series/Makefile.inc M src/mainboard/supermicro/x11-lga1151-series/bootblock.c A src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h M src/mainboard/supermicro/x11-lga1151-series/mainboard.c R src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c R src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c R src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c A src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c 10 files changed, 100 insertions(+), 70 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index f9b4e98..035dd28 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -1,10 +1,11 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += bootblock.c - -ramstage-y += mainboard.c - CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +ramstage-y += mainboard.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c index 3e5751c..b137c75 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c +++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c @@ -1,20 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <soc/gpio.h> -#include <variant/gpio.h> +#include <mainboard/gpio.h> #include <superio/aspeed/common/aspeed.h> #include <superio/aspeed/ast2400/ast2400.h> #include <console/uart.h> -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't do. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - static void early_config_superio(void) { const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); @@ -23,6 +14,6 @@ void bootblock_mainboard_early_init(void) { - early_config_gpio(); + mainboard_configure_early_gpios(); early_config_superio(); } diff --git a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h new file mode 100644 index 0000000..c6393be --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 1377a87..0f8dbed 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -2,8 +2,7 @@ #include <mainboard.h> #include <device/device.h> -#include <soc/ramstage.h> -#include <variant/gpio.h> +#include <mainboard/gpio.h> __weak void variant_mainboard_init(void *chip_info) { @@ -12,7 +11,7 @@ static void mainboard_chip_init(void *chip_info) { /* do common init */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + mainboard_configure_gpios(); /* do variant init */ variant_mainboard_init(chip_info); diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c similarity index 91% rename from src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h rename to src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c index 449349d..e37e008 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _GPIO_X11SSH_F_H -#define _GPIO_X11SSH_F_H - +#include <mainboard/gpio.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -226,17 +224,7 @@ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), }; -static const struct pad_config early_gpio_table[] = { - /* Early LPC configuration in romstage */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -}; - -#endif /* _GPIO_X11SSH_F_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c new file mode 100644 index 0000000..3ea21e0 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c similarity index 91% rename from src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h rename to src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c index 486caf4..06d3bd4 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _GPIO_X11SSH_TF_H -#define _GPIO_X11SSH_TF_H - +#include <mainboard/gpio.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -226,17 +224,7 @@ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), }; -static const struct pad_config early_gpio_table[] = { - /* Early LPC configuration in romstage */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -}; - -#endif /* _GPIO_X11SSH_TF_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c new file mode 100644 index 0000000..3ea21e0 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c similarity index 92% rename from src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h rename to src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c index 8c9d08e..dc41573 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _GPIO_X11SSM_F_H -#define _GPIO_X11SSM_F_H - +#include <mainboard/gpio.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -232,17 +230,7 @@ PAD_NC(GPD11, NONE), }; -static const struct pad_config early_gpio_table[] = { - /* Early LPC configuration in romstage */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -}; - -#endif /* _GPIO_X11SSM_F_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c new file mode 100644 index 0000000..3ea21e0 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e Gerrit-Change-Number: 48087 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.init
by Michael Niewöhner (Code Review) 29 Nov '20

29 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48083 ) Change subject: mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.init ...................................................................... mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.init GPIO needs to be initialized before the IPMI device gets initialized, so the GPIOs can be read/set by the code in CB:48096 and CB:48094. Thus, use mainboard_ops.init for GPIO configuration instead of using the indirection via a mainboard_enable function. To make it more visible, that we use chip.init, rename `mainboard_init` to `mainboard_chip_init`. Tested successfully on X11SSM-F including the IPMI changes. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I192e69a34fa262b38bc40a95fb11c22a4041d0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/48083 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h M src/mainboard/supermicro/x11-lga1151-series/mainboard.c M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c 3 files changed, 6 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h index c63b434..cad75f4 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h +++ b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h @@ -5,6 +5,6 @@ #include <device/device.h> -void variant_mainboard_init(struct device *dev); +void variant_mainboard_init(void *chip_info); #endif /* _BASEBOARD_X11_LGA1151_SERIES_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 92718e8..1377a87 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -5,24 +5,19 @@ #include <soc/ramstage.h> #include <variant/gpio.h> -__weak void variant_mainboard_init(struct device *dev) +__weak void variant_mainboard_init(void *chip_info) { } -static void mainboard_init(struct device *dev) +static void mainboard_chip_init(void *chip_info) { /* do common init */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); /* do variant init */ - variant_mainboard_init(dev); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; + variant_mainboard_init(chip_info); } struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .init = mainboard_chip_init, }; diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c index 0b26e06..75351eb 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c @@ -5,7 +5,7 @@ #include <intelblocks/pcr.h> #include <soc/pcr_ids.h> -void variant_mainboard_init(struct device *dev) +void variant_mainboard_init(void *chip_info) { // TODO: NMI; is this needed? vendor sets it pcr_write32(0xae, 0x01e4, 0x00000004); -- To view, visit https://review.coreboot.org/c/coreboot/+/48083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I192e69a34fa262b38bc40a95fb11c22a4041d0ae Gerrit-Change-Number: 48083 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.init
by Arthur Heymans (Code Review) 29 Nov '20

29 Nov '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48083 ) Change subject: mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.init ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I192e69a34fa262b38bc40a95fb11c22a4041d0ae Gerrit-Change-Number: 48083 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 29 Nov 2020 06:45:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for LPDDR5
by Angel Pons (Code Review) 28 Nov '20

28 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46899 ) Change subject: mb/intel/adlrvp: Add support for LPDDR5 ...................................................................... Patch Set 14: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/46899/14/src/mainboard/intel/adlrv… File src/mainboard/intel/adlrvp/memory.c: https://review.coreboot.org/c/coreboot/+/46899/14/src/mainboard/intel/adlrv… PS14, Line 51: { 3, 2, 1, 0, 5, 4, 6, 7, 15, 14, 12, 13, 8, 9, 10, 11 }, : { 0, 2, 3, 1, 5, 7, 4, 6, 14, 13, 15, 12, 8, 9, 11, 10 }, : { 1, 2, 0, 3, 4, 6, 5, 7, 15, 13, 12, 14, 9, 10, 8, 11 }, : { 2, 1, 3, 0, 7, 4, 5, 6, 13, 12, 15, 14, 9, 11, 8, 10 }, : { 1, 2, 3, 0, 6, 4, 5, 7, 15, 13, 14, 12, 10, 9, 8, 11 }, : { 1, 0, 3, 2, 6, 7, 4, 5, 14, 12, 15, 13, 8, 9, 10, 11 }, : { 0, 2, 1, 3, 4, 7, 5, 6, 12, 13, 15, 14, 9, 11, 10, 8 }, : { 3, 2, 1, 0, 5, 4, 6, 7, 13, 15, 11, 12, 10, 9, 14, 8 } I'd format this as follows: { 3, 2, 1, 0, 5, 4, 6, 7, 15, 14, 12, 13, 8, 9, 10, 11 }, { 0, 2, 3, 1, 5, 7, 4, 6, 14, 13, 15, 12, 8, 9, 11, 10 }, { 1, 2, 0, 3, 4, 6, 5, 7, 15, 13, 12, 14, 9, 10, 8, 11 }, { 2, 1, 3, 0, 7, 4, 5, 6, 13, 12, 15, 14, 9, 11, 8, 10 }, { 1, 2, 3, 0, 6, 4, 5, 7, 15, 13, 14, 12, 10, 9, 8, 11 }, { 1, 0, 3, 2, 6, 7, 4, 5, 14, 12, 15, 13, 8, 9, 10, 11 }, { 0, 2, 1, 3, 4, 7, 5, 6, 12, 13, 15, 14, 9, 11, 10, 8 }, { 3, 2, 1, 0, 5, 4, 6, 7, 13, 15, 11, 12, 10, 9, 14, 8 }, This way, the columns are aligned https://review.coreboot.org/c/coreboot/+/46899/14/src/mainboard/intel/adlrv… PS14, Line 58: } minor nit: add a comma for consistency? -- To view, visit https://review.coreboot.org/c/coreboot/+/46899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Gerrit-Change-Number: 46899 Gerrit-PatchSet: 14 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 28 Nov 2020 14:42:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add lp5_ccc_config to the board memory configura...
by Angel Pons (Code Review) 28 Nov '20

28 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47436 ) Change subject: soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Gerrit-Change-Number: 47436 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 28 Nov 2020 14:37:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11ssm-f: drop unneeded ITSS override
by Michael Niewöhner (Code Review) 28 Nov '20

28 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48084 ) Change subject: mb/supermicro/x11ssm-f: drop unneeded ITSS override ...................................................................... mb/supermicro/x11ssm-f: drop unneeded ITSS override The ITSS override is not needed for LPC_CLKOUT* pads. Drop it. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I3dbbc8944751779151dcd4f92fb870d937801d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48084 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c 1 file changed, 0 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c index 6f99d07..0b26e06 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c @@ -2,21 +2,11 @@ #include <mainboard.h> #include <device/device.h> -#include <intelblocks/itss.h> #include <intelblocks/pcr.h> -#include <soc/itss.h> #include <soc/pcr_ids.h> void variant_mainboard_init(struct device *dev) { - /* TODO: - * Find out why the polarities from gpio.h gets overwritten by FSP. - * This sets irq polarity to the same values as vendor - * but I do not know if this is really needed.... - */ - itss_set_irq_polarity(33, 0); - itss_set_irq_polarity(34, 0); - // TODO: NMI; is this needed? vendor sets it pcr_write32(0xae, 0x01e4, 0x00000004); pcr_write32(0xae, 0x01e8, 0x00000040); -- To view, visit https://review.coreboot.org/c/coreboot/+/48084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3dbbc8944751779151dcd4f92fb870d937801d69 Gerrit-Change-Number: 48084 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: configure gpios in mainboard init
by Michael Niewöhner (Code Review) 28 Nov '20

28 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48086 ) Change subject: mb/supermicro/x11-lga1151-series: configure gpios in mainboard init ...................................................................... mb/supermicro/x11-lga1151-series: configure gpios in mainboard init Move gpio configuration from the Fsp callback to mainboard init. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: If2a54c75c5243d94cdc025c597ee347820b35d32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48086 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/Makefile.inc M src/mainboard/supermicro/x11-lga1151-series/mainboard.c D src/mainboard/supermicro/x11-lga1151-series/ramstage.c 3 files changed, 4 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index d64fcb3..f9b4e98 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -2,7 +2,7 @@ bootblock-y += bootblock.c -ramstage-y += ramstage.c +ramstage-y += mainboard.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 0380c98..92718e8 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -2,6 +2,8 @@ #include <mainboard.h> #include <device/device.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> __weak void variant_mainboard_init(struct device *dev) { @@ -10,7 +12,7 @@ static void mainboard_init(struct device *dev) { /* do common init */ - // placeholder for common mainboard initialization + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); /* do variant init */ variant_mainboard_init(dev); diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c deleted file mode 100644 index 9262e2e..0000000 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/ramstage.h> -#include <variant/gpio.h> - -void mainboard_silicon_init_params(FSP_SIL_UPD *params) -{ - /* Configure pads prior to SiliconInit() in case there's any - dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/48086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2a54c75c5243d94cdc025c597ee347820b35d32 Gerrit-Change-Number: 48086 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: restructure and clean up devicetree
by Michael Niewöhner (Code Review) 28 Nov '20

28 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48082 ) Change subject: mb/supermicro/x11-lga1151-series: restructure and clean up devicetree ...................................................................... mb/supermicro/x11-lga1151-series: restructure and clean up devicetree Drop zero-value devicetree options and move PcieRpEnable options down to the corresponding devices. Test: built with TIMELESS=1; binaries remain identical Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I9285d786e973621a732e2627c734adc930e54207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb 3 files changed, 9 insertions(+), 41 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index e7b26dc..c021372 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -1,10 +1,6 @@ chip soc/intel/skylake - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" - # FSP Configuration - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Disabled" @@ -22,20 +18,6 @@ [7] = 1, \ }" - register "SataPortsDevSlp" = "{\ - [0] = 0, \ - [1] = 0, \ - [2] = 0, \ - [3] = 0, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ - }" - - # superspeed_inter-chip_supplement (SSIC) disabled - register "SsicPortEnable" = "0" - # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -46,9 +28,6 @@ register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" - # No extra VR mailbox command - register "SendVrMbxCmd" = "0" - # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 7996791..093786c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -11,19 +11,6 @@ register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # PCIe configuration - # Enable JPCIE1 - register "PcieRpEnable[0]" = "1" - - # Enable ASpeed PCI bridge - register "PcieRpEnable[2]" = "1" - - # Enable X550T (10GbE) - register "PcieRpEnable[4]" = "1" - - # Enable M.2 - register "PcieRpEnable[8]" = "1" - # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" @@ -66,9 +53,11 @@ device domain 0 on device pci 01.0 on end # unused device pci 01.1 on # PCIE Slot (JPCIE1) + register "PcieRpEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" end device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1) + register "PcieRpEnable[2]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" end device pci 1c.2 on # PCI Express Port 3 @@ -77,10 +66,12 @@ end end device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" device pci 00.0 on end # 10GbE device pci 00.1 on end # 10GbE end device pci 1d.0 on # PCI Express Port 9 + register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device pci 1f.0 on # LPC Interface diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 8b0a2a0..d7f1873 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -11,13 +11,6 @@ register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # PCIe configuration - register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 - register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 - register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 - register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 - register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA - # USB configuration # USB0/1 register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" @@ -58,18 +51,23 @@ smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" end device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) + register "PcieRpEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) + register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1d.0 on # PCH PCIe Port 9 + register "PcieRpEnable[8]" = "1" device pci 00.0 on end # GbE 1 end device pci 1d.1 on # PCH PCIe Port 10 + register "PcieRpEnable[9]" = "1" device pci 00.1 on end # GbE 2 end device pci 1d.2 on # PCH PCIe Port 11 + register "PcieRpEnable[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end -- To view, visit https://review.coreboot.org/c/coreboot/+/48082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9285d786e973621a732e2627c734adc930e54207 Gerrit-Change-Number: 48082 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: restructure and clean up devicetree
by Michael Niewöhner (Code Review) 28 Nov '20

28 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48082 ) Change subject: mb/supermicro/x11-lga1151-series: restructure and clean up devicetree ...................................................................... Patch Set 8: (1 comment) > Patch Set 4: Code-Review+1 > > Please check if the binary is identical done https://review.coreboot.org/c/coreboot/+/48082/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48082/4//COMMIT_MSG@9 PS4, Line 9: Drop zero-value devicetree options and move PcieRpEnable options down to : the corresponding devices. > Those should result in identical binaries with BUILD_TIMELESS=1. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/48082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9285d786e973621a732e2627c734adc930e54207 Gerrit-Change-Number: 48082 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 28 Nov 2020 12:57:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: correct OC pin skip value for disabled usb ports
by Michael Niewöhner (Code Review) 28 Nov '20

28 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48003 ) Change subject: soc/intel/skl: correct OC pin skip value for disabled usb ports ...................................................................... soc/intel/skl: correct OC pin skip value for disabled usb ports Commit 056d552 introduced a bug where 0xFF gets set as OC pin value to supposedly skip programming an OC pin for a disabled USB port. While the value is correct for the other platforms, Skylake uses 0x08 for this purpose. Correct this by using the enum value OC_SKIP (0x08) instead. Change-Id: I41a8df3dce3712b4ab27c4e6e10160b2207406d1 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48003 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/chip.c 1 file changed, 6 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index e2aee07..ada06f2 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -26,6 +26,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include <soc/usb.h> #include <string.h> #include "chip.h" @@ -151,16 +152,16 @@ if (config->usb2_ports[i].enable) params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; else - params->Usb2OverCurrentPin[i] = 0xff; + params->Usb2OverCurrentPin[i] = OC_SKIP; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - if (config->usb3_ports[i].enable) { + if (config->usb3_ports[i].enable) params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; - } else { - params->Usb3OverCurrentPin[i] = 0xff; - } + else + params->Usb3OverCurrentPin[i] = OC_SKIP; + if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = -- To view, visit https://review.coreboot.org/c/coreboot/+/48003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41a8df3dce3712b4ab27c4e6e10160b2207406d1 Gerrit-Change-Number: 48003 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2020