coreboot-gerrit November 2020

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Change in coreboot[master]: mb/siemens/mc_apl1/mainboard.c: Refactor loop body
by Patrick Georgi (Code Review) 30 Nov '20

30 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47403 ) Change subject: mb/siemens/mc_apl1/mainboard.c: Refactor loop body ...................................................................... mb/siemens/mc_apl1/mainboard.c: Refactor loop body Break down multi-line compound conditions into multiple if-statements, and leverage `continue` statements to avoid nesting multiple checks. Change-Id: I5edc279a57e25a0dff1a4b42f0bbc88c0659b476 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47403 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Tested-by: siemens-bot Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/mainboard.c 1 file changed, 10 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified siemens-bot: Verified Werner Zeh: Looks good to me, approved Uwe Poeche: Looks good to me, but someone else must approve diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 0d93563..5b8f70f 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -85,19 +85,18 @@ /* Open main hwinfo block */ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) return CB_ERR; - /* Now try to find a valid MAC address in hwinfo for this mapping.*/ + /* Now try to find a valid MAC address in hwinfo for this mapping. */ for (i = 0; i < MAX_NUM_MAPPINGS; i++) { - if ((hwilib_get_field(XMac1Mapping + i, buf, 16) == 16) && - !(memcmp(buf, mapping, chain_len + 4))) { - /* There is a matching mapping available, get MAC address. */ - if ((hwilib_get_field(XMac1 + i, mac, 6) == 6) && - (is_mac_adr_valid(mac))) { - return CB_SUCCESS; - } else { - return CB_ERR; - } - } else + if (hwilib_get_field(XMac1Mapping + i, buf, 16) != 16) continue; + if (memcmp(buf, mapping, chain_len + 4)) + continue; + /* There is a matching mapping available, get MAC address. */ + if (hwilib_get_field(XMac1 + i, mac, 6) == 6) { + if (is_mac_adr_valid(mac)) + return CB_SUCCESS; + } + return CB_ERR; } /* No MAC address found for */ return CB_ERR; -- To view, visit https://review.coreboot.org/c/coreboot/+/47403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5edc279a57e25a0dff1a4b42f0bbc88c0659b476 Gerrit-Change-Number: 47403 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: [WIP]src/arch/x86:Add support for low power idle table
by Shaunak Saha (Code Review) 30 Nov '20

30 Nov '20

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: [WIP]src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 5: > Patch Set 5: > > Any news? :-) If you need any help with this or in case you don't have the time to finalize it, I can take that if you wish. Just let me know Hi Michael. Sorry, i was still waiting for Angle's reply for the location of the change and was busy with some other high priority issues. Thanks for asking, please go ahead and take it over. The present form of patch is working. I had verifies it with 5.4 kernel. -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 30 Nov 2020 07:12:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variant/eldrid: switch to devtree aliases for PMC M...
by Scott Chao (Code Review) 29 Nov '20

29 Nov '20

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48066 ) Change subject: mb/google/volteer/variant/eldrid: switch to devtree aliases for PMC MUX connectors ...................................................................... mb/google/volteer/variant/eldrid: switch to devtree aliases for PMC MUX connectors Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. BUG=b:172528109 BRANCH=firmware-volteer-13521.B TEST=built and USB3.0, type-c display work. Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: Iedf9b972b341064ff62a4443bfa83f69c8c60108 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48066/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 72571c0..e5eb0d8 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -158,6 +158,13 @@ device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" @@ -175,14 +182,14 @@ register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/48066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedf9b972b341064ff62a4443bfa83f69c8c60108 Gerrit-Change-Number: 48066 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]src/arch/x86:Add support for low power idle table
by Michael Niewöhner (Code Review) 29 Nov '20

29 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: [WIP]src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 5: Any news? :-) If you need any help with this or in case you don't have the time to finalize it, I can take that if you wish. Just let me know -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sun, 29 Nov 2020 20:03:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/apple: Add Macmini6,1 support
by Evgeny Zinoviev (Code Review) 29 Nov '20

29 Nov '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48132 ) Change subject: mb/apple: Add Macmini6,1 support ...................................................................... mb/apple: Add Macmini6,1 support A1347 (EMC 2570) model. The board is 820-3227. Untested yet. Schematics is unavailable. Change-Id: Ia8d848acbedd93a051e72f0dba389cc6081565ad Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A src/mainboard/apple/macmini6_1/Kconfig A src/mainboard/apple/macmini6_1/Kconfig.name A src/mainboard/apple/macmini6_1/Makefile.inc A src/mainboard/apple/macmini6_1/acpi/ec.asl A src/mainboard/apple/macmini6_1/acpi/platform.asl A src/mainboard/apple/macmini6_1/acpi/superio.asl A src/mainboard/apple/macmini6_1/acpi_tables.c A src/mainboard/apple/macmini6_1/board_info.txt A src/mainboard/apple/macmini6_1/devicetree.cb A src/mainboard/apple/macmini6_1/dsdt.asl A src/mainboard/apple/macmini6_1/early_init.c A src/mainboard/apple/macmini6_1/gma-mainboard.ads A src/mainboard/apple/macmini6_1/gpio.c A src/mainboard/apple/macmini6_1/hda_verb.c A src/mainboard/apple/macmini6_1/mainboard.c 15 files changed, 508 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48132/1 diff --git a/src/mainboard/apple/macmini6_1/Kconfig b/src/mainboard/apple/macmini6_1/Kconfig new file mode 100644 index 0000000..4c6d620 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/Kconfig @@ -0,0 +1,40 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_APPLE_MACMINI6_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default apple/macmini6_1 + +config MAINBOARD_PART_NUMBER + string + default "Macmini6,1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/apple/macmini6_1/Kconfig.name b/src/mainboard/apple/macmini6_1/Kconfig.name new file mode 100644 index 0000000..1309768 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACMINI6_1 + bool "Macmini6,1" diff --git a/src/mainboard/apple/macmini6_1/Makefile.inc b/src/mainboard/apple/macmini6_1/Makefile.inc new file mode 100644 index 0000000..e09d538 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/apple/macmini6_1/acpi/ec.asl b/src/mainboard/apple/macmini6_1/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/acpi/ec.asl diff --git a/src/mainboard/apple/macmini6_1/acpi/platform.asl b/src/mainboard/apple/macmini6_1/acpi/platform.asl new file mode 100644 index 0000000..77a0295 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Method(_WAK, 1) +{ + Return (Package() { 0, 0 }) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/apple/macmini6_1/acpi/superio.asl b/src/mainboard/apple/macmini6_1/acpi/superio.asl new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/acpi/superio.asl @@ -0,0 +1 @@ + diff --git a/src/mainboard/apple/macmini6_1/acpi_tables.c b/src/mainboard/apple/macmini6_1/acpi_tables.c new file mode 100644 index 0000000..14a79f8 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/acpi_tables.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ +} diff --git a/src/mainboard/apple/macmini6_1/board_info.txt b/src/mainboard/apple/macmini6_1/board_info.txt new file mode 100644 index 0000000..c69a309 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: n +Release year: 2012 diff --git a/src/mainboard/apple/macmini6_1/devicetree.cb b/src/mainboard/apple/macmini6_1/devicetree.cb new file mode 100644 index 0000000..b3f6393 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/devicetree.cb @@ -0,0 +1,86 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + register "gpu_cpu_backlight" = "0x0000021c" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x021c021c" + + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x8086 0x7270 inherit + + device pci 00.0 on # Host bridge + subsystemid 0x106b 0x00ff + end + + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00ff + end + + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00ff + end + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge PCI-LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/apple/macmini6_1/dsdt.asl b/src/mainboard/apple/macmini6_1/dsdt.asl new file mode 100644 index 0000000..d29fb40 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macmini6_1/early_init.c b/src/mainboard/apple/macmini6_1/early_init.c new file mode 100644 index 0000000..8b31a88 --- /dev/null +++ b/src/mainboard/apple/macmini6_1/early_init.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <device/pci_ops.h> + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); +} + +/* TODO: Fix */ +const struct southbridge_usb_port mainboard_usb_ports[] = { + {1, 0, 0}, + {1, 0, 1}, + {1, 0, 2}, + {1, 0, 3}, + {1, 0, -1}, + {1, 0, -1}, + {1, 0, -1}, + {1, 0, -1}, + {1, 0, -1}, + {1, 0, -1}, + {1, 0, -1}, + {1, 0, -1}, + {1, 0, -1}, + {1, 0, -1}, +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); +} diff --git a/src/mainboard/apple/macmini6_1/gma-mainboard.ads b/src/mainboard/apple/macmini6_1/gma-mainboard.ads new file mode 100644 index 0000000..204f6fb --- /dev/null +++ b/src/mainboard/apple/macmini6_1/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; + diff --git a/src/mainboard/apple/macmini6_1/gpio.c b/src/mainboard/apple/macmini6_1/gpio.c new file mode 100644 index 0000000..f3dadef --- /dev/null +++ b/src/mainboard/apple/macmini6_1/gpio.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macmini6_1/hda_verb.c b/src/mainboard/apple/macmini6_1/hda_verb.c new file mode 100644 index 0000000..de0822f --- /dev/null +++ b/src/mainboard/apple/macmini6_1/hda_verb.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b5800, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x106b5800), + AZALIA_PIN_CFG(0, 0x09, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0a, 0x002b4040), + AZALIA_PIN_CFG(0, 0x0b, 0x90100130), + AZALIA_PIN_CFG(0, 0x0c, 0x008b3010), + AZALIA_PIN_CFG(0, 0x0d, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0e, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x00cbe020), + AZALIA_PIN_CFG(0, 0x10, 0x004be050), + AZALIA_PIN_CFG(0, 0x12, 0x400000f0), + AZALIA_PIN_CFG(0, 0x15, 0x400000f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560010), + AZALIA_PIN_CFG(3, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macmini6_1/mainboard.c b/src/mainboard/apple/macmini6_1/mainboard.c new file mode 100644 index 0000000..877483f --- /dev/null +++ b/src/mainboard/apple/macmini6_1/mainboard.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/48132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8d848acbedd93a051e72f0dba389cc6081565ad Gerrit-Change-Number: 48132 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel: Configure P2SB before other PCH controllers
by Furquan Shaikh (Code Review) 29 Nov '20

29 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47885 ) Change subject: soc/intel: Configure P2SB before other PCH controllers ...................................................................... soc/intel: Configure P2SB before other PCH controllers This change updates bootblock_pch_early_init() to perform P2SB configuration before any other PCH controllers are initialized. This is done because the other controllers might perform PCR settings which requires the PCR base address to be configured. As the PCR base address configuration happens during P2SB initialization, this change moves the p2sb init calls before any other PCH controller initialization. BUG=b:171534504 Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/elkhartlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 7 files changed, 48 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/47885/1 diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index b7d2c15..bc921e3 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -65,11 +65,16 @@ void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 242aa71..8ebfb3d 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -77,11 +77,16 @@ void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index 9224c48..e1b7d85 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -62,11 +62,16 @@ void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index f36bd31..a6b6b20 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -58,11 +58,16 @@ void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index f59d9c9..96a7dc2 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -62,11 +62,16 @@ void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c6b2ad9..38ae916 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -29,9 +29,14 @@ void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + + fast_spi_early_init(SPI_BASE_ADDRESS); } static void soc_config_acpibase(void) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 18ca5e5..5c4d1d5 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -67,11 +67,16 @@ void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. -- To view, visit https://review.coreboot.org/c/coreboot/+/47885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3 Gerrit-Change-Number: 47885 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/intel/adlrvp: Add support for LPDDR5
by Subrata Banik (Code Review) 29 Nov '20

29 Nov '20

Subrata Banik has uploaded a new patch set (#15) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46899 ) Change subject: mb/intel/adlrvp: Add support for LPDDR5 ...................................................................... mb/intel/adlrvp: Add support for LPDDR5 This patch adds LPDDR5 memory configuration parameters to FSP. TEST=Able to pass FSP-M MRC training on LPDDR5 RVP. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 --- M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex 5 files changed, 71 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/46899/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/46899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Gerrit-Change-Number: 46899 Gerrit-PatchSet: 15 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/intel/adlrvp: Add support for LPDDR5
by Subrata Banik (Code Review) 29 Nov '20

29 Nov '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46899 ) Change subject: mb/intel/adlrvp: Add support for LPDDR5 ...................................................................... Patch Set 14: (2 comments) https://review.coreboot.org/c/coreboot/+/46899/14/src/mainboard/intel/adlrv… File src/mainboard/intel/adlrvp/memory.c: https://review.coreboot.org/c/coreboot/+/46899/14/src/mainboard/intel/adlrv… PS14, Line 58: } > minor nit: add a comma for consistency? Ack https://review.coreboot.org/c/coreboot/+/46899/14/src/mainboard/intel/adlrv… PS14, Line 51: { 3, 2, 1, 0, 5, 4, 6, 7, 15, 14, 12, 13, 8, 9, 10, 11 }, : { 0, 2, 3, 1, 5, 7, 4, 6, 14, 13, 15, 12, 8, 9, 11, 10 }, : { 1, 2, 0, 3, 4, 6, 5, 7, 15, 13, 12, 14, 9, 10, 8, 11 }, : { 2, 1, 3, 0, 7, 4, 5, 6, 13, 12, 15, 14, 9, 11, 8, 10 }, : { 1, 2, 3, 0, 6, 4, 5, 7, 15, 13, 14, 12, 10, 9, 8, 11 }, : { 1, 0, 3, 2, 6, 7, 4, 5, 14, 12, 15, 13, 8, 9, 10, 11 }, : { 0, 2, 1, 3, 4, 7, 5, 6, 12, 13, 15, 14, 9, 11, 10, 8 }, : { 3, 2, 1, 0, 5, 4, 6, 7, 13, 15, 11, 12, 10, 9, 14, 8 } > I'd format this as follows: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/46899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Gerrit-Change-Number: 46899 Gerrit-PatchSet: 14 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 29 Nov 2020 14:44:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add lp5_ccc_config to the board memory configura...
by Subrata Banik (Code Review) 29 Nov '20

29 Nov '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47436 ) Change subject: soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration ...................................................................... soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47436 Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified V Sowmya: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 5fed568..36d0750 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -90,6 +90,14 @@ /* Board type */ uint8_t UserBd; + + /* + * Command pins mapping for Controller Channel (ccc) + * lp5_ccc_config: Bitmask where bits [3:0] are Controller 0 Channel [3:0] and + * bits [7:4] are Controller 1 Channel [3:0] + * Bit value: 0 = ccc pin mapping is ascending, 1 = ccc pin mapping is descending. + */ + uint8_t lp5_ccc_config; }; /* diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index f5f747d..8473ad8 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -178,6 +178,7 @@ meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); } + mem_cfg->Lp5CccConfig = board_cfg->lp5_ccc_config; mem_cfg->ECT = board_cfg->ect; mem_cfg->UserBd = board_cfg->UserBd; mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; -- To view, visit https://review.coreboot.org/c/coreboot/+/47436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Gerrit-Change-Number: 47436 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: set FADT PM profile to ENTERPRISE_S...
by Michael Niewöhner (Code Review) 29 Nov '20

29 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48088 ) Change subject: mb/supermicro/x11-lga1151-series: set FADT PM profile to ENTERPRISE_SERVER ...................................................................... mb/supermicro/x11-lga1151-series: set FADT PM profile to ENTERPRISE_SERVER Set the FADT PM profile to ENTERPRISE_SERVER, since the currently supported X11 boards are server boards. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I8fb5c7c262fbd3f3c085d7c2e2ef3d6ff6ce73eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48088 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/Makefile.inc A src/mainboard/supermicro/x11-lga1151-series/fadt.c 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index 035dd28..a4ebe46 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -7,5 +7,6 @@ ramstage-y += mainboard.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/supermicro/x11-lga1151-series/fadt.c b/src/mainboard/supermicro/x11-lga1151-series/fadt.c new file mode 100644 index 0000000..6306e03 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/fadt.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <soc/acpi.h> + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fb5c7c262fbd3f3c085d7c2e2ef3d6ff6ce73eb Gerrit-Change-Number: 48088 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2020