coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: soc/amd/picasso: Override weak functions for ioapic_id.
by Jason Glenesk (Code Review) 30 Nov '20

30 Nov '20

Hello Jason Glenesk, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46327 to review the following change. Change subject: soc/amd/picasso: Override weak functions for ioapic_id. ...................................................................... soc/amd/picasso: Override weak functions for ioapic_id. Override soc_get_fch_ioapic_id() and soc_get_gnb_ioapic_id() for picasso. Return CONFIG_PICASSO_FCH_IOAPIC_ID and CONFIG_PICASSO_GNB_IOAPIC_ID. BUG=b:167421913 TEST=Boot morphius to shell. Confirm overrides return values by dumping MADT. BRANCH=Zork Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Change-Id: I7f0403678d7b221e7f6e76c72b701a095f233c97 --- M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/cpu.c 3 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46327/1 diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index c5c1ed8..d10167e 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio_map.h> +#include <amdblocks/cpu.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -16,7 +17,7 @@ static void sm_init(struct device *dev) { - setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); + setup_ioapic(VIO_APIC_VADDR, soc_get_fch_ioapic_id()); } static u32 get_sm_mmio(struct device *dev) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 17940e9..645968f 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -19,6 +19,7 @@ #include <device/pci.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> +#include <amdblocks/cpu.h> #include <soc/acpi.h> #include <soc/pci_devs.h> #include <soc/cpu.h> @@ -52,10 +53,10 @@ current = acpi_create_madt_lapics(current); current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - CONFIG_PICASSO_FCH_IOAPIC_ID, IO_APIC_ADDR, 0); + soc_get_fch_ioapic_id(), IO_APIC_ADDR, 0); current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - CONFIG_PICASSO_GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); + soc_get_gnb_ioapic_id(), GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 4d6e98d..5e01e9e 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/cpu.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> @@ -139,3 +140,13 @@ .ops = &cpu_dev_ops, .id_table = cpu_table, }; + +uint8_t soc_get_fch_ioapic_id(void) +{ + return CONFIG_PICASSO_FCH_IOAPIC_ID; +} + +uint8_t soc_get_gnb_ioapic_id(void) +{ + return CONFIG_PICASSO_GNB_IOAPIC_ID; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0403678d7b221e7f6e76c72b701a095f233c97 Gerrit-Change-Number: 46327 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: soc/amd/picasso: remove unused AMDFW_OUTSIDE_CBFS Kconfig option
by Felix Held (Code Review) 30 Nov '20

30 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47890 ) Change subject: soc/amd/picasso: remove unused AMDFW_OUTSIDE_CBFS Kconfig option ...................................................................... soc/amd/picasso: remove unused AMDFW_OUTSIDE_CBFS Kconfig option The corresponding functionality in the SoC's Makefile.inc was removed in commit ef3395d990bbf1118a8d4e367a986bdbc92b1820 Change-Id: Iba84d9deb155ce314b3a3588781752b83a21486b Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/Kconfig 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47890/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6fa3664..c3995c8 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -406,14 +406,6 @@ menu "PSP Configuration Options" -config AMDFW_OUTSIDE_CBFS - bool - default n - help - The AMDFW (PSP) is typically locatable in cbfs. Select this - option to manually attach the generated amdfw.rom outside of - cbfs. The location is selected by the FWM position. - config AMD_FWM_POSITION_INDEX int "Firmware Directory Table location (0 to 5)" range 0 5 -- To view, visit https://review.coreboot.org/c/coreboot/+/47890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba84d9deb155ce314b3a3588781752b83a21486b Gerrit-Change-Number: 47890 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/skylake: Add chipset devicetree
by Michael Niewöhner (Code Review) 30 Nov '20

30 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46314 ) Change subject: soc/intel/skylake: Add chipset devicetree ...................................................................... Patch Set 7: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/46314/6/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chipset.cb: https://review.coreboot.org/c/coreboot/+/46314/6/src/soc/intel/skylake/chip… PS6, Line 10: device pci 07.0 alias chap off end # CHAP https://review.coreboot.org/c/coreboot/+/46314/6/src/soc/intel/skylake/chip… PS6, Line 61: pch_spi maybe fast_spi like in TGL? -- To view, visit https://review.coreboot.org/c/coreboot/+/46314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Gerrit-Change-Number: 46314 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 30 Nov 2020 20:23:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Add chipset devicetree
by Felix Singer (Code Review) 30 Nov '20

30 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46314 to look at the new patch set (#7). Change subject: soc/intel/skylake: Add chipset devicetree ...................................................................... soc/intel/skylake: Add chipset devicetree Set most of the devices to off to keep current behaviour. Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/Kconfig A src/soc/intel/skylake/chipset.cb 2 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/46314/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/46314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Gerrit-Change-Number: 46314 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Add chipset devicetree
by Felix Singer (Code Review) 30 Nov '20

30 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46314 to look at the new patch set (#6). Change subject: soc/intel/skylake: Add chipset devicetree ...................................................................... soc/intel/skylake: Add chipset devicetree Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/Kconfig A src/soc/intel/skylake/chipset.cb 2 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/46314/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/46314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Gerrit-Change-Number: 46314 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Add chipset devicetree
by Felix Singer (Code Review) 30 Nov '20

30 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46314 ) Change subject: soc/intel/skylake: Add chipset devicetree ...................................................................... Patch Set 5: (5 comments) This change is ready for review. https://review.coreboot.org/c/coreboot/+/46314/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chipset.cb: https://review.coreboot.org/c/coreboot/+/46314/2/src/soc/intel/skylake/chip… PS2, Line 8: device pci 04.0 alias sa_thermal off end # SA thermal subsystem > should be enabled by default (linux reads the tcc value from that device) defaults can be discussed in another patch. https://review.coreboot.org/c/coreboot/+/46314/2/src/soc/intel/skylake/chip… PS2, Line 14: device pci 14.2 alias thermal off end # Thermal Subsystem > should be enabled by default Done https://review.coreboot.org/c/coreboot/+/46314/2/src/soc/intel/skylake/chip… PS2, Line 20: heci1 > hmm, iirc this needs to be on so cb can initialize me. […] Done https://review.coreboot.org/c/coreboot/+/46314/2/src/soc/intel/skylake/chip… PS2, Line 60: pch_espi > lpc_espi maybe? Done https://review.coreboot.org/c/coreboot/+/46314/2/src/soc/intel/skylake/chip… PS2, Line 65: on > could be "hidden" by default Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Gerrit-Change-Number: 46314 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 30 Nov 2020 19:46:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lenovo/g505s: properly program the IRQ tables
by Mike Banon (Code Review) 30 Nov '20

30 Nov '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47852 ) Change subject: lenovo/g505s: properly program the IRQ tables ...................................................................... lenovo/g505s: properly program the IRQ tables IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for Lenovo G505S: all the fam15h boards have these "bad IRQs". OS like Linux still finds a way, but Kolibri can't see the IRQ table. With this change applied: * G505S boots fine to Linux - no angry IRQ-related messages at dmesg; * KolibriOS sees 18 IRQs in a table and could successfully attach a driver to Atheros QCA8172 onboard Ethernet controller with an IRQ 3. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I3a3ca74ac0ae93606dab5d5333cb7a9d12a6b32f --- M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/g505s/acpi/routing.asl M src/mainboard/lenovo/g505s/devicetree.cb M src/mainboard/lenovo/g505s/irq_tables.c M src/mainboard/lenovo/g505s/mainboard.c M src/mainboard/lenovo/g505s/mptable.c A src/mainboard/lenovo/g505s/mptable.h 7 files changed, 339 insertions(+), 393 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/47852/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 322d3a7..75ae32c 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -11,6 +11,7 @@ select DEFAULT_POST_ON_LPC select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER @@ -47,4 +48,8 @@ string default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS +config IRQ_SLOT_COUNT + int + default 14 + endif # BOARD_LENOVO_G505S diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl index bf6a881..2c183a6 100644 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ b/src/mainboard/lenovo/g505s/acpi/routing.asl @@ -4,308 +4,170 @@ Name(PR0, Package(){ /* NB devices */ /* Bus 0, Dev 0 - F15 Host Controller */ + /* IOMMU: 0:02.00 - IRQ 3 */ Package(){0x0000FFFF, 0, INTA, 0 }, Package(){0x0000FFFF, 1, INTB, 0 }, Package(){0x0000FFFF, 2, INTC, 0 }, Package(){0x0000FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics (IGP) */ + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + Package(){0x0001FFFF, 0, INTA, 0 }, + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + Package(){0x0001FFFF, 1, INTB, 0 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + Package(){0x0002FFFF, 0, INTA, 0 }, + Package(){0x0002FFFF, 1, INTB, 0 }, + Package(){0x0002FFFF, 2, INTC, 0 }, + Package(){0x0002FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for x1 PCIe Slot */ + /* PCIe GPP to Eth 2:00.00: 0:04.00 - IRQ 3 */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, Package(){0x0004FFFF, 2, INTC, 0 }, Package(){0x0004FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 5 - PCIe Bridge for x1 PCIe Slot */ + /* PCIe GPP to WiFi 3:00.00: 0:05.00 - IRQ 4 */ Package(){0x0005FFFF, 0, INTB, 0 }, Package(){0x0005FFFF, 1, INTC, 0 }, Package(){0x0005FFFF, 2, INTD, 0 }, Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - + /* SB devices */ + /* USB XHCI: 0:10.00 - IRQ 5 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + /* SATA: 0:11.00 - IRQ 7 */ + Package(){0x0011FFFF, 0, INTD, 0 }, + /* USB OHCI1: 0:12.00 - IRQ 5 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + /* USB EHCI1: 0:12.02 - IRQ 4 */ + Package(){0x0012FFFF, 1, INTB, 0 }, + /* USB OHCI2: 0:13.00 - IRQ 5 */ + Package(){0x0013FFFF, 0, INTC, 0 }, + /* USB EHCI2: 0:13.02 - IRQ 4 */ + Package(){0x0013FFFF, 1, INTB, 0 }, + /* USB OHCI3: 0:16.00 - IRQ 5 */ + Package(){0x0016FFFF, 0, INTC, 0 }, + /* USB EHCI3: 0:16.02 - IRQ 4 */ + Package(){0x0016FFFF, 1, INTB, 0 }, /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 1, INTB, 0 }, + /* USB OHCI4: 0:14.05 - IRQ 5 */ Package(){0x0014FFFF, 2, INTC, 0 }, Package(){0x0014FFFF, 3, INTD, 0 }, - - /* SB devices */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 PCIe Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, }) Name(APR0, Package(){ /* NB devices in APIC mode */ /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 17 }, - Package(){0x0001FFFF, 1, 0, 18 }, + /* IOMMU: 0:02.00 - IRQ 3 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics (IGP) */ + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + Package(){0x0001FFFF, 0, 0, 16 }, + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + Package(){0x0001FFFF, 1, 0, 17 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + Package(){0x0002FFFF, 0, 0, 16 }, + Package(){0x0002FFFF, 1, 0, 17 }, + Package(){0x0002FFFF, 2, 0, 18 }, + Package(){0x0002FFFF, 3, 0, 19 }, + /* Bus 0, Dev 4 - PCIe Bridge for x1 PCIe Slot */ + /* PCIe GPP to Eth 2:00.00: 0:04.00 - IRQ 3 */ Package(){0x0004FFFF, 0, 0, 16 }, Package(){0x0004FFFF, 1, 0, 17 }, Package(){0x0004FFFF, 2, 0, 18 }, Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 5 - PCIe Bridge for x1 PCIe Slot */ + /* PCIe GPP to WiFi 3:00.00: 0:05.00 - IRQ 4 */ Package(){0x0005FFFF, 0, 0, 17 }, Package(){0x0005FFFF, 1, 0, 18 }, Package(){0x0005FFFF, 2, 0, 19 }, Package(){0x0005FFFF, 3, 0, 16 }, - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - + /* SB devices in APIC mode */ + /* USB XHCI: 0:10.00 - IRQ 5 */ + Package(){0x0010FFFF, 0, 0, 18 }, + /* SATA: 0:11.00 - IRQ 7 */ + Package(){0x0011FFFF, 0, 0, 19 }, + /* USB OHCI1: 0:12.00 - IRQ 5 */ + Package(){0x0012FFFF, 0, 0, 18 }, + /* USB EHCI1: 0:12.02 - IRQ 4 */ + Package(){0x0012FFFF, 1, 0, 17 }, + /* USB OHCI2: 0:13.00 - IRQ 5 */ + Package(){0x0013FFFF, 0, 0, 18 }, + /* USB EHCI2: 0:13.02 - IRQ 4 */ + Package(){0x0013FFFF, 1, 0, 17 }, + /* USB OHCI3: 0:16.00 - IRQ 5 */ + Package(){0x0016FFFF, 0, 0, 18 }, + /* USB EHCI3: 0:16.02 - IRQ 4 */ + Package(){0x0016FFFF, 1, 0, 17 }, /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, + /* USB OHCI4: 0:14.05 - IRQ 5 */ Package(){0x0014FFFF, 2, 0, 18 }, Package(){0x0014FFFF, 3, 0, 19 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, }) Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, }) Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, }) - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ + /* Onboard Ethernet (Eth) 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ Package(){0x0000FFFF, 0, INTA, 0 }, Package(){0x0000FFFF, 1, INTB, 0 }, Package(){0x0000FFFF, 2, INTC, 0 }, Package(){0x0000FFFF, 3, INTD, 0 }, }) Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ + /* Onboard Ethernet (Eth) 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ Package(){0x0000FFFF, 0, 0, 16 }, Package(){0x0000FFFF, 1, 0, 17 }, Package(){0x0000FFFF, 2, 0, 18 }, Package(){0x0000FFFF, 3, 0, 19 }, }) - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ + /* PCIe x1 slot for WiFi 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ Package(){0x0000FFFF, 0, INTB, 0 }, Package(){0x0000FFFF, 1, INTC, 0 }, Package(){0x0000FFFF, 2, INTD, 0 }, Package(){0x0000FFFF, 3, INTA, 0 }, }) Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ + /* PCIe x1 slot for WiFi 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ Package(){0x0000FFFF, 0, 0, 17 }, Package(){0x0000FFFF, 1, 0, 18 }, Package(){0x0000FFFF, 2, 0, 19 }, Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, }) Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, }) - Name(PS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, }) Name(APS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - /* SB PCI Bridge J21, J22 */ Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, }) diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 4b4df36..97254a5 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -41,7 +41,7 @@ end end device pci 14.4 on end # FCH PCI Bridge [1022:780f] - device pci 14.5 off end # USB 2 + device pci 14.5 on end # USB 2 device pci 14.6 off end # Gec device pci 14.7 off end # SD device pci 15.0 off end # PCIe 0 diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c index 0baf079..3898a72 100644 --- a/src/mainboard/lenovo/g505s/irq_tables.c +++ b/src/mainboard/lenovo/g505s/irq_tables.c @@ -1,88 +1,61 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> -#include <console/console.h> -#include <device/pci_def.h> -#include <string.h> -#include <stdint.h> -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x14 << 3) | 0x4, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x780b, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x87, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* IOMMU: 0:02.00 - IRQ 3 */ + {0x00, (0x00 << 3) | 0x2, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0}, + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + {0x00, (0x02 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0}, + /* PCIe GPP to Eth 2:00.00: 0:04.00 - IRQ 3 */ + {0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0}, + /* PCIe GPP to WiFi 3:00.00: 0:05.00 - IRQ 3 */ + {0x00, (0x05 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0}, + /* USB XHCI: 0:10.00 - IRQ 5 */ + {0x00, (0x10 << 3) | 0x0, {{0x03, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* SATA: 0:11.00 - IRQ 7 */ + {0x00, (0x11 << 3) | 0x0, {{0x04, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI1: 0:12.00 - IRQ 5 */ + /* USB EHCI1: 0:12.02 - IRQ 4 */ + {0x00, (0x12 << 3) | 0x0, {{0x03, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI2: 0:13.00 - IRQ 5 */ + /* USB EHCI2: 0:13.02 - IRQ 4 */ + {0x00, (0x16 << 3) | 0x0, {{0x03, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI3: 0:16.00 - IRQ 5 */ + /* USB EHCI3: 0:16.02 - IRQ 4 */ + {0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + /* USB OHCI4: 0:14.05 - IRQ 5 */ + {0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0}, + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + {0x01, (0x00 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x1, 0x0}, + /* Onboard Ethernet (Eth) 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ + {0x02, (0x00 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x2, 0x0}, + /* PCIe x1 slot for WiFi 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ + {0x03, (0x00 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90} }, 0x3, 0x0} + } +}; unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index d900c94..83e1f92 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -7,8 +7,56 @@ #include <cpu/x86/smm.h> #include <device/device.h> +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <northbridge/amd/agesa/family15tn/pci_devs.h> #include <southbridge/amd/agesa/hudson/smi.h> +#include "mptable.h" + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ picr_data[PIRQ_A] if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D} }, */ + {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:02.00 - IRQ 3 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to Eth 2:00.00: 0:04.00 - IRQ 3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to WiFi 3:00.00: 0:05.00 - IRQ 4 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} } /* USB OHCI4: 0:14.05 - IRQ 5 */ +}; + +const u8 *picr_data = mainboard_picr_data; +const u8 *intr_data = mainboard_intr_data; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + static void pavilion_cold_boot_init(void) { /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */ @@ -21,6 +69,9 @@ { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); + hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); global_smi_enable(); diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index bc1759a..1c20d9b 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -5,24 +5,11 @@ #include <arch/smp/mpspec.h> #include <stdint.h> #include <string.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <drivers/generic/ioapic/chip.h> -u8 picr_data[0x54] = { - 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; +#include "mptable.h" static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { @@ -56,114 +43,133 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + // mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA "); - /* I/O APICs: APIC ID Version State Address */ + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + for (byte = 0x0; byte < sizeof(picr_data_ptr); byte++) { outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); + outb(mainboard_picr_data[byte], 0xC01); } /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + for (byte = 0x0; byte < sizeof(intr_data_ptr); byte++) { outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); + outb(mainboard_intr_data[byte], 0xC01); } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - /* IOMMU */ - PCI_INT(0x0, 0x00, 0x0, 0x10); - PCI_INT(0x0, 0x00, 0x1, 0x11); - PCI_INT(0x0, 0x00, 0x2, 0x12); - PCI_INT(0x0, 0x00, 0x3, 0x13); + /* IOMMU: 0:02.00 - IRQ 3 */ + PCI_INT(0x0, 0x00, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x00, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x00, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x00, 0x3, intr_data_ptr[PIRQ_D]); - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]); + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]); - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to Eth 2:00.00: 0:04.00 - IRQ 3 */ + PCI_INT(0x0, 0x04, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x04, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x04, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x04, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to WiFi 3:00.00: 0:05.00 - IRQ 4 */ + PCI_INT(0x0, 0x05, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x05, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x05, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x0, 0x05, 0x3, intr_data_ptr[PIRQ_A]); - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + /* USB XHCI: 0:10.00 - IRQ 5 */ + PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); + /* SATA: 0:11.00 - IRQ 7 */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + /* USB OHCI1: 0:12.00 - IRQ 5 */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + /* USB EHCI1: 0:12.02 - IRQ 4 */ + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + /* USB OHCI2: 0:13.00 - IRQ 5 */ + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + /* USB EHCI2: 0:13.02 - IRQ 4 */ + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + /* USB OHCI3: 0:16.00 - IRQ 5 */ + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + /* USB EHCI3: 0:16.02 - IRQ 4 */ + PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + /* USB OHCI4: 0:14.05 - IRQ 5 */ + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_C]); - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]); - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + /* Onboard Ethernet (Eth) 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x2, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x2, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x2, 0x0, 0x3, intr_data_ptr[PIRQ_D]); - /* on board NIC & Slot PCIE. */ + /* PCIe x1 slot for WiFi 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ + PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x3, 0x0, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x3, 0x0, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x3, 0x0, 0x3, intr_data_ptr[PIRQ_A]); - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ diff --git a/src/mainboard/lenovo/g505s/mptable.h b/src/mainboard/lenovo/g505s/mptable.h new file mode 100644 index 0000000..8e27e97 --- /dev/null +++ b/src/mainboard/lenovo/g505s/mptable.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Based on 51205_Bolton_FCH_BIOS_Dev_Guide.pdf. Acronyms: + * + * SCI - System Controller Interrupt, + * SMBUS - System Management Bus, + * ASF - Advanced Synchronization Facility, + * HDA - HD Audio, + * SD - SD Flash Controller, + * GEC - Gigabit Ethernet Controller, + * PerMon - Performance Monitor, + * IMC - Integrated Memory Controller, + * GPP - PCIe General Purpose Ports. + */ + +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0xAA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x05, 0x04, 0x05, + /* IDE, SATA */ + [0x40] = 0x1F, 0x07, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x1F, 0x1F, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, + /* IDE, SATA */ + [0x40] = 0x1F, 0x13, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/47852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a3ca74ac0ae93606dab5d5333cb7a9d12a6b32f Gerrit-Change-Number: 47852 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: soc/amd/picasso: remove PICASSO_LPC_IOMUX Kconfig option from SoC
by Felix Held (Code Review) 30 Nov '20

30 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47891 ) Change subject: soc/amd/picasso: remove PICASSO_LPC_IOMUX Kconfig option from SoC ...................................................................... soc/amd/picasso: remove PICASSO_LPC_IOMUX Kconfig option from SoC PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in the corresponding SoC code, so remove it from the SoC's Kconfig and reanme it in the mainboard's Kconfig to MANDOLIN_LPC. Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/Makefile.inc M src/mainboard/amd/mandolin/mainboard.c M src/soc/amd/picasso/Kconfig 4 files changed, 5 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/47891/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index dde7ac8..0cc75f4 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -21,7 +21,7 @@ config AMD_LPC_DEBUG_CARD bool "Enable LPC-Serial debug card on the debug header" default n - select PICASSO_LPC_IOMUX + select MANDOLIN_LPC select SUPERIO_SMSC_SIO1036 help AMD's debug card contains an SMSC SIO1036 device which provides an @@ -93,7 +93,7 @@ endchoice endif # !AMD_LPC_DEBUG_CARD -config PICASSO_LPC_IOMUX +config MANDOLIN_LPC bool default y if MANDOLIN_IOMUX_USE_LPC help diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 7787018..5ee5d44 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -5,10 +5,7 @@ ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/port_descriptors.c - -ifneq ($(CONFIG_PICASSO_LPC_IOMUX),y) -ramstage-y += emmc_gpio.c -endif +ramstage-$(CONFIG_MANDOLIN_LPC) += emmc_gpio.c ifeq ($(CONFIG_BOARD_AMD_MANDOLIN),y) APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_mandolin.bin diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index 247616c..b509282 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -111,13 +111,13 @@ { struct soc_amd_picasso_config *cfg = config_of_soc(); - if (!CONFIG(PICASSO_LPC_IOMUX)) + if (!CONFIG(MANDOLIN_LPC)) cfg->emmc_config.timing = SD_EMMC_EMMC_HS400; mainboard_program_gpios(); /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */ - if (CONFIG(PICASSO_LPC_IOMUX)) + if (CONFIG(MANDOLIN_LPC)) printk(BIOS_INFO, "eMMC not available due to LPC requirement\n"); else mainboard_program_emmc_gpios(); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index c3995c8..7bcc316 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -376,12 +376,6 @@ int default 150 -config PICASSO_LPC_IOMUX - bool - help - Picasso's LPC bus signals are MUXed with some of the EMMC signals. - Select this option if LPC signals are required. - config DISABLE_SPI_FLASH_ROM_SHARING def_bool n help -- To view, visit https://review.coreboot.org/c/coreboot/+/47891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8 Gerrit-Change-Number: 47891 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: arch/x86: Link NO_XIP_EARLY_STAGES like other stages
by Arthur Heymans (Code Review) 30 Nov '20

30 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36612 ) Change subject: arch/x86: Link NO_XIP_EARLY_STAGES like other stages ...................................................................... arch/x86: Link NO_XIP_EARLY_STAGES like other stages If stages are not run XIP they can be linked like other stages, which includes a (*.data) section. Change-Id: Ib165058abfb07e385461cdcca4aef31928ec7572 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/include/rules.h M src/lib/program.ld 4 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36612/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index c36dc1c..a838b6d 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -32,7 +32,8 @@ /* reset stack pointer to CAR stack */ mov $_car_stack_end, %esp - /* clear .bss section as it is not shared */ + /* clear .bss section as it is not shared if stages are run XIP*/ +#if !ENV_STAGE_HAS_DATA_SECTION cld xor %eax, %eax movl $(_ebss), %ecx @@ -40,6 +41,7 @@ sub %edi, %ecx shrl $2, %ecx rep stosl +#endif #if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP))) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 6ccbd8c..a68b635 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -69,6 +69,7 @@ * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ +#if !ENV_STAGE_HAS_DATA_SECTION . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; #if ENV_STAGE_HAS_BSS_SECTION @@ -84,6 +85,7 @@ #endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; +#endif _car_unallocated_start = .; #if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) diff --git a/src/include/rules.h b/src/include/rules.h index 0436198..fe162f8 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -274,7 +274,7 @@ /* Indicates memory layout is determined with arch/x86/car.ld. */ #define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM)) /* No .data sections with execute-in-place from ROM. */ -#define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM +#define ENV_STAGE_HAS_DATA_SECTION (!ENV_CACHE_AS_RAM || CONFIG(NO_XIP_EARLY_STAGES)) /* No .bss sections for stage with CAR teardown. */ #define ENV_STAGE_HAS_BSS_SECTION !(ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION)) #else diff --git a/src/lib/program.ld b/src/lib/program.ld index a9d4e48..d323ac1 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -125,7 +125,7 @@ } #endif -#if ENV_STAGE_HAS_BSS_SECTION && !ENV_CACHE_AS_RAM +#if ENV_STAGE_HAS_BSS_SECTION && ENV_STAGE_HAS_DATA_SECTION .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; -- To view, visit https://review.coreboot.org/c/coreboot/+/36612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib165058abfb07e385461cdcca4aef31928ec7572 Gerrit-Change-Number: 36612 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: soc/amd: move bootblock inside main SoC directories
by Felix Held (Code Review) 30 Nov '20

30 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47982 ) Change subject: soc/amd: move bootblock inside main SoC directories ...................................................................... soc/amd: move bootblock inside main SoC directories There's no need to have the bootblock in its own sub-directory, so move it to each SoC's main directory. Change-Id: I78a9ce1cd0d790250a66c82bb1d8aa6c3b4f7162 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/Makefile.inc R src/soc/amd/picasso/bootblock.c M src/soc/amd/stoneyridge/Makefile.inc R src/soc/amd/stoneyridge/bootblock.c 4 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47982/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f010c7b..b5e409b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -11,7 +11,7 @@ subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock.c bootblock-y += aoac.c bootblock-y += southbridge.c bootblock-y += i2c.c diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock.c similarity index 100% rename from src/soc/amd/picasso/bootblock/bootblock.c rename to src/soc/amd/picasso/bootblock.c diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 311ea68..8cdf6cc 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -12,7 +12,7 @@ bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c bootblock-y += BiosCallOuts.c -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += enable_usbdebug.c diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c similarity index 100% rename from src/soc/amd/stoneyridge/bootblock/bootblock.c rename to src/soc/amd/stoneyridge/bootblock.c -- To view, visit https://review.coreboot.org/c/coreboot/+/47982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78a9ce1cd0d790250a66c82bb1d8aa6c3b4f7162 Gerrit-Change-Number: 47982 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 7

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020