coreboot-gerrit October 2020

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Change in coreboot[master]: [TEST]mb/google/dedede: Enable dynamic emmc dll tuning.
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45599 to look at the new patch set (#8). Change subject: [TEST]mb/google/dedede: Enable dynamic emmc dll tuning. ...................................................................... [TEST]mb/google/dedede: Enable dynamic emmc dll tuning. BUG=b:140124451 TEST=Ran tuning on Waddledee and booted to OS via emmc. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I9d272eb860fb3025374e94891d6675c63e0edf42 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/45599/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/45599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d272eb860fb3025374e94891d6675c63e0edf42 Gerrit-Change-Number: 45599 Gerrit-PatchSet: 8 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Bora Guvendik has uploaded a new patch set (#13) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/38256 ) Change subject: [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure ...................................................................... [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure Provide support needed to save EMMC dll tuned data to SPI and registers boot after flash and in subsequent boots, read emmc data from SPI flash and copy to the registers. In case tuning fails, setting a flag in header to skip tuning next boot and use FSP default values. TEST: Tested if data is written to SPI EMMC_CACHE and if the readback data is valid. Also verified if the flag is setting right when tuning fails. Change-Id: I0ca1452cbdcbadd3fca644dcc2dfb7b721e02fb7 Signed-off-by: Thejaswani Putta <thejaswani.putta(a)intel.com> --- M src/mainboard/google/drallion/chromeos.fmd M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/Makefile.inc A src/soc/intel/common/block/scs/emmc_cache.c 4 files changed, 475 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38256/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/38256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca1452cbdcbadd3fca644dcc2dfb7b721e02fb7 Gerrit-Change-Number: 38256 Gerrit-PatchSet: 13 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block: Add eMMC DLL tuning
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44497 to look at the new patch set (#13). Change subject: soc/intel/common/block: Add eMMC DLL tuning ...................................................................... soc/intel/common/block: Add eMMC DLL tuning For 3 different operations (CMD, Tx Data, Rx Data) use mmc driver in coreboot to switch speed modes (DS, HS, DDR, HS200, HS400). 1) For each speed mode / operation combination, start writing delay values (each step 125pSec delay) from 0 to max for the corresponding register field. As an example, register "Tx Delay Control 1" 0x824h, bit field [8:14] is for HS400 speed and write operation (Tx Data). Max is 78 for this field. 2) After writing a delay value to the register field, try to send a CMD13 "send status" for CMD operation. For write (Tx Data), send CMD24 "Write Block". For read (Rx Data), send CMD17 "Read Single Block". 3) Mark that delay value as FAIL if there are crc errors, timeouts, bits set in Error Interrupt Status register or read/write failures. PASS if there are no errors. 4) Choose the middle of largest passing window and program register field with this optimal delay value. BUG=b:140124451 TEST=Ran tuning on Waddledee and booted to OS via eMMC. Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/dll_tuning.c 3 files changed, 383 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44497/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/44497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Gerrit-Change-Number: 44497 Gerrit-PatchSet: 13 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block: Add apis to read/write mmc dll register fields
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44496 to look at the new patch set (#4). Change subject: soc/intel/common/block: Add apis to read/write mmc dll register fields ...................................................................... soc/intel/common/block: Add apis to read/write mmc dll register fields Given a mode (Cmd/Tx/Rx) and speed(DS,HS,DDR,HS200,HS400), read and write the correct field of the following registers. Tx CMD Delay Control register (820h) Tx Delay Control 1 register (824h) Tx Delay Control 2 register (828h) Rx CMD Data Delay Control 1 register (82Ch) Rx Strobe Delay Control register (830h) Rx CMD Data Path Delay Control 2 register (834h) BUG=b:140124451 TEST=Run emmc dll tuning, verify register field updated. Change-Id: I068fdd92c77d83ebb13e54a7a4ec2524ebcffe1c Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/scs/dll_tuning.c 1 file changed, 146 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/44496/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/44496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I068fdd92c77d83ebb13e54a7a4ec2524ebcffe1c Gerrit-Change-Number: 44496 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block: Add function to choose best emmc DLL value
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Selma Bensaid, Bora Guvendik, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44495 to look at the new patch set (#4). Change subject: soc/intel/common/block: Add function to choose best emmc DLL value ...................................................................... soc/intel/common/block: Add function to choose best emmc DLL value Given an array of PASS and FAILs, choose and return the middle index of the largest continuous sequence of PASSes as the optimum value. ex: PASS FAIL PASS PASS <-- optimum PASS BUG=b:140124451 TEST=Run emmc dll tuning and check the value chosen. Change-Id: I5506400aeb7251f1f5b55a1b4cc32efe050b592d Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/Makefile.inc A src/soc/intel/common/block/scs/dll_tuning.c 3 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/44495/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/44495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5506400aeb7251f1f5b55a1b4cc32efe050b592d Gerrit-Change-Number: 44495 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: storage: Modify storage_block_fill_write to return error
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44494 to look at the new patch set (#4). Change subject: storage: Modify storage_block_fill_write to return error ...................................................................... storage: Modify storage_block_fill_write to return error Modify storage_block_fill_write api to return send_cmd error code from sdhci to upper levels. BUG=b:140124451 TEST=Boot to OS Change-Id: I6a3212b1f407e5b42dee47740f4a480b24c3207f Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/commonlib/include/commonlib/storage.h M src/commonlib/storage/storage.c M src/commonlib/storage/storage_erase.c M src/commonlib/storage/storage_write.c 4 files changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/44494/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/44494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a3212b1f407e5b42dee47740f4a480b24c3207f Gerrit-Change-Number: 44494 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/storage/mmc: Add DS and DDR50 speed modes
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44493 to look at the new patch set (#4). Change subject: commonlib/storage/mmc: Add DS and DDR50 speed modes ...................................................................... commonlib/storage/mmc: Add DS and DDR50 speed modes Add two new functions to switch speed to "High Speed DDR" and "Backwards Compatibility with legacy MMC card" mentioned in section 5.3.2 of JESD84_B51 spec. BUG=b:140124451 TEST=Change mmc speed to DDR50 and DS Change-Id: Ic75a3815a47e99e054d2cea2e82757740caffd1a Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/commonlib/include/commonlib/storage.h M src/commonlib/storage/mmc.c 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/44493/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/44493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75a3815a47e99e054d2cea2e82757740caffd1a Gerrit-Change-Number: 44493 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add new mmc APIs
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Angel Pons, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44492 to look at the new patch set (#4). Change subject: soc/intel/common: Add new mmc APIs ...................................................................... soc/intel/common: Add new mmc APIs Add APIs to read single eMMC DLL register and to read/write all registers at once. BUG=b:140124451 TEST=Read / write eMMC DLL registers. Change-Id: Ie70f14d95f81d30360f5a68fbb34b50425e98ece Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/scs/mmc.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/44492/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/44492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70f14d95f81d30360f5a68fbb34b50425e98ece Gerrit-Change-Number: 44492 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block: Add eMMC DLL tuning
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44497 to look at the new patch set (#12). Change subject: soc/intel/common/block: Add eMMC DLL tuning ...................................................................... soc/intel/common/block: Add eMMC DLL tuning For 3 different operations (CMD, Tx Data, Rx Data) use mmc driver in coreboot to switch speed modes (DS, HS, DDR, HS200, HS400). 1) For each speed mode / operation combination, start writing delay values (each step 125pSec delay) from 0 to max for the corresponding register field. As an example, register "Tx Delay Control 1" 0x824h, bit field [8:14] is for HS400 speed and write operation (Tx Data). Max is 78 for this field. 2) After writing a delay value to the register field, try to send a CMD13 "send status" for CMD operation. For write (Tx Data), send CMD24 "Write Block". For read (Rx Data), send CMD17 "Read Single Block". 3) Mark that delay value as FAIL if there are crc errors, timeouts, bits set in Error Interrupt Status register or read/write failures. PASS if there are no errors. 4) Choose the middle of largest passing window and program register field with this optimal delay value. BUG=b:140124451 TEST=Ran tuning on Waddledee and booted to OS via eMMC. Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/dll_tuning.c 3 files changed, 383 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44497/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/44497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Gerrit-Change-Number: 44497 Gerrit-PatchSet: 12 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/storage/mmc: Add DS and DDR50 speed modes
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44493 to look at the new patch set (#3). Change subject: commonlib/storage/mmc: Add DS and DDR50 speed modes ...................................................................... commonlib/storage/mmc: Add DS and DDR50 speed modes Add two new functions to switch speed to "High Speed DDR" and "Backwards Compatibility with legacy MMC card" mentioned in section 5.3.2 of JESD84_B51 spec. BUG=b:140124451 TEST=Change mmc speed to DDR50 and DS Change-Id: Ic75a3815a47e99e054d2cea2e82757740caffd1a Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/commonlib/include/commonlib/storage.h M src/commonlib/storage/mmc.c 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/44493/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/44493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75a3815a47e99e054d2cea2e82757740caffd1a Gerrit-Change-Number: 44493 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020