coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/*: conversion from constant to Kconfig for XTAL frequency
by Paul Menzel (Code Review) 06 Oct '20

06 Oct '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46018 ) Change subject: soc/intel/*: conversion from constant to Kconfig for XTAL frequency ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/46018/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46018/8//COMMIT_MSG@7 PS8, Line 7: soc/intel/*: conversion from constant to Kconfig for XTAL frequency Please add a verb (in imperative mood) to make it a statement: > Convert XTAL frequency constant to Kconfig option https://review.coreboot.org/c/coreboot/+/46018/8//COMMIT_MSG@9 PS8, Line 9: This converts the constant for the XTAL frequency to a Kconfig option. [Motivation missing] > … because device configuration goes either in Kconfig or devicetree. (Or should device be able to override it?) -- To view, visit https://review.coreboot.org/c/coreboot/+/46018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Gerrit-Change-Number: 46018 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Oct 2020 08:31:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: test
by Morgan Jang (Code Review) 06 Oct '20

06 Oct '20

Morgan Jang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46067 ) Change subject: test ...................................................................... Abandoned test commit -- To view, visit https://review.coreboot.org/c/coreboot/+/46067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id209326b4e79090650987a44bb6a5cffe5b6e07c Gerrit-Change-Number: 46067 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/soc/intel/common/block: add Kconfig for PM Timer emulation support
by Paul Menzel (Code Review) 06 Oct '20

06 Oct '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46017 ) Change subject: src/soc/intel/common/block: add Kconfig for PM Timer emulation support ...................................................................... Patch Set 6: Code-Review+1 (1 comment) I guess this can’t be autodected at runtime. https://review.coreboot.org/c/coreboot/+/46017/6/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/46017/6/src/soc/intel/common/block… PS6, Line 106: ucode Spell out microcode? -- To view, visit https://review.coreboot.org/c/coreboot/+/46017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Gerrit-Change-Number: 46017 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Oct 2020 08:28:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17
by Johnny Lin (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Marc Jones, John Looney, Jonathan Zhang, Jingle Hsu, Angel Pons, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45799 to look at the new patch set (#9). Change subject: mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17 ...................................................................... mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17 Override smbios_fill_dimm_locator for type 17 Locator and Bank Locator. Also remove CONFIG(GENERATE_SMBIOS_TABLES) compile option because SMBIOS is always enabled and it makes the code cleaner. One sample type 17 table displayed as below: Handle 0x0010, DMI type 17, 40 bytes Memory Device ... Locator: DIMM F0 Bank Locator: _Node0_Channel5_Dimm0 Tested=On OCP Delta Lake, the Locator and Bank Locator strings are expected. Change-Id: I84531f9ee8bc76d9529aa983bc13e64f40c93138 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 11 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/45799/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/45799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84531f9ee8bc76d9529aa983bc13e64f40c93138 Gerrit-Change-Number: 45799 Gerrit-PatchSet: 9 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Johnny Lin (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Marc Jones, Patrick Georgi, Martin Roth, John Looney, Patrick Rudolph, Jonathan Zhang, Jingle Hsu, Angel Pons, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45798 to look at the new patch set (#8). Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 For now only implement for one socket and some of the fields are hard-coded for DDR4 including memory device type, data width and ECC support. Change-Id: I3cb72d18027d972140828970206834ff55b72022 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/ddr.c A src/soc/intel/xeon_sp/cpx/include/soc/ddr.h M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/include/soc/romstage.h M src/soc/intel/xeon_sp/romstage.c 6 files changed, 228 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45798/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 8 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields
by Johnny Lin (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Rudolph, Jonathan Zhang, Jingle Hsu, Angel Pons, Morgan Jang, Patrick Rudolph, Nathaniel L Desimone, Isaac W Oram, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45797 to look at the new patch set (#6). Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields ...................................................................... vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields The fields from SystemMemoryMapHob can be used to generate SMBIOS type 17. Tested=On OCP Delta Lake, verify the values are expected. Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45797/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Gerrit-Change-Number: 45797 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Isaac W Oram <isaac.w.oram(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 7 -- Cache Information
by Morgan Jang (Code Review) 06 Oct '20

06 Oct '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44059 ) Change subject: mb/ocp/deltalake: Update SMBIOS type 7 -- Cache Information ...................................................................... mb/ocp/deltalake: Update SMBIOS type 7 -- Cache Information According to BIOS writer`s guide, L1 Data cache size and L1 Instruction cache size should be combined, and multiply the cache size of L1 and L2 by the number of cores TEST=Execute "dmidecode -t 4" to check if the cache information is correct for Deltalake platform Change-Id: Ibfb7d048046ff69fd3f0d18359193f80b8f39911 Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/ocp/deltalake/ramstage.c 3 files changed, 79 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/44059/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 070c7ea..ead956e 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -607,6 +607,20 @@ return 0x02; /* Unknown */ } +unsigned int __weak smbios_cache_error_correction_type(void) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN; /* Unknown */ +} +unsigned int __weak smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_UNKNOWN; /* Unknown */ +} + +unsigned int __weak smbios_cache_conf_operation_mode(u8 level) +{ + return 3; /* Unknown */ +} + static int smbios_write_type1(unsigned long *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; @@ -766,8 +780,10 @@ { struct smbios_type7 *t = (struct smbios_type7 *)*current; int len = sizeof(struct smbios_type7); - static unsigned int cnt = 0; + static unsigned int cnt = 1; char buf[8]; + u8 core_count; + struct cpuid_result res; memset(t, 0, sizeof(struct smbios_type7)); t->type = SMBIOS_CACHE_INFORMATION; @@ -780,7 +796,7 @@ t->cache_configuration = SMBIOS_CACHE_CONF_LEVEL(level) | SMBIOS_CACHE_CONF_LOCATION(0) | /* Internal */ SMBIOS_CACHE_CONF_ENABLED(1) | /* Enabled */ - SMBIOS_CACHE_CONF_OPERATION_MODE(3); /* Unknown */ + SMBIOS_CACHE_CONF_OPERATION_MODE(smbios_cache_conf_operation_mode(level)); if (max_cache_size < (SMBIOS_CACHE_SIZE_MASK * KiB)) { t->max_cache_size = max_cache_size / KiB; @@ -816,11 +832,33 @@ t->installed_size2 |= SMBIOS_CACHE_SIZE2_UNIT_64KB; } + if (cpu_have_cpuid() && cpuid_get_max_func() >= 0xb) { + uint32_t leaf_b_cores = 0, leaf_b_threads = 0; + res = cpuid_ext(0xb, 1); + leaf_b_cores = res.ebx; + res = cpuid_ext(0xb, 0); + leaf_b_threads = res.ebx; + /* if hyperthreading is not available, pretend this is 1 */ + if (leaf_b_threads == 0) + leaf_b_threads = 1; + + core_count = leaf_b_cores / leaf_b_threads; + } else { + core_count = (res.ebx >> 16) & 0xff; + } + + if (level == 0 || level == 1 || level == 2) { + t->max_cache_size *= core_count; + t->installed_size *= core_count; + t->max_cache_size2 *= core_count; + t->installed_size2 *= core_count; + } + t->associativity = associativity; t->supported_sram_type = sram_type; t->current_sram_type = sram_type; t->cache_speed = 0; /* Unknown */ - t->error_correction_type = SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN; + t->error_correction_type = smbios_cache_error_correction_type(); t->system_cache_type = type; len = t->length + smbios_string_table_len(t->eos); @@ -880,6 +918,7 @@ unsigned int cnt = 0; int len = 0; u32 leaf; + size_t cache0_size = 0; if (!cpu_have_cpuid()) return len; @@ -916,7 +955,7 @@ const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; - const size_t cache_size = assoc * partitions * cache_line_size * + size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; if (!cache_type) @@ -938,6 +977,16 @@ break; } + if (level == 1 && type == SMBIOS_CACHE_TYPE_DATA) { + cache0_size = cache_size; + continue; + } + + if (level == 1 && type == SMBIOS_CACHE_TYPE_INSTRUCTION) { + cache_size += cache0_size; + type = SMBIOS_CACHE_TYPE_UNIFIED; + } + if (CPUID_CACHE_FULL_ASSOC(res)) associativity = SMBIOS_CACHE_ASSOCIATIVITY_FULL; else @@ -946,7 +995,7 @@ const int h = (*handle)++; update_max(len, *max_struct_size, smbios_write_type7(current, h, - level, SMBIOS_CACHE_SRAM_TYPE_UNKNOWN, associativity, + level, smbios_cache_sram_type(), associativity, type, cache_size, cache_size)); if (type4) { diff --git a/src/include/smbios.h b/src/include/smbios.h index 45c550a..7cbf391 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -54,6 +54,10 @@ const char *smbios_chassis_serial_number(void); const char *smbios_processor_serial_number(void); +unsigned int smbios_cache_error_correction_type(void); +unsigned int smbios_cache_sram_type(void); +unsigned int smbios_cache_conf_operation_mode(u8 level); + /* Used by mainboard to add port information of type 8 */ struct port_information; int smbios_write_type8(unsigned long *current, int *handle, diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 4418ea4..2805f85 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -210,6 +210,27 @@ } #endif +unsigned int smbios_cache_error_correction_type(void) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_SINGLE_BIT; +} +unsigned int smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_SYNCHRONOUS; +} + +unsigned int smbios_cache_conf_operation_mode(u8 level) +{ + switch (level) { + case 1: + return 1; /* Writre Back */ + case 2: + case 3: + return 2; /* Varies with Memory Address*/ + default: + return 3; + } +} static void mainboard_enable(struct device *dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfb7d048046ff69fd3f0d18359193f80b8f39911 Gerrit-Change-Number: 44059 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff: Fix wyvern Port 12 to be enabled
by Edward O'Callaghan (Code Review) 06 Oct '20

06 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46063 ) Change subject: mb/google/puff: Fix wyvern Port 12 to be enabled ...................................................................... mb/google/puff: Fix wyvern Port 12 to be enabled A SSD is connected to port #12. BUG=b:162909831 BRANCH=puff TEST=none Change-Id: Iefdda80301d28edfb5c5be116eacb48129794ec9 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/wyvern/overridetree.cb 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46063/1 diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb index 3320455..9ffbaab 100644 --- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb @@ -395,7 +395,9 @@ device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) register "PcieRpSlotImplemented[10]" = "1" end - device pci 1e.3 off end # GSPI #1 + device pci 1e.3 on # SSD Port 12 + register "PcieRpSlotImplemented[11]" = "1" + end end # VR Settings Configuration for 4 Domains -- To view, visit https://review.coreboot.org/c/coreboot/+/46063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefdda80301d28edfb5c5be116eacb48129794ec9 Gerrit-Change-Number: 46063 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: zork/var/ezkinil: Adjust Touchscreen suspend off timing
by Lucas Chen (Code Review) 06 Oct '20

06 Oct '20

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45785 ) Change subject: zork/var/ezkinil: Adjust Touchscreen suspend off timing ...................................................................... zork/var/ezkinil: Adjust Touchscreen suspend off timing Adjust Touchscreen delay off values to let suspend off timing match power down specificatiion. BRANCH=zork BUG=b:163434386 TEST=Measuring scope timing Change-Id: I58866122f441cc3c427e659b8a5fdb6643987882 --- M src/mainboard/google/zork/variants/ezkinil/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/45785/1 diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 614d6ab..a60f427 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -86,7 +86,9 @@ register "generic.enable_delay_ms" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "5" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_off_delay_ms" = "10" register "generic.stop_delay_ms" = "300" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/45785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58866122f441cc3c427e659b8a5fdb6643987882 Gerrit-Change-Number: 45785 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add new mmc APIs
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44492 ) Change subject: soc/intel/common: Add new mmc APIs ...................................................................... Patch Set 4: (8 comments) https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@7 PS2, Line 7: intel/common > nit: soc/intel/common Done https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@7 PS2, Line 7: apis > nit: APIs Done https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@9 PS2, Line 9: emmc > nit: eMMC Done https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@9 PS2, Line 9: apis > nit: APIs Done https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@9 PS2, Line 9: dll > nit: DLL Done https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@13 PS2, Line 13: dll > nit: DLL Done https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@13 PS2, Line 13: emmc > nit: eMMC Done https://review.coreboot.org/c/coreboot/+/44492/2/src/soc/intel/common/block… File src/soc/intel/common/block/scs/mmc.c: https://review.coreboot.org/c/coreboot/+/44492/2/src/soc/intel/common/block… PS2, Line 27: EMMC_TX_CMD_CNTL_OFFSET); > nit: these lines should fit in 96 characters Done -- To view, visit https://review.coreboot.org/c/coreboot/+/44492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70f14d95f81d30360f5a68fbb34b50425e98ece Gerrit-Change-Number: 44492 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 06 Oct 2020 01:10:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2020