coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
by Karthik Ramasubramanian (Code Review) 05 Oct '20

05 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Evan Green, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45912 to look at the new patch set (#5). Change subject: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer ...................................................................... mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer The camera sensor component chosen for UFC and WFC have address conflict. Resolve it by enabling GPIO based I2C Multiplexer BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Here is the output SSDT: Scope (\_SB.PCI0.I2C3) { Device (MUX0) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0125 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "mux-gpios", Package (0x04) { \_SB.PCI0.I2C3.MUX0, Zero, Zero, Zero } } } }) } } Scope (\_SB.PCI0.I2C3.MUX0) { Device (MXA0) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_ADR, Zero) // _ADR: Address } } Scope (\_SB.PCI0.I2C3.MUX0) { Device (MXA1) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_ADR, One) // _ADR: Address } } Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/variants/waddledee/overridetree.cb 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/45912/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Gerrit-Change-Number: 45912 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Karthik Ramasubramanian (Code Review) 05 Oct '20

05 Oct '20

Hello Patrick Georgi, Martin Roth, Furquan Shaikh, Justin TerAvest, Evan Green, Duncan Laurie, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45911 to look at the new patch set (#5). Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... drivers/i2c: Add chip driver for GPIO based I2C multiplexer Add identifiers in ACPI tables for GPIO based I2C multiplexer. The multiplexer device defines the GPIO resource used to select the adapter/client lines. The multiplexer adapter device defines the address to select the adapter/client lines. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Here is the output SSDT: Scope (\_SB.PCI0.I2C3) { Device (MUX0) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0125 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "mux-gpios", Package (0x04) { \_SB.PCI0.I2C3.MUX0, Zero, Zero, Zero } } } }) } } Scope (\_SB.PCI0.I2C3.MUX0) { Device (MXA0) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_ADR, Zero) // _ADR: Address } } Scope (\_SB.PCI0.I2C3.MUX0) { Device (MXA1) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_ADR, One) // _ADR: Address } } Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- A src/drivers/i2c/gpio_mux/Kconfig A src/drivers/i2c/gpio_mux/Makefile.inc A src/drivers/i2c/gpio_mux/chip.h A src/drivers/i2c/gpio_mux/gpio_mux.c 4 files changed, 146 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45911/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/google: add SPD_PART_NUMBER_IN_CBI Kconfig option
by Nick Vaccaro (Code Review) 05 Oct '20

05 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45635 ) Change subject: vendorcode/google: add SPD_PART_NUMBER_IN_CBI Kconfig option ...................................................................... vendorcode/google: add SPD_PART_NUMBER_IN_CBI Kconfig option Add SPD_PART_NUMBER_IN_CBI Kconfig option to declare whether the SPD Module Part Number (memory part name) is stored in the CBI. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also built coreboot for hatch and dedede and verified that the build succeeds without error. Change-Id: I0d393efd0fc731daa70d3990e5b69865be99b78b Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/volteer/Kconfig M src/vendorcode/google/chromeos/Kconfig 4 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45635/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 79c2995..bc01ab9 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -37,6 +37,7 @@ bool default y select CHROMEOS_CSE_BOARD_RESET_OVERRIDE + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index ca310ed..44259a4 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -47,6 +47,7 @@ config CHROMEOS bool default y + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index d2880bf..34d34d0 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -35,6 +35,7 @@ bool default y select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 0528d00..3b335a4 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -103,5 +103,12 @@ does not understand the new cr50 strap config (applicable only to boards using strap config 0xe). Enabling this config will help to override the default global reset. +config CHROMEOS_DRAM_PART_NUMBER_IN_CBI + def_bool y + depends on EC_GOOGLE_CHROMEEC + help + Some boards declare the DRAM part number in the CBI instead of the SPD. This option + allows those boards to declare that their DRAM part number is stored in the CBI. + endif # CHROMEOS endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/45635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d393efd0fc731daa70d3990e5b69865be99b78b Gerrit-Change-Number: 45635 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc: move mainboard_get_dram_part_num prototype to memory_info.h
by Nick Vaccaro (Code Review) 05 Oct '20

05 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45879 ) Change subject: soc: move mainboard_get_dram_part_num prototype to memory_info.h ...................................................................... soc: move mainboard_get_dram_part_num prototype to memory_info.h BUG=b:169774661, b:168724473 TEST="emerge-volteer coreboot && emerge-nocturne coreboot && emerge-dedede coreboot" and verify they build successfully. Change-Id: I8b228475621ca1035fe13f8311355fc3b926e897 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/include/memory_info.h M src/soc/intel/alderlake/include/soc/romstage.h M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/elkhartlake/include/soc/romstage.h M src/soc/intel/jasperlake/include/soc/romstage.h M src/soc/intel/tigerlake/include/soc/romstage.h 6 files changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/45879/1 diff --git a/src/include/memory_info.h b/src/include/memory_info.h index d9d9c37..1ba7329 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -108,4 +108,10 @@ struct dimm_info dimm[DIMM_INFO_TOTAL]; } __packed; +/* + * mainboard_get_dram_part_num returns a DRAM part number override string + * return NULL = no part number override provided by mainboard + * return non-NULL = pointer to a string terminating in '\0' + */ +const char *mainboard_get_dram_part_num(void); #endif diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h index 55469a3..c72c8aa 100644 --- a/src/soc/intel/alderlake/include/soc/romstage.h +++ b/src/soc/intel/alderlake/include/soc/romstage.h @@ -6,8 +6,6 @@ #include <fsp/api.h> #include <stddef.h> -/* Provide a callback to allow mainboard to override the DRAM part number. */ -const char *mainboard_get_dram_part_num(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index f99175f..ae9aa60 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -7,8 +7,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); -/* Provide a callback to allow mainboard to override the DRAM part number. */ -const char *mainboard_get_dram_part_num(void); void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/elkhartlake/include/soc/romstage.h b/src/soc/intel/elkhartlake/include/soc/romstage.h index 1cffcb9..3772db4 100644 --- a/src/soc/intel/elkhartlake/include/soc/romstage.h +++ b/src/soc/intel/elkhartlake/include/soc/romstage.h @@ -5,8 +5,6 @@ #include <fsp/api.h> -/* Provide a callback to allow mainboard to override the DRAM part number. */ -const char *mainboard_get_dram_part_num(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/jasperlake/include/soc/romstage.h b/src/soc/intel/jasperlake/include/soc/romstage.h index 1cffcb9..3772db4 100644 --- a/src/soc/intel/jasperlake/include/soc/romstage.h +++ b/src/soc/intel/jasperlake/include/soc/romstage.h @@ -5,8 +5,6 @@ #include <fsp/api.h> -/* Provide a callback to allow mainboard to override the DRAM part number. */ -const char *mainboard_get_dram_part_num(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index 1cffcb9..3772db4 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -5,8 +5,6 @@ #include <fsp/api.h> -/* Provide a callback to allow mainboard to override the DRAM part number. */ -const char *mainboard_get_dram_part_num(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void romstage_pch_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/45879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b228475621ca1035fe13f8311355fc3b926e897 Gerrit-Change-Number: 45879 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib, mb, soc: change mainboard_get_dram_part_num() prototype
by Nick Vaccaro (Code Review) 05 Oct '20

05 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45873 ) Change subject: lib, mb, soc: change mainboard_get_dram_part_num() prototype ...................................................................... lib, mb, soc: change mainboard_get_dram_part_num() prototype Change mainboard_get_dram_part_num() to return a constant character pointer to a null-terminated C string and to take no input parameters. This also addresses the issue that different SOCs and motherboards were using different definitions for mainboard_get_dram_part_num by consolidating to a single definition. BUG=b:168724473 TEST="emerge-volteer coreboot && emerge-dedede coreboot && emerge-hatch coreboot" and verify build completes successfully. Change-Id: Ie7664eab65a2b9e25b7853bf68baf2525b040487 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/dedede/romstage.c M src/mainboard/google/hatch/romstage_spd_cbfs.c M src/mainboard/google/volteer/romstage.c M src/soc/intel/alderlake/include/soc/romstage.h M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/elkhartlake/include/soc/romstage.h M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/jasperlake/include/soc/romstage.h M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/romstage/romstage.c 13 files changed, 64 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45873/1 diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 8028db0..e143f70 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -22,17 +22,15 @@ memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) +const char *mainboard_get_dram_part_num(void) { static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], sizeof(part_num_store)) < 0) { printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - return false; + return NULL; } - *part_num = &part_num_store[0]; - *len = strlen(part_num_store); - return true; + return part_num_store; } diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c index a9a65e9..b8937de 100644 --- a/src/mainboard/google/hatch/romstage_spd_cbfs.c +++ b/src/mainboard/google/hatch/romstage_spd_cbfs.c @@ -57,7 +57,7 @@ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } -void mainboard_get_dram_part_num(const char **part_num, size_t *len) +const char *mainboard_get_dram_part_num(void) { static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; static enum { @@ -77,8 +77,7 @@ } if (part_num_state == PART_NUM_NOT_IN_CBI) - return; + return NULL; - *part_num = &part_num_store[0]; - *len = strlen(part_num_store) + 1; + return part_num_store; } diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 552648b..51a4ebc 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -29,16 +29,14 @@ meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); } -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) +const char *mainboard_get_dram_part_num(void) { static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; if (google_chromeec_cbi_get_dram_part_num(part_num_store, sizeof(part_num_store)) < 0) { printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); - return false; + return NULL; } - *part_num = part_num_store; - *len = strlen(part_num_store); - return true; + return part_num_store; } diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h index 716602c..55469a3 100644 --- a/src/soc/intel/alderlake/include/soc/romstage.h +++ b/src/soc/intel/alderlake/include/soc/romstage.h @@ -7,7 +7,7 @@ #include <stddef.h> /* Provide a callback to allow mainboard to override the DRAM part number. */ -const char *mainboard_get_dram_part_num(size_t *len); +const char *mainboard_get_dram_part_num(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 9f4fbb6..a62a726 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -21,7 +21,7 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -__weak const char *mainboard_get_dram_part_num(size_t *len) +const char * __weak mainboard_get_dram_part_num(void) { /* Default weak implementation, no need to override part number. */ return NULL; @@ -41,7 +41,8 @@ const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID; const uint8_t *serial_num; const char *dram_part_num = NULL; - size_t dram_part_num_len; + size_t dram_part_num_len = 0; + bool part_name_overridden = false; /* Locate the memory info HOB, presence validated by raminit */ meminfo_hob = fsp_find_extension_hob_by_guid( @@ -64,7 +65,11 @@ memset(mem_info, 0, sizeof(*mem_info)); /* Allow mainboard to override DRAM part number. */ - dram_part_num = mainboard_get_dram_part_num(&dram_part_num_len); + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) { + dram_part_num_len = strlen(dram_part_num); + part_name_overridden = true; + } /* Save available DIMM information */ index = 0; @@ -84,7 +89,7 @@ /* If there is no DRAM part number overridden by * mainboard then use original one. */ - if (!dram_part_num) { + if (!part_name_overridden) { dram_part_num_len = sizeof(src_dimm->ModulePartNum); dram_part_num = (const char *) &src_dimm->ModulePartNum[0]; diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index 4e513f0..f99175f 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -8,7 +8,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); /* Provide a callback to allow mainboard to override the DRAM part number. */ -void mainboard_get_dram_part_num(const char **part_num, size_t *len); +const char *mainboard_get_dram_part_num(void); void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index c56add7..74dc20f 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -23,7 +23,7 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -void __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) +const char * __weak mainboard_get_dram_part_num(void) { /* Default weak implementation, no need to override part number. */ } @@ -42,7 +42,7 @@ const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; const char *dram_part_num; - size_t dram_part_num_len; + size_t dram_part_num_len = 0; /* Locate the memory info HOB, presence validated by raminit */ memory_info_hob = fsp_find_extension_hob_by_guid( @@ -79,13 +79,16 @@ if (src_dimm->Status != DIMM_PRESENT) continue; - dram_part_num_len = sizeof(src_dimm->ModulePartNum); - dram_part_num = (const char *) - &src_dimm->ModulePartNum[0]; - /* Allow mainboard to override DRAM part number. */ - mainboard_get_dram_part_num(&dram_part_num, - &dram_part_num_len); + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) { + dram_part_num_len = strlen(dram_part_num); + } else { + dram_part_num_len = + sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) + &src_dimm->ModulePartNum[0]; + } u8 memProfNum = memory_info_hob->MemoryProfile; diff --git a/src/soc/intel/elkhartlake/include/soc/romstage.h b/src/soc/intel/elkhartlake/include/soc/romstage.h index baa35c5..1cffcb9 100644 --- a/src/soc/intel/elkhartlake/include/soc/romstage.h +++ b/src/soc/intel/elkhartlake/include/soc/romstage.h @@ -6,7 +6,7 @@ #include <fsp/api.h> /* Provide a callback to allow mainboard to override the DRAM part number. */ -bool mainboard_get_dram_part_num(const char **part_num, size_t *len); +const char *mainboard_get_dram_part_num(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index 09b1744..d7b2959 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -21,10 +21,10 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -bool __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) +const char * __weak mainboard_get_dram_part_num(void) { /* Default implementation, no need to override part number. */ - return false; + return NULL; } /* Save the DIMM information for SMBIOS table 17 */ @@ -42,8 +42,8 @@ FSP_SMBIOS_MEMORY_INFO_GUID; const uint8_t *serial_num; const char *dram_part_num = NULL; - size_t dram_part_num_len; - bool is_dram_part_overridden = false; + size_t dram_part_num_len = 0; + bool part_name_overridden = false; /* Locate the memory info HOB, presence validated by raminit */ meminfo_hob = fsp_find_extension_hob_by_guid( @@ -66,8 +66,11 @@ memset(mem_info, 0, sizeof(*mem_info)); /* Allow mainboard to override DRAM part number. */ - is_dram_part_overridden = mainboard_get_dram_part_num(&dram_part_num, - &dram_part_num_len); + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) { + dram_part_num = strlen(dram_part_num); + part_name_overridden = true; + } /* Save available DIMM information */ index = 0; @@ -89,7 +92,7 @@ /* If there is no DRAM part number overridden by * mainboard then use original one. */ - if (!is_dram_part_overridden) { + if (!part_name_overridden) { dram_part_num_len = sizeof(src_dimm->ModulePartNum); dram_part_num = (const char *) &src_dimm->ModulePartNum[0]; diff --git a/src/soc/intel/jasperlake/include/soc/romstage.h b/src/soc/intel/jasperlake/include/soc/romstage.h index baa35c5..1cffcb9 100644 --- a/src/soc/intel/jasperlake/include/soc/romstage.h +++ b/src/soc/intel/jasperlake/include/soc/romstage.h @@ -6,7 +6,7 @@ #include <fsp/api.h> /* Provide a callback to allow mainboard to override the DRAM part number. */ -bool mainboard_get_dram_part_num(const char **part_num, size_t *len); +const char *mainboard_get_dram_part_num(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index db014ea..6a3ebd6 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -21,10 +21,10 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -bool __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) +const char * __weak mainboard_get_dram_part_num(void) { /* Default weak implementation, no need to override part number. */ - return false; + return NULL; } /* Save the DIMM information for SMBIOS table 17 */ @@ -42,8 +42,8 @@ FSP_SMBIOS_MEMORY_INFO_GUID; const uint8_t *serial_num; const char *dram_part_num = NULL; - size_t dram_part_num_len; - bool is_dram_part_overridden = false; + size_t dram_part_num_len = 0; + bool part_name_overridden = false; /* Locate the memory info HOB, presence validated by raminit */ meminfo_hob = fsp_find_extension_hob_by_guid( @@ -66,8 +66,12 @@ memset(mem_info, 0, sizeof(*mem_info)); /* Allow mainboard to override DRAM part number. */ - is_dram_part_overridden = mainboard_get_dram_part_num(&dram_part_num, + dram_part_num = mainboard_get_dram_part_num(&, &dram_part_num_len); + if (dram_part_num) { + dram_part_num_len = strlen(dram_part_num); + part_name_overridden = true; + } /* Save available DIMM information */ index = 0; @@ -89,7 +93,7 @@ /* If there is no DRAM part number overridden by * mainboard then use original one. */ - if (!is_dram_part_overridden) { + if (!part_name_overridden) { dram_part_num_len = sizeof(src_dimm->ModulePartNum); dram_part_num = (const char *) &src_dimm->ModulePartNum[0]; diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index baa35c5..1cffcb9 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -6,7 +6,7 @@ #include <fsp/api.h> /* Provide a callback to allow mainboard to override the DRAM part number. */ -bool mainboard_get_dram_part_num(const char **part_num, size_t *len); +const char *mainboard_get_dram_part_num(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index db014ea..fd18fea 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -21,10 +21,10 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -bool __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) +const char * __weak mainboard_get_dram_part_num(void) { /* Default weak implementation, no need to override part number. */ - return false; + return NULL; } /* Save the DIMM information for SMBIOS table 17 */ @@ -42,8 +42,8 @@ FSP_SMBIOS_MEMORY_INFO_GUID; const uint8_t *serial_num; const char *dram_part_num = NULL; - size_t dram_part_num_len; - bool is_dram_part_overridden = false; + size_t dram_part_num_len = 0; + bool part_name_overridden = false; /* Locate the memory info HOB, presence validated by raminit */ meminfo_hob = fsp_find_extension_hob_by_guid( @@ -66,8 +66,11 @@ memset(mem_info, 0, sizeof(*mem_info)); /* Allow mainboard to override DRAM part number. */ - is_dram_part_overridden = mainboard_get_dram_part_num(&dram_part_num, - &dram_part_num_len); + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) { + dram_part_num_len = strlen(dram_part_num); + part_name_overridden = true; + } /* Save available DIMM information */ index = 0; @@ -89,7 +92,7 @@ /* If there is no DRAM part number overridden by * mainboard then use original one. */ - if (!is_dram_part_overridden) { + if (!part_name_overridden) { dram_part_num_len = sizeof(src_dimm->ModulePartNum); dram_part_num = (const char *) &src_dimm->ModulePartNum[0]; -- To view, visit https://review.coreboot.org/c/coreboot/+/45873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7664eab65a2b9e25b7853bf68baf2525b040487 Gerrit-Change-Number: 45873 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

2 17

Change in coreboot[master]: soc/intel/elkhartlake: add __weak to mainboard_get_dram_part_num()
by Nick Vaccaro (Code Review) 05 Oct '20

05 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45871 ) Change subject: soc/intel/elkhartlake: add __weak to mainboard_get_dram_part_num() ...................................................................... soc/intel/elkhartlake: add __weak to mainboard_get_dram_part_num() Add missing __weak declaration to Elkhart Lake's definition of mainboard_get_dram_part_num(). BUG=b:168724473 TEST=none Change-Id: I883d662315a9ab91eb6183ebcdfd7e7cc8064c64 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/elkhartlake/romstage/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45871/1 diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index d68d2da..09b1744 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -21,7 +21,7 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) +bool __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) { /* Default implementation, no need to override part number. */ return false; -- To view, visit https://review.coreboot.org/c/coreboot/+/45871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I883d662315a9ab91eb6183ebcdfd7e7cc8064c64 Gerrit-Change-Number: 45871 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/skl: guard ACPI PM timer emulation enablement
by Michael Niewöhner (Code Review) 05 Oct '20

05 Oct '20

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45953 ) Change subject: soc/intel/skl: guard ACPI PM timer emulation enablement ...................................................................... Abandoned BIOS spec says, emulation shall be always enabled -- To view, visit https://review.coreboot.org/c/coreboot/+/45953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I529cdbe759e9c9270493bd3fff42ded65c74a6b4 Gerrit-Change-Number: 45953 Gerrit-PatchSet: 19 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: guard ACPI timer emulation en...
by Michael Niewöhner (Code Review) 05 Oct '20

05 Oct '20

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45956 ) Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: guard ACPI timer emulation enablement ...................................................................... Abandoned BIOS spec says, emulation shall be always enabled -- To view, visit https://review.coreboot.org/c/coreboot/+/45956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3e2eaf37b3e6f1dc3360331d343db9aa178adcc Gerrit-Change-Number: 45956 Gerrit-PatchSet: 19 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: drop duplicate PM ACPI timer ...
by Michael Niewöhner (Code Review) 05 Oct '20

05 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45958 to look at the new patch set (#21). Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: drop duplicate PM ACPI timer disabling ...................................................................... [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: drop duplicate PM ACPI timer disabling FSP already disables the PM ACPI timer, when EnableTcoTimer=0, so there is no need to do it again in coreboot. Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/finalize.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/finalize.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 17 files changed, 4 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45958/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/45958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Gerrit-Change-Number: 45958 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: PM ACPI timer state from Kconfig
by Michael Niewöhner (Code Review) 05 Oct '20

05 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45957 to look at the new patch set (#21). Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: PM ACPI timer state from Kconfig ...................................................................... [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: PM ACPI timer state from Kconfig Sets the FSP option for PM ACPI timer enablement from the devicetree option, to be able to disable the timer for power savings. Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 4 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45957/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/45957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Gerrit-Change-Number: 45957 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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