coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common: Add new mmc APIS
by Bora Guvendik (Code Review) 06 Oct '20

06 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Angel Pons, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44492 to look at the new patch set (#3). Change subject: soc/intel/common: Add new mmc APIS ...................................................................... soc/intel/common: Add new mmc APIS Add APIS to read single eMMC DLL register and to read/write all registers at once. BUG=b:140124451 TEST=Read / write eMMC DLL registers. Change-Id: Ie70f14d95f81d30360f5a68fbb34b50425e98ece Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/scs/mmc.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/44492/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/44492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70f14d95f81d30360f5a68fbb34b50425e98ece Gerrit-Change-Number: 44492 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Update TCSS PM flow
by John Zhao (Code Review) 06 Oct '20

06 Oct '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45014 ) Change subject: soc/intel/tigerlake: Update TCSS PM flow ...................................................................... soc/intel/tigerlake: Update TCSS PM flow s0xi fails while USB4 device is connected and PCIe tunneling is up. There is need to change PM flow along with TBT firmware update. This change invokes D3CE and D3CX in DMA _PS0 when _OFF was not called earlier. BUG=b:158777291 TEST=Validated s0ix with USB4 device connected along with TBT firmware QS variants TBT_TGL_B0_CHROME_Rev33 image. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Iebc8065fe4c8600960d089577608890ab12a95fc --- M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl 3 files changed, 33 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45014/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 9893833..ed43e05 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -524,6 +524,7 @@ If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) { Printf("TDM0 does not exist.") } Else { + \_SB.PCI0.TDM0.SCMP = 3 If (\_SB.PCI0.TDM0.STAT == 0) { /* DMA0 is in D3Cold early. */ \_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */ @@ -554,6 +555,7 @@ If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) { Printf("TDM0 does not exist.") } Else { + \_SB.PCI0.TDM0.SCMP = 2 If (\_SB.PCI0.TDM0.STAT == 1) { /* DMA0 is not in D3Cold now. */ \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ @@ -579,6 +581,7 @@ If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) { Printf("TDM1 does not exist.") } Else { + \_SB.PCI0.TDM1.SCMP = 3 If (\_SB.PCI0.TDM1.STAT == 0) { /* DMA1 is in D3Cold early. */ \_SB.PCI0.TDM1.D3CX() /* RTD3 Exit */ @@ -609,6 +612,7 @@ If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) { Printf("TDM1 does not exist.") } Else { + \_SB.PCI0.TDM1.SCMP = 2 If (\_SB.PCI0.TDM1.STAT == 1) { /* DMA1 is not in D3Cold now */ \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index da2e8fe..df96576 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -72,6 +72,28 @@ */ Name (SD3C, 0) +/* SW CM Power State Flow Control */ +Name (SCMP, 0) + +Method (_PS0, 0, Serialized) +{ + If (SCMP != 3) { + If (DUID == 0) { + \_SB.PCI0.TG0F() + \_SB.PCI0.TG0N() + } Else { + \_SB.PCI0.TG1F() + \_SB.PCI0.TG1N() + } + } + SCMP = 0 +} + +Method (_PS3, 0, Serialized) +{ + SCMP = 1 +} + Method (_DSW, 3) { /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index abca5d1..9571e19 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -76,10 +76,14 @@ Method (_DSW, 3) { - C2PM (Arg0, Arg1, Arg2, DCPM) /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ - \_SB.PCI0.TDM0.SD3C = Arg1 - \_SB.PCI0.TDM1.SD3C = Arg1 + If ((TUID == 0) || (TUID == 1)) { + \_SB.PCI0.TDM0.SD3C = Arg1 + } Else { + \_SB.PCI0.TDM1.SD3C = Arg1 + } + + C2PM (Arg0, Arg1, Arg2, DCPM) } Method (_PRW, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/45014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc8065fe4c8600960d089577608890ab12a95fc Gerrit-Change-Number: 45014 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
by Furquan Shaikh (Code Review) 05 Oct '20

05 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45912 ) Change subject: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45912/5/src/mainboard/google/deded… File src/mainboard/google/dedede/Kconfig.name: https://review.coreboot.org/c/coreboot/+/45912/5/src/mainboard/google/deded… PS5, Line 54: select DRIVERS_I2C_GPIO_MUX It should be fine to do this in Kconfig under BOARD_GOOGLE_BASEBOARD_DEDEDE. Linker should drop the unused components for other boards. -- To view, visit https://review.coreboot.org/c/coreboot/+/45912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Gerrit-Change-Number: 45912 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Oct 2020 21:27:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Furquan Shaikh (Code Review) 05 Oct '20

05 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45911 ) Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... Patch Set 5: (5 comments) https://review.coreboot.org/c/coreboot/+/45911/5/src/drivers/i2c/gpio_mux/c… File src/drivers/i2c/gpio_mux/chip.h: https://review.coreboot.org/c/coreboot/+/45911/5/src/drivers/i2c/gpio_mux/c… PS5, Line 16: char const https://review.coreboot.org/c/coreboot/+/45911/5/src/drivers/i2c/gpio_mux/c… PS5, Line 17: acpi_hid I don't think we need to take in acpi_hid as a parameter from the mainboard. This should be a fixed HID value based on what the kernel driver expects. From the kernel driver implementation, I don't see any ACPI HID since the driver wasn't written for ACPI support. The way we have handled this for some other drivers is using PRP0001 HID and device tree compatible string in _DSD. I am guessing that we would probably go down the same route here. References: 1. GPIO keys driver in coreboot: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/t… 2. https://www.kernel.org/doc/html/latest/firmware-guide/acpi/enumeration.html… https://review.coreboot.org/c/coreboot/+/45911/5/src/drivers/i2c/gpio_mux/c… PS5, Line 19: /* GPIOs used to select the mux lines */ : uint32_t mux_gpio_count; : struct acpi_gpio mux_gpio[MAX_NUM_MUX_GPIOS]; Should we put these in a structure just to make it clear that they are applicable only to i2c_mux? https://review.coreboot.org/c/coreboot/+/45911/4/src/drivers/i2c/gpio_mux/g… File src/drivers/i2c/gpio_mux/gpio_mux.c: PS4: > Should this really just two separate chip drivers? It looks like the acpi_fill_ssdt() for each is to […] I proposed that just to keep the support for the mux and the bus closer in coreboot. Probably we can organize it like drivers/i2c/gpio_mux/mux and drivers/i2c/gpio_mux/bus and have 2 separate chip drivers support them? https://review.coreboot.org/c/coreboot/+/45911/5/src/drivers/i2c/gpio_mux/g… File src/drivers/i2c/gpio_mux/gpio_mux.c: https://review.coreboot.org/c/coreboot/+/45911/5/src/drivers/i2c/gpio_mux/g… PS5, Line 108: dev->ops = &i2c_gpio_mux_ops; I see that Tim has commented about having 2 separate chip drivers. In case we don't go with that, it would be good to add separate ops here for mux and bus so that you don't have to check the device type in other functions: static struct device_operations i2c_gpio_mux_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .scan_bus = scan_static_bus, .acpi_name = mux_acpi_name, .acpi_fill_ssdt = mux_fill_ssdt, }; static struct device_operations i2c_gpio_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .acpi_name = bus_acpi_name, .acpi_fill_ssdt = bus_fill_ssdt, }; and in here you can set the ops depending upon the device type: static void i2c_gpio_mux_enable(struct device *dev) { struct drivers_i2c_gpio_mux_config *config = dev->chip_info; if (!config) return; if (dev->device_type == I2C_MUX) dev->ops = &i2c_gpio_mux_ops; else if (dev->device_type == I2C_MUX_ADAPTER) dev->ops = &i2c_gpio_bus_ops; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Oct 2020 21:26:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Fleex: Resume from suspend on critical battery
by Daisuke Nojiri (Code Review) 05 Oct '20

05 Oct '20

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45967 ) Change subject: Fleex: Resume from suspend on critical battery ...................................................................... Fleex: Resume from suspend on critical battery This patch makes Fleex EC wake up AP from s0ix when the state of charge drops to 5%. Demonstrated as follows: 1. Boot Fleex. 2. Run powerd_dbus_suspend. 3. On EC, run battfake 5. 4. System resumes. BUG=b:163721887 BRANCH=Octopus TEST=Verified on Fleex: Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I4a998ad0aef5a7cfc6fd18995bde5571e6127e77 --- M src/mainboard/google/octopus/variants/fleex/include/variant/ec.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45967/1 diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h index 60c53dc..29aee4f 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h @@ -5,4 +5,9 @@ #include <baseboard/ec.h> +#undef MAINBOARD_EC_S0IX_WAKE_EVENTS +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)) + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a998ad0aef5a7cfc6fd18995bde5571e6127e77 Gerrit-Change-Number: 45967 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/Makefile.inc: fail build when SPD would be empty
by Angel Pons (Code Review) 05 Oct '20

05 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45131 ) Change subject: lib/Makefile.inc: fail build when SPD would be empty ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/45131/14/src/lib/Makefile.inc File src/lib/Makefile.inc: https://review.coreboot.org/c/coreboot/+/45131/14/src/lib/Makefile.inc@360 PS14, Line 360: test -n "$(SPD_SOURCES)" || \ : (echo "HAVE_SPD_BIN_IN_CBFS is set but SPD_SOURCES is empty" && exit 1) > Agreed that we can potentially fix the problem by either using some default file or having a placeho […] Thank you very much, Furquan. -- To view, visit https://review.coreboot.org/c/coreboot/+/45131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Gerrit-Change-Number: 45131 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Oct 2020 18:45:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/Makefile.inc: fail build when SPD would be empty
by Furquan Shaikh (Code Review) 05 Oct '20

05 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45131 ) Change subject: lib/Makefile.inc: fail build when SPD would be empty ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/45131/14/src/lib/Makefile.inc File src/lib/Makefile.inc: https://review.coreboot.org/c/coreboot/+/45131/14/src/lib/Makefile.inc@360 PS14, Line 360: test -n "$(SPD_SOURCES)" || \ : (echo "HAVE_SPD_BIN_IN_CBFS is set but SPD_SOURCES is empty" && exit 1) > Thanks for the detailed explanation. […] Agreed that we can potentially fix the problem by either using some default file or having a placeholder file as you suggested. I will follow-up on Paul's change. As to why the SPDs are in SoC - yes that is a pending clean up to move the SPDs to a common location so that they don't have to live under SoC. -- To view, visit https://review.coreboot.org/c/coreboot/+/45131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Gerrit-Change-Number: 45131 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Oct 2020 18:26:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/spd_bin: add LPDDR4X case to spd_get_name()
by Nick Vaccaro (Code Review) 05 Oct '20

05 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45886 ) Change subject: lib/spd_bin: add LPDDR4X case to spd_get_name() ...................................................................... lib/spd_bin: add LPDDR4X case to spd_get_name() Add case for LPDDR4x to spd_get_name(). BUG=b:169800932, b:168724473 TEST=none Change-Id: I6bae373468b8ad5ae0a6b8dd6bbe14143afb85af Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/lib/spd_bin.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/45886/1 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 3888896..d14fd97 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -152,6 +152,7 @@ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_LPDDR4: + case SPD_DRAM_LPDDR4X: memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); spd_name[DDR4_SPD_PART_LEN] = 0; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/45886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bae373468b8ad5ae0a6b8dd6bbe14143afb85af Gerrit-Change-Number: 45886 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch,dedede,volteer: enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI
by Nick Vaccaro (Code Review) 05 Oct '20

05 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45883 ) Change subject: mb/google/hatch,dedede,volteer: enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI ...................................................................... mb/google/hatch,dedede,volteer: enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI Enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI on hatch, dedede, and volteer to use the common version of mainboard_get_dram_part_num(). Remove duplicate instances of mainboard_get_dram_part_num(). BUG=b:169789558, b:168724473 TEST="emerge-volteer coreboot && emerge-hatch coreboot && emerge-dedede coreboot" and verify it builds. Change-Id: I4e29d3e7ef0f3370eab9a6996a5c4a21a636b40e Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/romstage.c M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/romstage_spd_cbfs.c M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/romstage.c 6 files changed, 3 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/45883/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index bd7d36e..f3b2b0a 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -36,6 +36,7 @@ config CHROMEOS bool default y + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select CHROMEOS_CSE_BOARD_RESET_OVERRIDE select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index e143f70..02ebfac 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -21,16 +21,3 @@ memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } - -const char *mainboard_get_dram_part_num(void) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - return NULL; - } - - return part_num_store; -} diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index ecf156f..257ad77 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -47,6 +47,7 @@ config CHROMEOS bool default y + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c index b8937de..f3c38bb 100644 --- a/src/mainboard/google/hatch/romstage_spd_cbfs.c +++ b/src/mainboard/google/hatch/romstage_spd_cbfs.c @@ -56,28 +56,3 @@ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } - -const char *mainboard_get_dram_part_num(void) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - static enum { - PART_NUM_NOT_READ, - PART_NUM_AVAILABLE, - PART_NUM_NOT_IN_CBI, - } part_num_state = PART_NUM_NOT_READ; - - if (part_num_state == PART_NUM_NOT_READ) { - if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - part_num_state = PART_NUM_NOT_IN_CBI; - } else { - part_num_state = PART_NUM_AVAILABLE; - } - } - - if (part_num_state == PART_NUM_NOT_IN_CBI) - return NULL; - - return part_num_store; -} diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index f32b54a..eef8fe3 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -34,6 +34,7 @@ config CHROMEOS bool default y + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 51a4ebc..720ab7f 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -28,15 +28,3 @@ meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); } - -const char *mainboard_get_dram_part_num(void) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(part_num_store, - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); - return NULL; - } - return part_num_store; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e29d3e7ef0f3370eab9a6996a5c4a21a636b40e Gerrit-Change-Number: 45883 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: remove duplicate weak versions of mainboard_get_dram_part_...
by Nick Vaccaro (Code Review) 05 Oct '20

05 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45890 ) Change subject: soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num() ...................................................................... soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num() Consolidate all weak declarations of mainboard_get_dram_part_num() to instead use the common definition in lib/spd_bin.c. BUG=b:168724473 TEST="emerge-volteer coreboot && emerge-nocturne coreboot && emerge-dedede coreboot" and verify build succeeds without error. Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/lib/spd_bin.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c 6 files changed, 7 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45890/1 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 3888896..aeed204 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -2,6 +2,7 @@ #include <cbfs.h> #include <console/console.h> +#include <memory_info.h> #include <spd_bin.h> #include <string.h> #include <device/dram/ddr3.h> @@ -17,6 +18,12 @@ } } +const char * __weak mainboard_get_dram_part_num(void) +{ + /* Default weak implementation, no need to override part number. */ + return NULL; +} + static bool use_ddr4_params(int dram_type) { switch (dram_type) { diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 32657c7..6cd22d0 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -21,12 +21,6 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -const char * __weak mainboard_get_dram_part_num(void) -{ - /* Default weak implementation, no need to override part number. */ - return NULL; -} - /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index e8947f1..0bf0404 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -23,12 +23,6 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -const char * __weak mainboard_get_dram_part_num(void) -{ - /* Default weak implementation, no need to override part number. */ - return NULL; -} - /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index 06fa114..ae9cc4a 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -21,12 +21,6 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -const char * __weak mainboard_get_dram_part_num(void) -{ - /* Default implementation, no need to override part number. */ - return NULL; -} - /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 6fddbc4..1fa6c2d 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -21,12 +21,6 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -const char * __weak mainboard_get_dram_part_num(void) -{ - /* Default weak implementation, no need to override part number. */ - return NULL; -} - /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 6fddbc4..1fa6c2d 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -21,12 +21,6 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -const char * __weak mainboard_get_dram_part_num(void) -{ - /* Default weak implementation, no need to override part number. */ - return NULL; -} - /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1 Gerrit-Change-Number: 45890 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020