Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46018 )
Change subject: soc/intel/*: conversion from constant to Kconfig for XTAL frequency
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46018/8//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/46018/8//COMMIT_MSG@9
PS8, Line 9: This converts the constant for the XTAL frequency to a Kconfig option.
> [Motivation missing] […]
The value depends on the soc. No device should override this and thus, it's not a devicetree option.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46017 )
Change subject: src/soc/intel/common/block: add Kconfig for PM Timer emulation support
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Patch Set 6:
> Patch Set 6: Code-Review+1
>
> (1 comment)
>
> I guess this can’t be autodected at runtime.
Since Disabling PM Timer via Kconfig depends on this, it's needed even if we could detect it
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45799 )
Change subject: mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17
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Patch Set 11: Code-Review+2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45798 )
Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
......................................................................
Patch Set 10: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/45798/10/src/soc/intel/xeon_sp/cpx…
File src/soc/intel/xeon_sp/cpx/include/soc/ddr.h:
https://review.coreboot.org/c/coreboot/+/45798/10/src/soc/intel/xeon_sp/cpx…
PS10, Line 7:
Please add a comment stating that these numbers are in picoseconds
https://review.coreboot.org/c/coreboot/+/45798/10/src/soc/intel/xeon_sp/cpx…
PS10, Line 8: #define DDR_800_TCK_MIN 2500
These are equivalent to the definitions in src/include/device/dram/common.h, but expressed in different units. I don't think the definitions in there are precise enough for higher memory speeds, though.
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Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields
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Patch Set 7: Code-Review+2
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45957 )
Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: PM ACPI timer state from Kconfig
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Patch Set 21:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45957/21//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/45957/21//COMMIT_MSG@7
PS21, Line 7: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: PM ACPI timer state from Kconfig
Please make it a statement:
> Set PM ACPI timer state from Kconfig
https://review.coreboot.org/c/coreboot/+/45957/21//COMMIT_MSG@9
PS21, Line 9: devicetree
Kconfig?
https://review.coreboot.org/c/coreboot/+/45957/21/src/soc/intel/elkhartlake…
File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/45957/21/src/soc/intel/elkhartlake…
PS21, Line 64: /* PM ACPI timer */
I’d remove the redundent comment, or add a reference to the requirement (datasheet, spec).
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 )
Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45952/17/src/soc/intel/common/bloc…
File src/soc/intel/common/block/pmc/Kconfig:
https://review.coreboot.org/c/coreboot/+/45952/17/src/soc/intel/common/bloc…
PS17, Line 45: is required for ACPI
It sounds like, if you disable the timer, then ACPI stop working?
https://review.coreboot.org/c/coreboot/+/45952/17/src/soc/intel/common/bloc…
PS17, Line 45: TCO
It’d be great, if you spelt it out once.
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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45799 )
Change subject: mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17
......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45799/5/src/mainboard/ocp/deltalak…
File src/mainboard/ocp/deltalake/ramstage.c:
https://review.coreboot.org/c/coreboot/+/45799/5/src/mainboard/ocp/deltalak…
PS5, Line 246: dimm_locator[dimm->channel_num]
> No, what I'd like to avoid is the character array. […]
Done
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Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
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Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/…
File src/soc/intel/xeon_sp/cpx/romstage.c:
https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/…
PS4, Line 88: 1200
> If the HOB provides this information, why not use it?
Done
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