coreboot-gerrit October 2020

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Change in coreboot[master]: drivers/uart: Override uart base address
by Bryant Ou (Code Review) 09 Nov '20

09 Nov '20

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45405 ) Change subject: drivers/uart: Override uart base address ...................................................................... drivers/uart: Override uart base address Add CONFIG_UART_OVERRIDE_BASE_ADDR to select the function, platform overrides the base address by providing a uart_platform_base routine. Signed-off-by: Bryant Ou <Bryant.Ou.Q(a)gmail.com> Change-Id: I2079bd1e5ffa209553383b6aafe3b8724849ba2a --- M src/drivers/uart/Kconfig M src/drivers/uart/uart8250io.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45405/1 diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 41b870f..9cbb359 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -33,6 +33,13 @@ Set to "y" when the platform overrides the uart_platform_refclk routine. +config UART_OVERRIDE_BASE_ADDR + bool + default n + help + Set to "y" when the platform overrides the base address by providing + a uart_platform_base routine. + config DRIVERS_UART_8250MEM bool default n diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index d0841de..c5317af 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -75,6 +75,7 @@ ENABLE_TRACE; } +#if !CONFIG(UART_OVERRIDE_BASE_ADDR) static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; uintptr_t uart_platform_base(unsigned int idx) @@ -83,6 +84,7 @@ return bases[idx]; return 0; } +#endif void uart_init(unsigned int idx) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2079bd1e5ffa209553383b6aafe3b8724849ba2a Gerrit-Change-Number: 45405 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

9 24

Change in coreboot[master]: mb/google/volteer/eldrid: Describe the privacy_gpio
by Ricardo Ribalda (Code Review) 09 Nov '20

09 Nov '20

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46964 ) Change subject: mb/google/volteer/eldrid: Describe the privacy_gpio ...................................................................... mb/google/volteer/eldrid: Describe the privacy_gpio Add information regarding the privacy pin on the overridetree and the gpio. Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> --- M src/mainboard/google/volteer/variants/eldrid/gpio.c M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 2 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46964/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c index 4f6650b..3d627e3 100644 --- a/src/mainboard/google/volteer/variants/eldrid/gpio.c +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -63,7 +63,7 @@ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* D4 : IMGCLKOUT0# ==> CAMMERA_SWITCH */ - PAD_CFG_GPI(GPP_D4, NONE, DEEP), + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 7fd6576..3efa40c 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -68,6 +68,21 @@ }" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "privacy_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH_ACTIVE_LOW(GPP_D4)" + device usb 3.2 on end + end + end + end + end + device ref dptf on # DPTF Policy for Eldrid board chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/46964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc Gerrit-Change-Number: 46964 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: mb/google/hatch/jinlon: Describe the privacy_gpio
by Ricardo Ribalda (Code Review) 09 Nov '20

09 Nov '20

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46962 ) Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ...................................................................... mb/google/hatch/jinlon: Describe the privacy_gpio Add information regarding the privacy pin on the overridetree and gpio. Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> --- M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46962/1 diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 88f0092..3b6a76f 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -18,6 +18,8 @@ * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* D4 : Camera Privacy Status */ + PAD_CFG_GPI(GPP_D4, NONE, DEEP), /* E0 : View Angle Management */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index fc3bb85..22cc5d3 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -80,6 +80,16 @@ device generic 0 on end end end # Integrated Graphics Device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" + device usb 2.6 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/46962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Gerrit-Change-Number: 46962 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: acpi: Add support for privacy_gpio
by Ricardo Ribalda (Code Review) 09 Nov '20

09 Nov '20

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46961 ) Change subject: acpi: Add support for privacy_gpio ...................................................................... acpi: Add support for privacy_gpio Some devices, such as cameras, can implement a physical switch to disable the input on demand. Think of it like the typical privacy sticker on the notebooks, but more elegant. In order to notify the system about the status this feature, a GPIO is typically used. The map between a GPIO and the feature is done via ACPI, the same way as the reset_gpio works. This patch implements an extra field for the described privacy gpio. This gpio does not require any extra handling from the power management. Change-Id: Idcc65c9a13eca6f076ac3c68aaa1bed3c481df3d Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46961/1 diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 8cd9268..4a55cc6 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -45,6 +45,7 @@ struct acpi_pld custom_pld; struct acpi_gpio reset_gpio; + struct acpi_gpio privacy_gpio; }; #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index d33b7de..9b45483 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -13,10 +13,13 @@ /* * Return false if reset GPIO is not provided. */ - if (cfg->reset_gpio.pin_count == 0) - return false; + if (cfg->reset_gpio.pin_count) + return true; - return true; + if (cfg->privacy_gpio.pin_count) + return true; + + return false; } static void usb_acpi_fill_ssdt_generator(const struct device *dev) @@ -49,15 +52,23 @@ /* Resources */ if (usb_acpi_add_gpios_to_crs(config) == true) { struct acpi_dp *dsd; + int idx = 0; acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); - acpi_device_write_gpio(&config->reset_gpio); + if (config->reset_gpio.pin_count) + acpi_device_write_gpio(&config->reset_gpio); + if (config->privacy_gpio.pin_count) + acpi_device_write_gpio(&config->privacy_gpio); acpigen_write_resourcetemplate_footer(); dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_gpio(dsd, "reset-gpio", path, 0, 0, - config->reset_gpio.active_low); + if (config->reset_gpio.pin_count) + acpi_dp_add_gpio(dsd, "reset-gpio", path, idx++, 0, + config->reset_gpio.active_low); + if (config->privacy_gpio.pin_count) + acpi_dp_add_gpio(dsd, "privacy-gpio", path, idx++, 0, + config->privacy_gpio.active_low); acpi_dp_write(dsd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcc65c9a13eca6f076ac3c68aaa1bed3c481df3d Gerrit-Change-Number: 46961 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: tests: Add lib/timestamp-test test case
by Name of user not set (Code Review) 09 Nov '20

09 Nov '20

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46968 ) Change subject: tests: Add lib/timestamp-test test case ...................................................................... tests: Add lib/timestamp-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I39abfc644fef085cef2175086a0e45a040b244de --- A tests/include/stubs/timestamp.h M tests/lib/Makefile.inc A tests/lib/timestamp-test.c A tests/stubs/timestamp.c 4 files changed, 180 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46968/1 diff --git a/tests/include/stubs/timestamp.h b/tests/include/stubs/timestamp.h new file mode 100644 index 0000000..10b8159 --- /dev/null +++ b/tests/include/stubs/timestamp.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <types.h> + +void dummy_timestamp_set(uint64_t v); + +void dummy_timestamp_tick_freq_mhz_set(int v); diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 3062bca..27773b7 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += imd-test +tests-y += timestamp-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -17,4 +18,9 @@ imd-test-srcs += tests/lib/imd-test.c imd-test-srcs += tests/stubs/console.c -imd-test-srcs += src/lib/imd.c \ No newline at end of file +imd-test-srcs += src/lib/imd.c + +timestamp-test-srcs += tests/lib/timestamp-test.c +timestamp-test-srcs += tests/stubs/timestamp.c +timestamp-test-srcs += tests/stubs/console.c +timestamp-test-stage := romstage diff --git a/tests/lib/timestamp-test.c b/tests/lib/timestamp-test.c new file mode 100644 index 0000000..8dc103d --- /dev/null +++ b/tests/lib/timestamp-test.c @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../lib/timestamp.c" +#include <commonlib/bsd/helpers.h> +#include <tests/test.h> +#include "stubs/timestamp.h" + +/* Timestamp region definition */ +#define TIMESTAMP_REGION_SIZE (1 * KiB) +TEST_REGION(timestamp, TIMESTAMP_REGION_SIZE); + +void test_timestamp_init(void **state) +{ + timestamp_init(1000); + + assert_non_null(glob_ts_table); +} + +void test_timestamp_add(void **state) +{ + const int base_multipler = 2000; + const int timestamp_base = 1000; + struct timestamp_entry *entry; + int i; + + timestamp_init(timestamp_base); + + timestamp_add(TS_START_ROMSTAGE, base_multipler); + + assert_int_equal(1, glob_ts_table->num_entries); + + entry = &glob_ts_table->entries[0]; + assert_int_equal(1, entry->entry_id); + assert_int_equal(base_multipler - timestamp_base, /* Added timestamp reduced by base */ + entry->entry_stamp); + + /* Add few timestamps to check if all of them will be added properly */ + for (i = 1; i < 10; ++i) + timestamp_add(i + 1, base_multipler * (i + 1)); + + assert_int_equal(10, glob_ts_table->num_entries); + + for (i = 0; i < 10; ++i) { + entry = &glob_ts_table->entries[i]; + assert_int_equal(i + 1, entry->entry_id); + assert_int_equal(base_multipler * (i + 1) - timestamp_base, + entry->entry_stamp); + } +} + +void test_timestamp_add_now(void **state) +{ + const int base_multipler = 2000; + const int timestamp_base = 1000; + struct timestamp_entry *entry; + + /* Initialize with base timestamp of 1000. + * This value will be subtracted from each timestamp + * when adding it. + */ + timestamp_init(timestamp_base); + + dummy_timestamp_set(base_multipler); + + timestamp_add_now(TS_START_ROMSTAGE); + + assert_int_equal(1, glob_ts_table->num_entries); + + entry = &glob_ts_table->entries[0]; + + assert_int_equal(1, entry->entry_id); + assert_int_equal(base_multipler - timestamp_base, /* Added timestamp reduced by base */ + entry->entry_stamp); +} + +void test_timestamp_rescale_table(void **state) +{ + const int base_multipler = 1000; + int i; + + timestamp_init(0); + + /* Add few timestamps to check if all of them will be rescaled properly */ + for (i = 1; i <= 10; ++i) + timestamp_add(i, base_multipler * i); + + /* Check if all entries were added to table */ + assert_int_equal(10, glob_ts_table->num_entries); + + timestamp_rescale_table(2, 4); + + /* Check if there is the same number of entries */ + assert_int_equal(10, glob_ts_table->num_entries); + + for (i = 0; i < glob_ts_table->num_entries; ++i) + assert_int_equal(base_multipler * (i + 1) / 4 * 2, + glob_ts_table->entries[i].entry_stamp); +} + +void test_get_us_since_boot(void **state) +{ + const int base_multipler = 10000; + const int timestamp_base = 1000; + const int freq_base = 100; + + timestamp_init(timestamp_base); + dummy_timestamp_set(base_multipler); + dummy_timestamp_tick_freq_mhz_set(freq_base); + /* There is a need to update this field manually, because cbmem hooks are not used. */ + glob_ts_table->tick_freq_mhz = freq_base; + + assert_int_equal((base_multipler - timestamp_base) / freq_base, get_us_since_boot()); +} + +int setup_timestamp_and_freq(void **state) +{ + dummy_timestamp_set(0); + dummy_timestamp_tick_freq_mhz_set(1); + + return 0; +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup(test_timestamp_init, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_add, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_add_now, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_rescale_table, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_get_us_since_boot, setup_timestamp_and_freq), + }; + +#if CONFIG(COLLECT_TIMESTAMPS) + return cmocka_run_group_tests(tests, NULL, NULL); +#else + return 0; +#endif +} diff --git a/tests/stubs/timestamp.c b/tests/stubs/timestamp.c new file mode 100644 index 0000000..3fd739f --- /dev/null +++ b/tests/stubs/timestamp.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "stubs/timestamp.h" + +static uint64_t timestamp_value = 0; +static int timestamp_tick_freq_mhz_value = 1; + +/* Provides way to control timestamp value */ +void dummy_timestamp_set(uint64_t v) +{ + timestamp_value = v; +} + +/* Provides way to control timestamp tick frequency MHz value */ +void dummy_timestamp_tick_freq_mhz_set(int v) +{ + timestamp_tick_freq_mhz_value = v; +} + +/* Reimplementation of timestamp getter to control behaviour */ +uint64_t timestamp_get(void) +{ + return timestamp_value; +} + +int timestamp_tick_freq_mhz(void) +{ + return timestamp_tick_freq_mhz_value; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39abfc644fef085cef2175086a0e45a040b244de Gerrit-Change-Number: 46968 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: intel/common/pmc: Add functions for IPC mailbox in ACPI
by Duncan Laurie (Code Review) 09 Nov '20

09 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46259 ) Change subject: intel/common/pmc: Add functions for IPC mailbox in ACPI ...................................................................... intel/common/pmc: Add functions for IPC mailbox in ACPI This change adds two functions that provide an IPC mailbox method via ACPI for runtime clock configuration. pmc_acpi_fill_ssdt_ipc_write_method() will provide a method in the SSDT that can be called by other ACPI devices to send an IPC mailbox command. This function is exported because some SOCs override the default PMC device and need to call this function to write the method into the SSDT. pmc_acpi_set_pci_clock() will call the method defined by the previous function to enable or disable the PCIe SRCCLK for a specified root port and clock pin. It can be called by the PCIe root port after turning off power to the attached device. BUG=b:160996445 TEST=boot on volteer device and disassemble the SSDT to ensure that this method exists. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I95f5a1ba2bc6905e0f8ce0e8b2342ad1287a23a0 --- M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmc.c 3 files changed, 175 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46259/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 75e2127..b70d4dd 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -60,4 +60,27 @@ */ const struct device *soc_get_pmc_mux_device(int port_number); +/* + * Provides an ACPI method in the SSDT to write to the IPC mailbox which is + * defined in the PMC device MMIO address space. + * + * One possible use of this method is to to enable/disable the clock for a + * particular PCIe root port at runtime when the device is in D3 state. + * + * The ACPI method takes 7 arguments: + * IPCW (COMMAND, SUB_ID, SIZE, DATA0, DATA1, DATA2, DATA3) + * + * And can return: + * 0 = success + * 1 = error + * 2 = timeout + */ +void pmc_acpi_fill_ssdt_ipc_write_method(void); + +/* + * Call the ACPI method to write to the IPC mailbox and enable/disable the + * specified clock pin connected to the specified PCIe root port. + */ +void pmc_acpi_set_pci_clock(unsigned int pcie_rp, unsigned int clock_pin, bool enable); + #endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index ce41b23..cb6d888 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -13,6 +13,14 @@ config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y +config PMC_IPC_MAILBOX_ACPI_INTERFACE + bool + default n + depends on HAVE_ACPI_TABLES + help + Enable this to have the PMC IPC mailbox ACPI interface added + to the SSDT for use by other drivers. + endif # SOC_INTEL_COMMON_BLOCK_PMC config PMC_INVALID_READ_AFTER_WRITE diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 24f28e3..76eaddb 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> @@ -9,6 +10,16 @@ #include <device/pci_ids.h> #include <intelblocks/pmc.h> #include <soc/pci_devs.h> +#include <soc/iomap.h> + +/* PMC IPC Mailbox Interface. */ +#define PMC_IPC_CMD 0x00 /* IPC command */ +#define PMC_IPC_CMD_OFFSET_COMMAND 0 /* IPC command.COMMAND */ +#define PMC_IPC_CMD_OFFSET_SUB_ID 12 /* IPC command.SUB_ID */ +#define PMC_IPC_CMD_OFFSET_SIZE 16 /* IPC command.SIZE */ +#define PMC_IPC_CMD_SET_PCIE_CLOCK 0xAC /* IPC command: Set PCIe Clock */ +#define PMC_IPC_STS 0x04 /* IPC Status */ +#define PMC_IPC_WBUF 0x80 /* IPC Write Buffer */ /* SoC overrides */ @@ -98,6 +109,138 @@ } } +void pmc_acpi_fill_ssdt_ipc_write_method(void) +{ + const struct fieldlist ipcw_fields[] = { + FIELDLIST_OFFSET(PMC_IPC_CMD), /* Command */ + FIELDLIST_NAMESTR("ICMD", 32), /* Command Register */ + FIELDLIST_OFFSET(PMC_IPC_STS), /* Status */ + FIELDLIST_NAMESTR("IBSY", 1), /* Status Busy */ + FIELDLIST_NAMESTR("IERR", 1), /* Status Error */ + FIELDLIST_OFFSET(PMC_IPC_WBUF), /* Write Buffer */ + FIELDLIST_NAMESTR("IWB0", 32), /* Write Buffer 0 */ + FIELDLIST_NAMESTR("IWB1", 32), /* Write Buffer 1 */ + FIELDLIST_NAMESTR("IWB2", 32), /* Write Buffer 2 */ + FIELDLIST_NAMESTR("IWB3", 32), /* Write Buffer 3 */ + }; + const struct opregion ipcw_opregion = OPREGION("IPCS", SYSTEMMEMORY, + PCH_PWRM_BASE_ADDRESS, 0xff); + + if (!CONFIG(CONFIG_PMC_IPC_MAILBOX_ACPI_INTERFACE)) + return; + + acpigen_write_method_serialized("IPCW", 7); + + acpigen_write_opregion(&ipcw_opregion); + acpigen_write_field("IPCS", ipcw_fields, ARRAY_SIZE(ipcw_fields), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); + + /* Fill write buffer data registers. */ + acpigen_write_store_op_to_namestr(ARG3_OP, "IWB0"); + acpigen_write_store_op_to_namestr(ARG4_OP, "IWB1"); + acpigen_write_store_op_to_namestr(ARG5_OP, "IWB2"); + acpigen_write_store_op_to_namestr(ARG6_OP, "IWB3"); + + /* Program the command register with command and size of write data. */ + acpigen_write_store_int_to_op(0, LOCAL0_OP); + + /* Local0 += (Arg0 << PMC_IPC_CMD_OFFSET_COMMAND) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG0_OP, PMC_IPC_CMD_OFFSET_COMMAND); + acpigen_emit_byte(LOCAL0_OP); + + /* Local0 += (Arg1 << PMC_IPC_CMD_OFFSET_SUB_ID) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG1_OP, PMC_IPC_CMD_OFFSET_SUB_ID); + acpigen_emit_byte(LOCAL0_OP); + + /* Local0 += (Arg1 << PMC_IPC_CMD_OFFSET_SIZE) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG2_OP, PMC_IPC_CMD_OFFSET_SIZE); + acpigen_emit_byte(LOCAL0_OP); + + /* Start mailbox command with one 32bit write. */ + acpigen_write_store_op_to_namestr(LOCAL0_OP, "ICMD"); + + /* Read status register to get busy/error status for up to 10ms. */ + acpigen_write_store_int_to_op(10, LOCAL1_OP); + + /* While (Local0 > 0) */ + acpigen_emit_byte(WHILE_OP); + acpigen_write_len_f(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_emit_byte(ZERO_OP); + /* If (IBSY == 0) { Return (SUCCESS) } */ + acpigen_write_if_lequal_namestr_int("IBSY", 0); + acpigen_write_return_integer(0); + acpigen_pop_len(); + /* If (IERR == 1) { Return (ERROR) } */ + acpigen_write_if_lequal_namestr_int("IERR", 1); + acpigen_write_return_integer(1); + acpigen_pop_len(); + /* Sleep (1) */ + acpigen_write_sleep(1); + /* Decrement (Local0) */ + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_pop_len(); /* While */ + /* Return (TIMEOUT) */ + acpigen_write_return_integer(2); + + acpigen_pop_len(); /* Method */ +} + +void pmc_acpi_set_pci_clock(unsigned int pcie_rp, unsigned int clock_pin, bool enable) +{ + const uint32_t data[] = { + 1 << clock_pin, /* Clock pin to be modified */ + (enable ? 0 : 1) << clock_pin, /* Clock pin to set */ + 1 << pcie_rp, /* PCIe root port to be modified */ + (enable ? 0 : 1) << pcie_rp, /* PCIe root port to set */ + }; + const char *method = acpi_device_path_join(pcidev_path_on_root(PCH_DEVFN_PMC), "IPCW"); + + if (!CONFIG(CONFIG_PMC_IPC_MAILBOX_ACPI_INTERFACE)) + return; + + if (!method) { + printk(BIOS_ERR, "%s: Unable to find PMC device IPCW method\n", __func__); + return; + } + + /* + * The PMC IPC mailbox write method takes 7 arguments: + * IPCW (COMMAND, SUB_ID, SIZE, DATA0, DATA1, DATA2, DATA3) + */ + acpigen_emit_namestring(method); + acpigen_write_integer(PMC_IPC_CMD_SET_PCIE_CLOCK); + acpigen_write_integer(0); + acpigen_write_integer(sizeof(data)); + acpigen_write_integer(data[0]); + acpigen_write_integer(data[1]); + acpigen_write_integer(data[2]); + acpigen_write_integer(data[3]); +} + +static void pmc_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + + if (!scope) + return; + + acpigen_write_scope(scope); + + /* Define IPC Write Method */ + pmc_acpi_fill_ssdt_ipc_write_method(); + + acpigen_pop_len(); /* Scope */ +} + static struct device_operations device_ops = { .read_resources = pch_pmc_read_resources, .set_resources = pci_dev_set_resources, @@ -105,6 +248,7 @@ .init = pmc_soc_init, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus, + .acpi_fill_ssdt = pmc_fill_ssdt, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95f5a1ba2bc6905e0f8ce0e8b2342ad1287a23a0 Gerrit-Change-Number: 46259 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 17

Change in coreboot[master]: mb/google/volteer: Skip TPM detection except on SPI
by Jes Klinke (Code Review) 09 Nov '20

09 Nov '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47049 to review the following change. Change subject: mb/google/volteer: Skip TPM detection except on SPI ...................................................................... mb/google/volteer: Skip TPM detection except on SPI Production Volteer devices have Cr50 TPM connected via SPI, depending on Cr50 firmware version it may or may not support long enough interrupt pulses for the SoC to safely be able to enable lowest power mode. Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced with Dauntless, communicating via I2C. The I2C drivers do not support being accessed early in ramstage, before chip init and memory mapping, (tlcl_lib_init() will halt with an error finding the I2C controlled base address.) Since the Dauntless device under development can be made to support longer interrupts, or a completely new interrupt signalling mode, there is no need to try to go through the same discovery as is done via SPI. This CL will skip the discovery, enabling the S0i3.4 sleep mode in all cases, on the reworked test devices. BUG=b:169526865 TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce Signed-off-by: Jes Bodi Klinke <jbk(a)chromium.org> --- M 3rdparty/amd_blobs M src/mainboard/google/volteer/mainboard.c 2 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47049/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 8c668ab..e393a88 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 8c668ab552a02724a07f8c6e7285a5f21a61569b +Subproject commit e393a885c89f8ee3f05242a9e42578c60931b49d diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index b4d6676..480a3f6 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -45,13 +45,24 @@ void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) { int ret; + if (!CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) { + /* + * Negotiation of long interrupt pulses is only supported via + * SPI. I2C is only used on reworked prototypes on which the + * TPM is replaced with Dauntless under development, it will + * use long pulses by default, or use the interrupt line in a + * different way altogether. + */ + return; + } + ret = tlcl_lib_init(); if (ret != VB2_SUCCESS) { printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); return; } - if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) { + if (cr50_is_long_interrupt_pulse_enabled()) { printk(BIOS_INFO, "Enabling S0i3.4\n"); } else { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce Gerrit-Change-Number: 47049 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

6 20

Change in coreboot[4.11_branch]: sec/intel/txt/Kconfig: Remove the menu for including ACMs
by Angel Pons (Code Review) 08 Nov '20

08 Nov '20

Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45003 to review the following change. Change subject: sec/intel/txt/Kconfig: Remove the menu for including ACMs ...................................................................... sec/intel/txt/Kconfig: Remove the menu for including ACMs This is consistent with how other binaries (e.g. FSP) are added via Kconfig. This also makes it more visible that things need to be configured. Change-Id: I399de6270cc4c0ab3b8c8a9543aec0d68d3cfc03 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/txt/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/45003/1 diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index d828a9d..049705f 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -26,8 +26,6 @@ if INTEL_TXT -menu "Intel" - config INTEL_TXT_BIOSACM_FILE string "BIOS ACM file" default "3rdparty/blobs/soc/intel/fsp_broadwell_de/biosacm.bin" if SOC_INTEL_FSP_BROADWELL_DE @@ -71,6 +69,4 @@ string default "txt_sinit_acm.bin" -endmenu # Intel - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I399de6270cc4c0ab3b8c8a9543aec0d68d3cfc03 Gerrit-Change-Number: 45003 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function
by Angel Pons (Code Review) 07 Nov '20

07 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47042 ) Change subject: sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function ...................................................................... sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function Change-Id: I957556bcb3f2d793ed2d9a9c966b2081f9be090c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/47042/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 2e4dcd0..373bafc 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -73,6 +73,25 @@ #endif } +static void enable_hpet(struct device *const dev) +{ + u32 reg32; + size_t i; + + /* Assign unique bus/dev/fn for each HPET */ + for (i = 0; i < 8; ++i) + pci_write_config16(dev, LPC_HnBDF(i), + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); + + /* Move HPET to default address 0xfed00000 and enable it */ + reg32 = RCBA32(HPTC); + reg32 |= (1 << 7); // HPET Address Enable + reg32 &= ~(3 << 0); + RCBA32(HPTC) = reg32; + /* Read it back to stick. It's affected by posted write syndrome. */ + RCBA32(HPTC); +} + /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved @@ -359,25 +378,6 @@ RCBA32_OR(0x33c8, (1 << 15)); } -static void enable_hpet(struct device *const dev) -{ - u32 reg32; - size_t i; - - /* Assign unique bus/dev/fn for each HPET */ - for (i = 0; i < 8; ++i) - pci_write_config16(dev, LPC_HnBDF(i), - PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); - - /* Move HPET to default address 0xfed00000 and enable it */ - reg32 = RCBA32(HPTC); - reg32 |= (1 << 7); // HPET Address Enable - reg32 &= ~(3 << 0); - RCBA32(HPTC) = reg32; - /* Read it back to stick. It's affected by posted write syndrome. */ - RCBA32(HPTC); -} - static void enable_clock_gating(struct device *dev) { /* LynxPoint Mobile */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I957556bcb3f2d793ed2d9a9c966b2081f9be090c Gerrit-Change-Number: 47042 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Correct GPI routing check
by Angel Pons (Code Review) 07 Nov '20

07 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47044 ) Change subject: sb/intel/lynxpoint/lpc.c: Correct GPI routing check ...................................................................... sb/intel/lynxpoint/lpc.c: Correct GPI routing check Code does not match comment, but this time the comment is right. Change-Id: I4e277a802c68c8a4e858b2e33e7ec69b41dd9773 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/47044/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ee0dc53..1845273 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -265,7 +265,7 @@ * Set the board's GPI routing on LynxPoint-H. * This is done as part of GPIO configuration on LynxPoint-LP. */ - if (pch_is_lp()) + if (!pch_is_lp()) pch_gpi_routing(dev, config); /* GPE setup based on device tree configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e277a802c68c8a4e858b2e33e7ec69b41dd9773 Gerrit-Change-Number: 47044 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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